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.github/workflows/ci.yml

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uses: actions/setup-python@v5
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with:
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python-version: '3.x'
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- name: install libcairo-dev
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run: sudo apt install -y libcairo-dev
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- name: install packages
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run: pip install -r tools/rst2pdf/requirements.txt
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- name: check .rst document syntax

CONTRIBUTING.md

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[Morello Descriptor ABI for the Arm 64-bit Architecture](https://github.com/ARM-software/abi-aa/tree/master/descabi-morello) | Silviu Baranga | @sbaranga-arm
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[Memtag ABI Extension to ELF for the Arm 64-bit Architecture](https://github.com/ARM-software/abi-aa/tree/master/memtagabielf64) | Florian Mayer | @fmayer
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[C/C++ Atomics Application Binary Interface Standard for the Arm 64-bit Architecture](https://github.com/ARM-software/abi-aa/tree/master/atomicsabi64) | Luke Geeson | @lukeg101
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[AArch64 ELF Conventions for Binary Analysis](https://github.com/ARM-software/abi-aa/tree/main/baabielf64) | Pavel Iliin | @ilinpv
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3. Merging the change
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atomicsabi64/atomicsabi64.rst

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@@ -379,6 +379,15 @@ Suggestions and improvements to this specification may be submitted to the:
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`issue tracker page on GitHub <https://github.com/ARM-software/abi-aa/issues>`_.
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Atomic types
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============
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``_Atomic`` struct types types with size less than 16 bytes must be padded to the nearest power
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of 2. Their alignment must be the same as their size so that they can be used by atomic instructions.
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``atomic_is_lock_free`` must return ``true`` for all ``_Atomic`` objects with size less than or equal
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to 16 bytes, and ``false`` otherwise.
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AArch64 atomic mappings
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=======================
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+-----------------------------------------------------+--------------------------------------+
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| ``atomic_thread_fence(release)`` | .. code-block:: none |
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| | |
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| ``atomic_thread_fence(acq_rel)`` | DMB ISH |
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| | DMB ISHLD |
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| | DMB ISHST |
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| +--------------------------------------+
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| | .. code-block:: none |
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| | |
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| ``atomic_thread_fence(seq_cst)`` | |
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+-------------------------------------+---------------+--------------------------------------+
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| | DMB ISH |
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+-----------------------------------------------------+--------------------------------------+
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| ``atomic_thread_fence(acq_rel)`` | .. code-block:: none |
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| | |
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| ``atomic_thread_fence(seq_cst)`` | DMB ISH |
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+-----------------------------------------------------+--------------------------------------+
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The release fence has two alternative implementations. Using ``DMB ISHLD`` and ``DMB ISHST``
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allows for more reordering since the combination is not a store-load barrier.
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32-bit types
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------------
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| +---------------+--------------------------------------+
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| | ``FEAT_LSE`` | .. code-block:: none |
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| | | |
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| | | SWAL W2, W0, [X1] * |
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| | | SWPAL W2, W0, [X1] * |
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+-------------------------------------+---------------+--------------------------------------+
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| ``fetch_add(loc,val,relaxed)`` | ``Armv8-A`` | .. code-block:: none |
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| | | |
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| +---------------+--------------------------------------+
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| | ``FEAT_LSE`` | .. code-block:: none |
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| | | |
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| | | LDADD W0, W2, [X1] * |
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| | | LDADD W2, W0, [X1] * |
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+-------------------------------------+---------------+--------------------------------------+
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| ``fetch_add(loc,val,acquire)`` | ``Armv8-A`` | .. code-block:: none |
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| | | |
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| +---------------+--------------------------------------+
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| | ``FEAT_LSE`` | .. code-block:: none |
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| | | |
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| | | LDADDA W0, W2, [X1] * |
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| | | LDADDA W2, W0, [X1] * |
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+-------------------------------------+---------------+--------------------------------------+
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| ``fetch_add(loc,val,release)`` | ``Armv8-A`` | .. code-block:: none |
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| | | |
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| +---------------+--------------------------------------+
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| | ``FEAT_LSE`` | .. code-block:: none |
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| | | |
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| | | LDADDL W0, W2, [X1] * |
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| | | LDADDL W2, W0, [X1] * |
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+-------------------------------------+---------------+--------------------------------------+
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| ``fetch_add(loc,val,acq_rel)`` | ``Armv8-A`` | .. code-block:: none |
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| ``fetch_add(loc,val,seq_cst)`` | | |
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| +---------------+--------------------------------------+
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| | ``FEAT_LSE`` | .. code-block:: none |
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| | | |
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| | | LDADDAL W0, W2, [X1] * |
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| | | LDADDAL W2, W0, [X1] * |
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+-------------------------------------+---------------+--------------------------------------+
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| ``compare_exchange_strong(`` | ``Armv8-A`` | .. code-block:: none |
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| ``loc,exp,val,relaxed,relaxed)`` | | |
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| +---------------+--------------------------------------+
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| |``FEAT_LRCPC3``| .. code-block:: none |
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| | | |
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| | | STILP x2, X3, [X4] |
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| | | STILP X2, X3, [X4] |
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+-------------------------------------+---------------+--------------------------------------+
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| ``load(loc,relaxed)`` | ``Armv8-A`` | .. code-block:: none |
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| | | |

baabielf64/Arm_logo_blue_RGB.svg

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baabielf64/CONTRIBUTIONS

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Contributions to this project are licensed under an inbound=outbound
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model such that any such contributions are licensed by the contributor
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under the same terms as those in the LICENSE file.

baabielf64/LICENSE

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This work is licensed under the Creative Commons
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Attribution-ShareAlike 4.0 International License. To view a copy of
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this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or
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send a letter to Creative Commons, PO Box 1866, Mountain View, CA
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94042, USA.
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Grant of Patent License. Subject to the terms and conditions of this
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license (both the Public License and this Patent License), each
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Licensor hereby grants to You a perpetual, worldwide, non-exclusive,
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no-charge, royalty-free, irrevocable (except as stated in this
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section) patent license to make, have made, use, offer to sell, sell,
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import, and otherwise transfer the Licensed Material, where such
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license applies only to those patent claims licensable by such
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Licensor that are necessarily infringed by their contribution(s) alone
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or by combination of their contribution(s) with the Licensed Material
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to which such contribution(s) was submitted. If You institute patent
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litigation against any entity (including a cross-claim or counterclaim
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in a lawsuit) alleging that the Licensed Material or a contribution
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incorporated within the Licensed Material constitutes direct or
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contributory patent infringement, then any licenses granted to You
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under this license for that Licensed Material shall terminate as of
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the date such litigation is filed.

baabielf64/README.md

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<div align="center">
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<img src="Arm_logo_blue_RGB.svg" />
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</div>
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# AArch64 ELF Conventions for Binary Analysis
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## About this document
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The [AArch64 ELF Conventions for Binary Analysis](baabielf64.rst) specifies code-patterns recognised by Binary Analysis tools.
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## About the license
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As identified more fully in the [LICENSE](LICENSE) file, this project
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is licensed under CC-BY-SA-4.0 along with an additional patent
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license. The language in the additional patent license is largely
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identical to that in Apache-2.0 (specifically, Section 3 of Apache-2.0
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as reflected at https://www.apache.org/licenses/LICENSE-2.0) with two
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exceptions.
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First, several changes were made related to the defined terms so as to
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reflect the fact that such defined terms need to align with the
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terminology in CC-BY-SA-4.0 rather than Apache-2.0 (e.g., changing
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“Work” to “Licensed Material”).
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Second, the defensive termination clause was changed such that the
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scope of defensive termination applies to “any licenses granted to
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You” (rather than “any patent licenses granted to You”). This change
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is intended to help maintain a healthy ecosystem by providing
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additional protection to the community against patent litigation
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claims.
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## Defects report
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Please report defects in the [AArch64 ELF Conventions for Binary Analysis](baabielf64.rst) to the [issue tracker page on
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GitHub](https://github.com/ARM-software/abi-aa/issues).

baabielf64/TRADEMARK_NOTICE

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The text of and illustrations in this document are licensed
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under a Creative Commons Attribution–Share Alike 4.0 International
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license ("CC-BY-SA-4.0”), with an additional clause on patents.
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The Arm trademarks featured here are registered trademarks or
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trademarks of Arm Limited (or its subsidiaries) in the US and/or
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elsewhere. All rights reserved. Please visit
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https://www.arm.com/company/policies/trademarks for more information
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about Arm’s trademarks.

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