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FriedrichWuFriedrichWu
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Merge pull request #1 from FriedrichWu/dev_supply_fix
Dev supply fix
2 parents 7ec4073 + a0ff83c commit 2ff7833

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16 files changed

+2001
-91
lines changed

16 files changed

+2001
-91
lines changed

‎.gitlab-ci.yml

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
default:
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image: ubuntu:latest
3+
before_script:
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- apt-get update && apt-get install -y git wget make gcc curl
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- git checkout ci_test
6+
- git pull origin ci_test
7+
- chmod +x ./install_conda.sh
8+
- ./install_conda.sh
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- echo "export OPENRAM_HOME="/builds/asic_non_nda/openramenhanced/compiler"" >> ~/.bashrc
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- echo "export OPENRAM_TECH="/builds/asic_non_nda/openramenhance/technology"" >> ~/.bashrc
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- echo "export PYTHONPATH=$OPENRAM_HOME" >> ~/.bashrc
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- source ~/.bashrc
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- source miniconda/bin/activate
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- make sky130-pdk
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- make sky130-install
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script:
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- pwd
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- cd ./macros
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- make sky130_sram_1rw_tiny
20+

‎compiler/base/channel_route.py

Lines changed: 287 additions & 6 deletions
Large diffs are not rendered by default.

‎compiler/base/hierarchy_layout.py

Lines changed: 81 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1913,6 +1913,42 @@ def add_io_pin(self, instance, pin_name, new_name, start_layer=None, directions=
19131913
# Just use the power pin function for now to save code
19141914
self.add_power_pin(new_name, pin.center(), start_layer=start_layer, directions=directions)
19151915

1916+
def add_power_pin_m2(self, name, loc, directions=None, start_layer="m1"):
1917+
# same function like normal one, but add power pin at m2
1918+
# Hack for min area
1919+
if OPTS.tech_name == "sky130":
1920+
min_area = drc["minarea_{}".format(self.pwr_grid_layers[1])]
1921+
width = round_to_grid(sqrt(min_area))
1922+
height = round_to_grid(min_area / width)
1923+
else:
1924+
width = None
1925+
height = None
1926+
1927+
pin = None
1928+
if start_layer == "m2":
1929+
pin = self.add_layout_pin_rect_center(text=name,
1930+
layer=start_layer,
1931+
offset=loc,
1932+
width=width,
1933+
height=height)
1934+
else:
1935+
via = self.add_via_stack_center(from_layer=start_layer,
1936+
to_layer="m2",
1937+
offset=loc,
1938+
directions=directions)
1939+
1940+
if not width:
1941+
width = via.width
1942+
if not height:
1943+
height = via.height
1944+
pin = self.add_layout_pin_rect_center(text=name,
1945+
layer="m2",
1946+
offset=loc,
1947+
width=width,
1948+
height=height)
1949+
1950+
return pin
1951+
19161952
def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
19171953
# Hack for min area
19181954
if OPTS.tech_name == "sky130":
@@ -2027,7 +2063,7 @@ def add_perimeter_pin(self, name, pin, side, bbox):
20272063
layer=layer,
20282064
offset=peri_pin_loc)
20292065

2030-
def add_dnwell(self, bbox=None, inflate=1):
2066+
def add_dnwell(self, bbox=None, inflate=1, route_option="classic"):
20312067
""" Create a dnwell, along with nwell moat at border. """
20322068

20332069
if "dnwell" not in tech_layer:
@@ -2049,11 +2085,20 @@ def add_dnwell(self, bbox=None, inflate=1):
20492085
ul = vector(ll.x, ur.y)
20502086
lr = vector(ur.x, ll.y)
20512087

2052-
# Add the dnwell
2053-
self.add_rect("dnwell",
2054-
offset=ll,
2055-
height=ur.y - ll.y,
2056-
width=ur.x - ll.x)
2088+
# Hack for sky130 klayout drc rule nwell.6
2089+
if OPTS.tech_name == "sky130":
2090+
# Apply the drc rule
2091+
# Add the dnwell
2092+
self.add_rect("dnwell",
2093+
offset=ll - vector(0.5 * self.nwell_width, 0.5 * self.nwell_width) - vector(drc["minclosure_nwell_by_dnwell"], drc["minclosure_nwell_by_dnwell"]),
2094+
height=ur.y - ll.y + self.nwell_width + 2 * drc["minclosure_nwell_by_dnwell"],
2095+
width=ur.x - ll.x + self.nwell_width + 2 * drc["minclosure_nwell_by_dnwell"])
2096+
else: # other tech
2097+
# Add the dnwell
2098+
self.add_rect("dnwell",
2099+
offset=ll,
2100+
height=ur.y - ll.y,
2101+
width=ur.x - ll.x)
20572102

20582103
# Add the moat
20592104
self.add_path("nwell", [ll, lr, ur, ul, ll - vector(0, 0.5 * self.nwell_width)])
@@ -2063,9 +2108,9 @@ def add_dnwell(self, bbox=None, inflate=1):
20632108
tap_spacing = 2
20642109
nwell_offset = vector(self.nwell_width, self.nwell_width)
20652110

2066-
# Every nth tap is connected to gnd
2111+
# Every nth tap is connected to vdd
20672112
period = 5
2068-
2113+
moat_pins = []
20692114
# BOTTOM
20702115
count = 0
20712116
loc = ll + nwell_offset.scale(tap_spacing, 0)
@@ -2080,9 +2125,10 @@ def add_dnwell(self, bbox=None, inflate=1):
20802125
to_layer="m1",
20812126
offset=loc)
20822127
else:
2083-
self.add_power_pin(name="vdd",
2084-
loc=loc,
2085-
start_layer="li")
2128+
pin = self.add_power_pin(name="vdd",
2129+
loc=loc,
2130+
start_layer="li")
2131+
moat_pins.append(pin)
20862132
count += 1
20872133
loc += nwell_offset.scale(tap_spacing, 0)
20882134

@@ -2100,9 +2146,10 @@ def add_dnwell(self, bbox=None, inflate=1):
21002146
to_layer="m1",
21012147
offset=loc)
21022148
else:
2103-
self.add_power_pin(name="vdd",
2104-
loc=loc,
2105-
start_layer="li")
2149+
pin = self.add_power_pin(name="vdd",
2150+
loc=loc,
2151+
start_layer="li")
2152+
moat_pins.append(pin)
21062153
count += 1
21072154
loc += nwell_offset.scale(tap_spacing, 0)
21082155

@@ -2120,9 +2167,15 @@ def add_dnwell(self, bbox=None, inflate=1):
21202167
to_layer="m2",
21212168
offset=loc)
21222169
else:
2123-
self.add_power_pin(name="vdd",
2124-
loc=loc,
2125-
start_layer="li")
2170+
if route_option == "classic":
2171+
pin = self.add_power_pin(name="vdd",
2172+
loc=loc,
2173+
start_layer="li")
2174+
elif route_option == "quality":
2175+
pin = self.add_power_pin_m2(name="vdd",
2176+
loc=loc,
2177+
start_layer="li")
2178+
moat_pins.append(pin)
21262179
count += 1
21272180
loc += nwell_offset.scale(0, tap_spacing)
21282181

@@ -2140,14 +2193,21 @@ def add_dnwell(self, bbox=None, inflate=1):
21402193
to_layer="m2",
21412194
offset=loc)
21422195
else:
2143-
self.add_power_pin(name="vdd",
2144-
loc=loc,
2145-
start_layer="li")
2196+
if route_option == "classic":
2197+
pin = self.add_power_pin(name="vdd",
2198+
loc=loc,
2199+
start_layer="li")
2200+
elif route_option == "quality":
2201+
pin = self.add_power_pin_m2(name="vdd",
2202+
loc=loc,
2203+
start_layer="li")
2204+
moat_pins.append(pin)
21462205
count += 1
21472206
loc += nwell_offset.scale(0, tap_spacing)
21482207

2149-
# Add the gnd ring
2208+
# Add the vdd ring
21502209
self.add_ring([ll, ur])
2210+
return moat_pins
21512211

21522212
def add_ring(self, bbox=None, width_mult=8, offset=0):
21532213
"""

‎compiler/gdsMill/gdsMill/vlsiLayout.py

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -742,6 +742,9 @@ def getAllPinShapes(self, pin_name):
742742
Search for a pin label and return ALL the enclosing rectangles on the same layer
743743
as the pin label.
744744
"""
745+
#debug
746+
for pin in self.pins:
747+
print(pin)
745748
shape_list = []
746749
pin_map = self.pins[pin_name]
747750
for pin_list in pin_map:

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