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Merged main:51c351f49ed1 into amd-gfx:bedf99a6863a
Local branch amd-gfx bedf99a Merged main:3f743fd3a319 into amd-gfx:fa9cd7924a4e Remote branch main 51c351f [X86][MC] Support decoding of EGPR for APX (llvm#72102)
2 parents bedf99a + 51c351f commit 565b3cd

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-180
lines changed

14 files changed

+1110
-180
lines changed

‎clang/include/clang/Basic/RISCVVTypes.def

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -452,6 +452,62 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2x4_t", RvvFloat64m2x4, RvvFloat64m2x4Ty, 2
452452

453453
RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4x2_t", RvvFloat64m4x2, RvvFloat64m4x2Ty, 4, 64, 2)
454454

455+
//===- BFloat16 tuple types -------------------------------------------------===//
456+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x2_t", RvvBFloat16mf4x2, RvvBFloat16mf4x2Ty,
457+
1, 16, 2)
458+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x3_t", RvvBFloat16mf4x3, RvvBFloat16mf4x3Ty,
459+
1, 16, 3)
460+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x4_t", RvvBFloat16mf4x4, RvvBFloat16mf4x4Ty,
461+
1, 16, 4)
462+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x5_t", RvvBFloat16mf4x5, RvvBFloat16mf4x5Ty,
463+
1, 16, 5)
464+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x6_t", RvvBFloat16mf4x6, RvvBFloat16mf4x6Ty,
465+
1, 16, 6)
466+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x7_t", RvvBFloat16mf4x7, RvvBFloat16mf4x7Ty,
467+
1, 16, 7)
468+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4x8_t", RvvBFloat16mf4x8, RvvBFloat16mf4x8Ty,
469+
1, 16, 8)
470+
471+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x2_t", RvvBFloat16mf2x2, RvvBFloat16mf2x2Ty,
472+
2, 16, 2)
473+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x3_t", RvvBFloat16mf2x3, RvvBFloat16mf2x3Ty,
474+
2, 16, 3)
475+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x4_t", RvvBFloat16mf2x4, RvvBFloat16mf2x4Ty,
476+
2, 16, 4)
477+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x5_t", RvvBFloat16mf2x5, RvvBFloat16mf2x5Ty,
478+
2, 16, 5)
479+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x6_t", RvvBFloat16mf2x6, RvvBFloat16mf2x6Ty,
480+
2, 16, 6)
481+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x7_t", RvvBFloat16mf2x7, RvvBFloat16mf2x7Ty,
482+
2, 16, 7)
483+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2x8_t", RvvBFloat16mf2x8, RvvBFloat16mf2x8Ty,
484+
2, 16, 8)
485+
486+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x2_t", RvvBFloat16m1x2, RvvBFloat16m1x2Ty,
487+
4, 16, 2)
488+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x3_t", RvvBFloat16m1x3, RvvBFloat16m1x3Ty,
489+
4, 16, 3)
490+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x4_t", RvvBFloat16m1x4, RvvBFloat16m1x4Ty,
491+
4, 16, 4)
492+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x5_t", RvvBFloat16m1x5, RvvBFloat16m1x5Ty,
493+
4, 16, 5)
494+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x6_t", RvvBFloat16m1x6, RvvBFloat16m1x6Ty,
495+
4, 16, 6)
496+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x7_t", RvvBFloat16m1x7, RvvBFloat16m1x7Ty,
497+
4, 16, 7)
498+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m1x8_t", RvvBFloat16m1x8, RvvBFloat16m1x8Ty,
499+
4, 16, 8)
500+
501+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x2_t", RvvBFloat16m2x2, RvvBFloat16m2x2Ty,
502+
8, 16, 2)
503+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x3_t", RvvBFloat16m2x3, RvvBFloat16m2x3Ty,
504+
8, 16, 3)
505+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x4_t", RvvBFloat16m2x4, RvvBFloat16m2x4Ty,
506+
8, 16, 4)
507+
508+
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m4x2_t", RvvBFloat16m4x2, RvvBFloat16m4x2Ty,
509+
16, 16, 2)
510+
455511
#undef RVV_VECTOR_TYPE_BFLOAT
456512
#undef RVV_VECTOR_TYPE_FLOAT
457513
#undef RVV_VECTOR_TYPE_INT

‎clang/include/clang/Serialization/ASTBitCodes.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
11011101
///
11021102
/// Type IDs for non-predefined types will start at
11031103
/// NUM_PREDEF_TYPE_IDs.
1104-
const unsigned NUM_PREDEF_TYPE_IDS = 500;
1104+
const unsigned NUM_PREDEF_TYPE_IDS = 600;
11051105

11061106
// Ensure we do not overrun the predefined types we reserved
11071107
// in the enum PredefinedTypeIDs above.

‎clang/include/clang/Support/RISCVVIntrinsicUtils.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,13 +97,14 @@ enum class TypeModifier : uint8_t {
9797
UnsignedInteger = 1 << 3,
9898
SignedInteger = 1 << 4,
9999
Float = 1 << 5,
100+
BFloat = 1 << 6,
100101
// LMUL1 should be kind of VectorTypeModifier, but that might come with
101102
// Widening2XVector for widening reduction.
102103
// However that might require VectorTypeModifier become bitmask rather than
103104
// simple enum, so we decide keek LMUL1 in TypeModifier for code size
104105
// optimization of clang binary size.
105-
LMUL1 = 1 << 6,
106-
MaxOffset = 6,
106+
LMUL1 = 1 << 7,
107+
MaxOffset = 7,
107108
LLVM_MARK_AS_BITMASK_ENUM(LMUL1),
108109
};
109110

‎clang/lib/Support/RISCVVIntrinsicUtils.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -857,6 +857,9 @@ void RVVType::applyModifier(const PrototypeDescriptor &Transformer) {
857857
case TypeModifier::Float:
858858
ScalarType = ScalarTypeKind::Float;
859859
break;
860+
case TypeModifier::BFloat:
861+
ScalarType = ScalarTypeKind::BFloat;
862+
break;
860863
case TypeModifier::LMUL1:
861864
LMUL = LMULType(0);
862865
// Update ElementBitwidth need to update Scale too.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -305,6 +305,31 @@
305305
// CHECK-NEXT: [[F64M2X3:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 8
306306
// CHECK-NEXT: [[F64M2X4:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 8
307307
// CHECK-NEXT: [[F64M4X2:%.*]] = alloca { <vscale x 4 x double>, <vscale x 4 x double> }, align 8
308+
// CHECK-NEXT: [[BF16MF4X2:%.*]] = alloca { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> }, align 2
309+
// CHECK-NEXT: [[BF16MF4X3:%.*]] = alloca { <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat> }, align 2
310+
// CHECK-NEXT: [[BF16MF4X4:%.*]] = alloca { <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat> }, align 2
311+
// CHECK-NEXT: [[BF16MF4X5:%.*]] = alloca { <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat> }, align 2
312+
// CHECK-NEXT: [[BF16MF4X6:%.*]] = alloca { <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat> }, align 2
313+
// CHECK-NEXT: [[BF16MF4X7:%.*]] = alloca { <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat> }, align 2
314+
// CHECK-NEXT: [[BF16MF4X8:%.*]] = alloca { <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat> }, align 2
315+
// CHECK-NEXT: [[BF16MF2X2:%.*]] = alloca { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> }, align 2
316+
// CHECK-NEXT: [[BF16MF2X3:%.*]] = alloca { <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat> }, align 2
317+
// CHECK-NEXT: [[BF16MF2X4:%.*]] = alloca { <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat> }, align 2
318+
// CHECK-NEXT: [[BF16MF2X5:%.*]] = alloca { <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat> }, align 2
319+
// CHECK-NEXT: [[BF16MF2X6:%.*]] = alloca { <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat> }, align 2
320+
// CHECK-NEXT: [[BF16MF2X7:%.*]] = alloca { <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat> }, align 2
321+
// CHECK-NEXT: [[BF16MF2X8:%.*]] = alloca { <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat> }, align 2
322+
// CHECK-NEXT: [[BF16M1X2:%.*]] = alloca { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> }, align 2
323+
// CHECK-NEXT: [[BF16M1X3:%.*]] = alloca { <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat> }, align 2
324+
// CHECK-NEXT: [[BF16M1X4:%.*]] = alloca { <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat> }, align 2
325+
// CHECK-NEXT: [[BF16M1X5:%.*]] = alloca { <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat> }, align 2
326+
// CHECK-NEXT: [[BF16M1X6:%.*]] = alloca { <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat> }, align 2
327+
// CHECK-NEXT: [[BF16M1X7:%.*]] = alloca { <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat> }, align 2
328+
// CHECK-NEXT: [[BF16M1X8:%.*]] = alloca { <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat> }, align 2
329+
// CHECK-NEXT: [[BF16M2X2:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 2
330+
// CHECK-NEXT: [[BF16M2X3:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 2
331+
// CHECK-NEXT: [[BF16M2X4:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 2
332+
// CHECK-NEXT: [[BF16M4X2:%.*]] = alloca { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> }, align 2
308333
// CHECK-NEXT: ret void
309334
//
310335
void foo () {
@@ -664,4 +689,34 @@ void foo () {
664689
vfloat64m2x4_t f64m2x4;
665690

666691
vfloat64m4x2_t f64m4x2;
692+
// bf16
693+
vbfloat16mf4x2_t bf16mf4x2;
694+
vbfloat16mf4x3_t bf16mf4x3;
695+
vbfloat16mf4x4_t bf16mf4x4;
696+
vbfloat16mf4x5_t bf16mf4x5;
697+
vbfloat16mf4x6_t bf16mf4x6;
698+
vbfloat16mf4x7_t bf16mf4x7;
699+
vbfloat16mf4x8_t bf16mf4x8;
700+
701+
vbfloat16mf2x2_t bf16mf2x2;
702+
vbfloat16mf2x3_t bf16mf2x3;
703+
vbfloat16mf2x4_t bf16mf2x4;
704+
vbfloat16mf2x5_t bf16mf2x5;
705+
vbfloat16mf2x6_t bf16mf2x6;
706+
vbfloat16mf2x7_t bf16mf2x7;
707+
vbfloat16mf2x8_t bf16mf2x8;
708+
709+
vbfloat16m1x2_t bf16m1x2;
710+
vbfloat16m1x3_t bf16m1x3;
711+
vbfloat16m1x4_t bf16m1x4;
712+
vbfloat16m1x5_t bf16m1x5;
713+
vbfloat16m1x6_t bf16m1x6;
714+
vbfloat16m1x7_t bf16m1x7;
715+
vbfloat16m1x8_t bf16m1x8;
716+
717+
vbfloat16m2x2_t bf16m2x2;
718+
vbfloat16m2x3_t bf16m2x3;
719+
vbfloat16m2x4_t bf16m2x4;
720+
721+
vbfloat16m4x2_t bf16m4x2;
667722
}

‎clang/utils/TableGen/RISCVVEmitter.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -401,7 +401,9 @@ void RVVEmitter::createHeader(raw_ostream &OS) {
401401
auto TupleT = TypeCache.computeType(
402402
BT, Log2LMUL,
403403
PrototypeDescriptor(BaseTypeModifier::Vector, getTupleVTM(NF),
404-
TypeModifier::Float));
404+
(BT == BasicType::BFloat16
405+
? TypeModifier::BFloat
406+
: TypeModifier::Float)));
405407
if (TupleT)
406408
printType(*TupleT);
407409
}

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 480794
19+
#define LLVM_MAIN_REVISION 480796
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

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