Merged main:a1d73ace13a20ed122a66d3d59f0cbae58d0f669 into amd-gfx:df3bf34a3c95

Local branch amd-gfx df3bf34 Merged main:faa4e35c622c13c7a565b979a6676d6cf3040cd4 into amd-gfx:b65e986d8413
Remote branch main a1d73ac [libc++][TZDB] Finishes zoned_time constructors. (llvm#95010)

Author: SC llvm team

clang/cmake/caches/Fuchsia-stage2.cmake

@@ -141,7 +141,7 @@ if(WIN32 OR LLVM_WINSYSROOT)
   set(RUNTIMES_${target}_CMAKE_MODULE_LINKER_FLAGS ${WINDOWS_LINK_FLAGS} CACHE STRING "")
 endif()
 
-foreach(target aarch64-linux-gnu;armv7-linux-gnueabihf;i386-linux-gnu;riscv64-linux-gnu;x86_64-linux-gnu)
+foreach(target aarch64-unknown-linux-gnu;armv7-unknown-linux-gnueabihf;i386-unknown-linux-gnu;riscv64-unknown-linux-gnu;x86_64-unknown-linux-gnu)
   if(LINUX_${target}_SYSROOT)
     # Set the per-target builtins options.
     list(APPEND BUILTIN_TARGETS "${target}")

clang/lib/Basic/Targets/Hexagon.cpp

@@ -238,6 +238,18 @@ static constexpr CPUSuffix Suffixes[] = {
     {{"hexagonv73"}, {"73"}},
 };
 
+std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) {
+  StringRef Arch = Name;
+  Arch.consume_front("hexagonv");
+  Arch.consume_back("t");
+
+  unsigned Val;
+  if (!Arch.getAsInteger(0, Val))
+    return Val;
+
+  return std::nullopt;
+}
+
 const char *HexagonTargetInfo::getHexagonCPUSuffix(StringRef Name) {
   const CPUSuffix *Item = llvm::find_if(
       Suffixes, [Name](const CPUSuffix &S) { return S.Name == Name; });

clang/lib/Basic/Targets/Hexagon.h

@@ -17,6 +17,7 @@
 #include "clang/Basic/TargetOptions.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/TargetParser/Triple.h"
+#include <optional>
 
 namespace clang {
 namespace targets {
@@ -115,6 +116,7 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
   std::string_view getClobbers() const override { return ""; }
 
   static const char *getHexagonCPUSuffix(StringRef Name);
+  static std::optional<unsigned> getHexagonCPURev(StringRef Name);
 
   bool isValidCPUName(StringRef Name) const override {
     return getHexagonCPUSuffix(Name);
@@ -139,6 +141,14 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
   }
 
   bool hasBitIntType() const override { return true; }
+
+  std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
+    std::optional<unsigned> Rev = getHexagonCPURev(CPU);
+
+    // V73 and later have 64-byte cache lines.
+    unsigned CacheLineSizeBytes = Rev >= 73 ? 64 : 32;
+    return std::make_pair(CacheLineSizeBytes, CacheLineSizeBytes);
+  }
 };
 } // namespace targets
 } // namespace clang

clang/lib/Sema/TreeTransform.h

@@ -2896,6 +2896,9 @@ class TreeTransform {
     SS.Adopt(QualifierLoc);
 
     Base = BaseResult.get();
+    if (Base->containsErrors())
+      return ExprError();
+
     QualType BaseType = Base->getType();
 
     if (isArrow && !BaseType->isPointerType())

clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp

@@ -574,3 +574,34 @@ namespace N4 {
     }
   };
 } // namespace N4
+
+namespace N5 {
+  struct A {
+    int x;
+  };
+
+  template<typename T>
+  void f() {
+    A y = T::x; // expected-error {{type 'int' cannot be used prior to '::' because it has no members}}
+    y.x;
+  }
+
+  template void f<int>(); // expected-note {{in instantiation of}}
+
+  struct B {
+    template<typename T>
+    B(T&&);
+
+    int x;
+  };
+
+  template<typename T>
+  void g(T y) {
+    B z([&]() { // expected-note {{while substituting into a lambda expression here}}
+      h(&y); // expected-error {{use of undeclared identifier 'h'}}
+    });
+    z.x;
+  }
+
+  template void g(int); // expected-note {{in instantiation of}}
+} // namespace N5

clang/test/Driver/print-supported-extensions-riscv.c

@@ -70,6 +70,7 @@
 // CHECK-NEXT:     zksed                1.0       'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)
 // CHECK-NEXT:     zksh                 1.0       'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)
 // CHECK-NEXT:     zkt                  1.0       'Zkt' (Data Independent Execution Latency)
+// CHECK-NEXT:     ztso                 1.0       'Ztso' (Memory Model - Total Store Order)
 // CHECK-NEXT:     zvbb                 1.0       'Zvbb' (Vector basic bit-manipulation instructions)
 // CHECK-NEXT:     zvbc                 1.0       'Zvbc' (Vector Carryless Multiplication)
 // CHECK-NEXT:     zve32f               1.0       'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)
@@ -170,7 +171,6 @@
 // CHECK-NEXT:     zicfilp              0.4       'Zicfilp' (Landing pad)
 // CHECK-NEXT:     zicfiss              0.4       'Zicfiss' (Shadow stack)
 // CHECK-NEXT:     zalasr               0.1       'Zalasr' (Load-Acquire and Store-Release Instructions)
-// CHECK-NEXT:     ztso                 0.1       'Ztso' (Memory Model - Total Store Order)
 // CHECK-NEXT:     smmpm                1.0       'Smmpm' (Machine-level Pointer Masking for M-mode)
 // CHECK-NEXT:     smnpm                1.0       'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
 // CHECK-NEXT:     ssnpm                1.0       'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)

clang/test/Driver/riscv-arch.c

@@ -365,24 +365,30 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
-// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso'
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izalasr'
 // RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
-// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso'
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izalasr'
 // RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7 -menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr0p7 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
-// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32iztso0p7'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'ztso' (this compiler supports 0.1)
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izalasr0p7'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zalasr' (this compiler supports 0.1)
 
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso0p1 -menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p1 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
-// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-ztso"
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zalasr"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZTSO %s
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZTSO %s
+// RV32-ZTSO: "-target-feature" "+ztso"
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s

clang/test/Preprocessor/hexagon-predefines.c

@@ -169,3 +169,20 @@
 // CHECK-ATOMIC: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 2
 // CHECK-ATOMIC: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 2
 // CHECK-ATOMIC: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 2
+
+// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-linux-musl \
+// RUN: -target-cpu hexagonv67 | FileCheck \
+// RUN: %s -check-prefix CHECK-INTERFERENCE
+// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-none-elf \
+// RUN: -target-cpu hexagonv67 | FileCheck \
+// RUN: %s -check-prefix CHECK-INTERFERENCE
+// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-none-elf \
+// RUN: -target-cpu hexagonv71t | FileCheck \
+// RUN: %s -check-prefix CHECK-INTERFERENCE
+// CHECK-INTERFERENCE: #define __GCC_CONSTRUCTIVE_SIZE 32
+// CHECK-INTERFERENCE: #define __GCC_DESTRUCTIVE_SIZE 32
+// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-none-elf \
+// RUN: -target-cpu hexagonv73 | FileCheck \
+// RUN: %s -check-prefix CHECK-INTERFERENCE-73
+// CHECK-INTERFERENCE-73: #define __GCC_CONSTRUCTIVE_SIZE 64
+// CHECK-INTERFERENCE-73: #define __GCC_DESTRUCTIVE_SIZE 64

clang/test/Preprocessor/riscv-target-features.c

@@ -1650,13 +1650,13 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
 // CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}}
 
-// RUN: %clang --target=riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv32iztso0p1 -E -dM %s \
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32iztso1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
-// RUN: %clang --target=riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv64iztso0p1 -E -dM %s \
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64iztso1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
-// CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}}
+// CHECK-ZTSO-EXT: __riscv_ztso 1000000{{$}}
 
 // RUN: %clang --target=riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32ifzvfbfmin1p0 -E -dM %s \

compiler-rt/CODE_OWNERS.TXT

@@ -67,3 +67,7 @@ D: ThreadSanitizer
 N: Bill Wendling
 E: isanbard@gmail.com
 D: Profile runtime library
+
+N: Christopher Apple, David Trevelyan
+E: cja-private@pm.me, realtime.sanitizer@gmail.com
+D: Realtime Sanitizer (RTSan)