From 7097f8b03638bf6b0431f4cc0ac49ad765072978 Mon Sep 17 00:00:00 2001
From: "Maksimova, Viktoria" <viktoria.maksimova@intel.com>
Date: Fri, 13 Mar 2026 04:04:22 -0700
Subject: [PATCH 1/7] [Backport to 16] [SPIRV-to-LLVM] Set LocalId parameter of
 GroupBroadcast to unsigned in SPV-IR (#3084)

LocalId should not be negative. Change its type from signed to unsigned
in SPV-IR aligns with OpenCL work_group_broadcast built-in and use of
GroupBroadcast built-in in SYCL header.

Also change NumElements/Stride parameters of OpGroupAsyncCopy to
unsigned.
---
 lib/SPIRV/SPIRVUtil.cpp                  | 5 +++++
 test/GroupAndSubgroupInstructions.spvasm | 2 +-
 test/transcoding/OpGroupAsyncCopy.ll     | 4 ++--
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
index 10e1cadbf0..d5065a8cc9 100644
--- a/lib/SPIRV/SPIRVUtil.cpp
+++ b/lib/SPIRV/SPIRVUtil.cpp
@@ -2537,8 +2537,13 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
       addUnsignedArg(0);
       addUnsignedArg(3);
       break;
+    case OpGroupAsyncCopy:
+      addUnsignedArg(3);
+      addUnsignedArg(4);
+      break;
     case OpGroupUMax:
     case OpGroupUMin:
+    case OpGroupBroadcast:
     case OpGroupNonUniformBroadcast:
     case OpGroupNonUniformBallotBitCount:
     case OpGroupNonUniformShuffle:
diff --git a/test/GroupAndSubgroupInstructions.spvasm b/test/GroupAndSubgroupInstructions.spvasm
index 5ea14e4cfe..9f6432f58e 100644
--- a/test/GroupAndSubgroupInstructions.spvasm
+++ b/test/GroupAndSubgroupInstructions.spvasm
@@ -79,7 +79,7 @@
 
 ; CHECK-SPV-IR: declare spir_func i1 @_Z16__spirv_GroupAllib(i32, i1) #[[#Attrs:]]
 ; CHECK-SPV-IR: declare spir_func i1 @_Z16__spirv_GroupAnyib(i32, i1) #[[#Attrs]]
-; CHECK-SPV-IR: declare spir_func i32 @_Z22__spirv_GroupBroadcastiii(i32, i32, i32) #[[#Attrs]]
+; CHECK-SPV-IR: declare spir_func i32 @_Z22__spirv_GroupBroadcastiij(i32, i32, i32) #[[#Attrs]]
 ; CHECK-SPV-IR: declare spir_func void @_Z22__spirv_ControlBarrieriii(i32, i32, i32) #[[#Attrs]]
 ; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupIAddiii(i32, i32, i32) #[[#Attrs]]
 ; CHECK-SPV-IR: declare spir_func float @_Z17__spirv_GroupFAddiif(i32, i32, float) #[[#Attrs]]
diff --git a/test/transcoding/OpGroupAsyncCopy.ll b/test/transcoding/OpGroupAsyncCopy.ll
index 31ca2d05e5..0cdc4f14f8 100644
--- a/test/transcoding/OpGroupAsyncCopy.ll
+++ b/test/transcoding/OpGroupAsyncCopy.ll
@@ -13,9 +13,9 @@
 ; CHECK-LLVM: declare spir_func %opencl.event_t* @_Z29async_work_group_strided_copyPU3AS1Dv2_hPU3AS3KS_jj9ocl_event(<2 x i8> addrspace(1)*, <2 x i8> addrspace(3)*, i32, i32, %opencl.event_t*)
 ; CHECK-LLVM: declare spir_func void @_Z17wait_group_eventsiPU3AS49ocl_event(i32, %opencl.event_t* addrspace(4)*)
 
-; CHECK-SPV-IR: call spir_func %spirv.Event* @_Z22__spirv_GroupAsyncCopyiPU3AS1Dv2_cPU3AS3S_iiP13__spirv_Event(i32 2
+; CHECK-SPV-IR: call spir_func %spirv.Event* @_Z22__spirv_GroupAsyncCopyiPU3AS1Dv2_cPU3AS3S_jjP13__spirv_Event(i32 2
 ; CHECK-SPV-IR: call spir_func void @_Z23__spirv_GroupWaitEventsiiPU3AS4P13__spirv_Event(i32 2
-; CHECK-SPV-IR: declare spir_func %spirv.Event* @_Z22__spirv_GroupAsyncCopyiPU3AS1Dv2_cPU3AS3S_iiP13__spirv_Event(i32, <2 x i8> addrspace(1)*, <2 x i8> addrspace(3)*, i32, i32, %spirv.Event*
+; CHECK-SPV-IR: declare spir_func %spirv.Event* @_Z22__spirv_GroupAsyncCopyiPU3AS1Dv2_cPU3AS3S_jjP13__spirv_Event(i32, <2 x i8> addrspace(1)*, <2 x i8> addrspace(3)*, i32, i32, %spirv.Event*
 ; CHECK-SPV-IR: declare spir_func void @_Z23__spirv_GroupWaitEventsiiPU3AS4P13__spirv_Event(i32, i32, %spirv.Event* addrspace(4)*)
 
 ; CHECK-SPIRV-DAG: GroupAsyncCopy {{[0-9]+}} {{[0-9]+}} [[Scope:[0-9]+]]

From 6b14216cbe2a22e704f380966e4d780eae38bf9d Mon Sep 17 00:00:00 2001
From: "Maksimova, Viktoria" <viktoria.maksimova@intel.com>
Date: Fri, 13 Mar 2026 04:04:22 -0700
Subject: [PATCH 2/7] [Backport to 16] [LLVM->SPV-IR] Set an arg of
 __spirv_ocl_nan/shuffle/shuffle2 to unsigned (#3106)

OpenCL built-in nan's argument type and shuffle/shuffle2's mask argument
type is unsigned. DPC++ header also sets unsigned type for them. So this
PR changes them to unsigned in SPV-IR.
---
 lib/SPIRV/SPIRVUtil.cpp            |  9 ++++++
 test/transcoding/OpenCL/nan.ll     | 33 +++++++++++++++++++++
 test/transcoding/OpenCL/shuffle.ll | 46 ++++++++++++++++++++++++++++++
 3 files changed, 88 insertions(+)
 create mode 100644 test/transcoding/OpenCL/nan.ll
 create mode 100644 test/transcoding/OpenCL/shuffle.ll

diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
index d5065a8cc9..97137182ae 100644
--- a/lib/SPIRV/SPIRVUtil.cpp
+++ b/lib/SPIRV/SPIRVUtil.cpp
@@ -2739,6 +2739,15 @@ class OpenCLStdToSPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpenCLLIB::S_Upsample:
       addUnsignedArg(1);
       break;
+    case OpenCLLIB::Nan:
+      addUnsignedArg(0);
+      break;
+    case OpenCLLIB::Shuffle:
+      addUnsignedArg(1);
+      break;
+    case OpenCLLIB::Shuffle2:
+      addUnsignedArg(2);
+      break;
     default:;
       // No special handling is needed
     }
diff --git a/test/transcoding/OpenCL/nan.ll b/test/transcoding/OpenCL/nan.ll
new file mode 100644
index 0000000000..ce2d96cb65
--- /dev/null
+++ b/test/transcoding/OpenCL/nan.ll
@@ -0,0 +1,33 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefixes=CHECK-LLVM
+; RUN: llvm-spirv -r %t.spv --spirv-target-env=SPV-IR -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefixes=CHECK-SPV-IR
+
+; Check OpenCL built-in nan translation.
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64-G1"
+target triple = "spir64"
+
+; CHECK-SPIRV: ExtInst [[#]] [[#]] [[#]] nan
+
+; CHECK-LLVM: call spir_func float @_Z3nanj(
+
+; CHECK-SPV-IR: call spir_func float @_Z15__spirv_ocl_nanj(
+
+define dso_local spir_kernel void @test(ptr addrspace(1) align 4 %a, i32 %b) {
+entry:
+  %call = tail call spir_func float @_Z3nanj(i32 %b)
+  store float %call, ptr addrspace(1) %a, align 4
+  ret void
+}
+
+declare spir_func float @_Z3nanj(i32)
+
+!opencl.ocl.version = !{!0}
+
+!0 = !{i32 3, i32 0}
diff --git a/test/transcoding/OpenCL/shuffle.ll b/test/transcoding/OpenCL/shuffle.ll
new file mode 100644
index 0000000000..584e7af558
--- /dev/null
+++ b/test/transcoding/OpenCL/shuffle.ll
@@ -0,0 +1,46 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefixes=CHECK-LLVM
+; RUN: llvm-spirv -r %t.spv --spirv-target-env=SPV-IR -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefixes=CHECK-SPV-IR
+
+; Check OpenCL built-in shuffle and shuffle2 translation.
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64-G1"
+target triple = "spir64"
+
+; CHECK-SPIRV: ExtInst [[#]] [[#]] [[#]] shuffle
+; CHECK-SPIRV: ExtInst [[#]] [[#]] [[#]] shuffle2
+
+; CHECK-LLVM: call spir_func <2 x float> @_Z7shuffleDv2_fDv2_j(
+; CHECK-LLVM: call spir_func <4 x float> @_Z8shuffle2Dv2_fS_Dv4_j(
+
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z19__spirv_ocl_shuffleDv2_fDv2_j(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z20__spirv_ocl_shuffle2Dv2_fS_Dv4_j(
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64-G1"
+target triple = "spir64"
+
+define spir_kernel void @test() {
+entry:
+  %call = call spir_func <2 x float> @_Z7shuffleDv2_fDv2_j(<2 x float> zeroinitializer, <2 x i32> zeroinitializer)
+  ret void
+}
+
+declare spir_func <2 x float> @_Z7shuffleDv2_fDv2_j(<2 x float>, <2 x i32>)
+
+define spir_kernel void @test2() {
+entry:
+  %call = call spir_func <4 x float> @_Z8shuffle2Dv2_fS_Dv4_j(<2 x float> zeroinitializer, <2 x float> zeroinitializer, <4 x i32> zeroinitializer)
+  ret void
+}
+
+declare spir_func <4 x float> @_Z8shuffle2Dv2_fS_Dv4_j(<2 x float>, <2 x float>, <4 x i32>)
+
+!opencl.ocl.version = !{!0}
+
+!0 = !{i32 3, i32 0}

From 4138b2a777618ca0cd8ea9d6936f9b0c9b559138 Mon Sep 17 00:00:00 2001
From: "Maksimova, Viktoria" <viktoria.maksimova@intel.com>
Date: Fri, 13 Mar 2026 04:04:22 -0700
Subject: [PATCH 3/7] [Backport to 16] [LLVM->SPV-IR] Set vload/vstore's offset
 arg type to unsigned (#3478)

Offset arg type is size_t in OpenCL ExtendedInstructionSet Spec.
---
 lib/SPIRV/SPIRVUtil.cpp              |  15 ++
 test/OpenCL.std/vload_half.spvasm    |  32 +--
 test/OpenCL.std/vload_halfn.spvasm   |  40 ++--
 test/OpenCL.std/vloada_halfn.spvasm  |  40 ++--
 test/OpenCL.std/vloadn.spvasm        | 280 +++++++++++++--------------
 test/OpenCL.std/vstore_half.spvasm   | 130 ++++++-------
 test/OpenCL.std/vstore_halfn.spvasm  |  60 +++---
 test/OpenCL.std/vstorea_halfn.spvasm |  60 +++---
 test/OpenCL.std/vstoren.spvasm       | 224 ++++++++++-----------
 9 files changed, 448 insertions(+), 433 deletions(-)

diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
index 97137182ae..0d940453b6 100644
--- a/lib/SPIRV/SPIRVUtil.cpp
+++ b/lib/SPIRV/SPIRVUtil.cpp
@@ -2748,6 +2748,21 @@ class OpenCLStdToSPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpenCLLIB::Shuffle2:
       addUnsignedArg(2);
       break;
+    case OpenCLLIB::Vloadn:
+    case OpenCLLIB::Vload_half:
+    case OpenCLLIB::Vload_halfn:
+    case OpenCLLIB::Vloada_halfn:
+      addUnsignedArg(0);
+      break;
+    case OpenCLLIB::Vstoren:
+    case OpenCLLIB::Vstore_half:
+    case OpenCLLIB::Vstore_half_r:
+    case OpenCLLIB::Vstore_halfn:
+    case OpenCLLIB::Vstore_halfn_r:
+    case OpenCLLIB::Vstorea_halfn:
+    case OpenCLLIB::Vstorea_halfn_r:
+      addUnsignedArg(1);
+      break;
     default:;
       // No special handling is needed
     }
diff --git a/test/OpenCL.std/vload_half.spvasm b/test/OpenCL.std/vload_half.spvasm
index 677a8db1ec..3932566975 100644
--- a/test/OpenCL.std/vload_half.spvasm
+++ b/test/OpenCL.std/vload_half.spvasm
@@ -6,22 +6,22 @@
 ;
 ; CHECK-LABEL: spir_kernel void @test
 ;
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS1Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS1Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS1Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS1Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS3Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS3Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS3Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS3Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS2Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS2Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS2Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPU3AS2Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPDh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPDh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPDh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatiPDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
 ;
 ; CHECK-CL20: call spir_func float @_Z10vload_halfjPU3AS1KDh
 ; CHECK-CL20: call spir_func float @_Z10vload_halfjPU3AS1KDh
diff --git a/test/OpenCL.std/vload_halfn.spvasm b/test/OpenCL.std/vload_halfn.spvasm
index 90bf3f568f..f86a9a202e 100644
--- a/test/OpenCL.std/vload_halfn.spvasm
+++ b/test/OpenCL.std/vload_halfn.spvasm
@@ -6,26 +6,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @test
 ;
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2iPDhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3iPDhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4iPDhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8iPDhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16iPDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPDhi(
 ;
 ; CHECK-CL20: call spir_func <2 x float> @_Z11vload_half2jPU3AS1KDh(
 ; CHECK-CL20: call spir_func <3 x float> @_Z11vload_half3jPU3AS1KDh(
diff --git a/test/OpenCL.std/vloada_halfn.spvasm b/test/OpenCL.std/vloada_halfn.spvasm
index 3eeb845689..b93b2e20cc 100644
--- a/test/OpenCL.std/vloada_halfn.spvasm
+++ b/test/OpenCL.std/vloada_halfn.spvasm
@@ -6,26 +6,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @test
 ;
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2iPDhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3iPDhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4iPDhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8iPDhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16iPDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPDhi(
 ;
 ; CHECK-CL20: call spir_func <2 x float> @_Z12vloada_half2jPU3AS1KDh(
 ; CHECK-CL20: call spir_func <3 x float> @_Z12vloada_half3jPU3AS1KDh(
diff --git a/test/OpenCL.std/vloadn.spvasm b/test/OpenCL.std/vloadn.spvasm
index 6668198941..093ffd233a 100644
--- a/test/OpenCL.std/vloadn.spvasm
+++ b/test/OpenCL.std/vloadn.spvasm
@@ -6,26 +6,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testChar
 ;
-; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2iPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3iPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4iPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8iPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16iPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2iPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3iPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4iPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8iPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16iPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2iPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3iPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4iPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8iPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16iPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2iPci(
-; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3iPci(
-; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4iPci(
-; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8iPci(
-; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16iPci(
+; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPU3AS1ci(
+; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPU3AS1ci(
+; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPU3AS1ci(
+; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPU3AS1ci(
+; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPU3AS1ci(
+; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPU3AS3ci(
+; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPU3AS3ci(
+; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPU3AS3ci(
+; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPU3AS3ci(
+; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPU3AS3ci(
+; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPU3AS2ci(
+; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPU3AS2ci(
+; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPU3AS2ci(
+; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPU3AS2ci(
+; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPU3AS2ci(
+; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPci(
+; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPci(
+; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPci(
+; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPci(
+; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPci(
 ;
 ; CHECK-CL20: call spir_func <2 x i8> @_Z6vload2jPU3AS1Kc(
 ; CHECK-CL20: call spir_func <3 x i8> @_Z6vload3jPU3AS1Kc(
@@ -50,26 +50,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testShort
 ;
-; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2iPU3AS1si(
-; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3iPU3AS1si(
-; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4iPU3AS1si(
-; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8iPU3AS1si(
-; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16iPU3AS1si(
-; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2iPU3AS3si(
-; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3iPU3AS3si(
-; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4iPU3AS3si(
-; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8iPU3AS3si(
-; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16iPU3AS3si(
-; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2iPU3AS2si(
-; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3iPU3AS2si(
-; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4iPU3AS2si(
-; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8iPU3AS2si(
-; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16iPU3AS2si(
-; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2iPsi(
-; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3iPsi(
-; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4iPsi(
-; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8iPsi(
-; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16iPsi(
+; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPU3AS1si(
+; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPU3AS1si(
+; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPU3AS1si(
+; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPU3AS1si(
+; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPU3AS1si(
+; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPU3AS3si(
+; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPU3AS3si(
+; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPU3AS3si(
+; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPU3AS3si(
+; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPU3AS3si(
+; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPU3AS2si(
+; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPU3AS2si(
+; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPU3AS2si(
+; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPU3AS2si(
+; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPU3AS2si(
+; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPsi(
+; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPsi(
+; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPsi(
+; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPsi(
+; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPsi(
 ;
 ; CHECK-CL20: call spir_func <2 x i16> @_Z6vload2jPU3AS1Ks(
 ; CHECK-CL20: call spir_func <3 x i16> @_Z6vload3jPU3AS1Ks(
@@ -94,26 +94,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testInt
 ;
-; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2iPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3iPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4iPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8iPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16iPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2iPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3iPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4iPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8iPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16iPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2iPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3iPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4iPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8iPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16iPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2iPii(
-; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3iPii(
-; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4iPii(
-; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8iPii(
-; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16iPii(
+; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPU3AS1ii(
+; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPU3AS1ii(
+; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPU3AS1ii(
+; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPU3AS1ii(
+; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPU3AS1ii(
+; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPU3AS3ii(
+; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPU3AS3ii(
+; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPU3AS3ii(
+; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPU3AS3ii(
+; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPU3AS3ii(
+; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPU3AS2ii(
+; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPU3AS2ii(
+; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPU3AS2ii(
+; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPU3AS2ii(
+; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPU3AS2ii(
+; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPii(
+; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPii(
+; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPii(
+; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPii(
+; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPii(
 ;
 ; CHECK-CL20: call spir_func <2 x i32> @_Z6vload2jPU3AS1Ki(
 ; CHECK-CL20: call spir_func <3 x i32> @_Z6vload3jPU3AS1Ki(
@@ -138,26 +138,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testLong
 ;
-; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2iPU3AS1li(
-; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3iPU3AS1li(
-; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4iPU3AS1li(
-; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8iPU3AS1li(
-; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16iPU3AS1li(
-; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2iPU3AS3li(
-; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3iPU3AS3li(
-; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4iPU3AS3li(
-; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8iPU3AS3li(
-; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16iPU3AS3li(
-; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2iPU3AS2li(
-; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3iPU3AS2li(
-; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4iPU3AS2li(
-; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8iPU3AS2li(
-; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16iPU3AS2li(
-; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2iPli(
-; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3iPli(
-; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4iPli(
-; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8iPli(
-; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16iPli(
+; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPU3AS1li(
+; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPU3AS1li(
+; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPU3AS1li(
+; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPU3AS1li(
+; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPU3AS1li(
+; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPU3AS3li(
+; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPU3AS3li(
+; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPU3AS3li(
+; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPU3AS3li(
+; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPU3AS3li(
+; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPU3AS2li(
+; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPU3AS2li(
+; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPU3AS2li(
+; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPU3AS2li(
+; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPU3AS2li(
+; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPli(
+; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPli(
+; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPli(
+; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPli(
+; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPli(
 ;
 ; CHECK-CL20: call spir_func <2 x i64> @_Z6vload2jPU3AS1Kl(
 ; CHECK-CL20: call spir_func <3 x i64> @_Z6vload3jPU3AS1Kl(
@@ -182,26 +182,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testHalf
 ;
-; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16iPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16iPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16iPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2iPDhi(
-; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3iPDhi(
-; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4iPDhi(
-; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8iPDhi(
-; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16iPDhi(
+; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPU3AS1Dhi(
+; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPU3AS3Dhi(
+; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPU3AS2Dhi(
+; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPDhi(
+; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPDhi(
+; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPDhi(
+; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPDhi(
+; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPDhi(
 ;
 ; CHECK-CL20: call spir_func <2 x half> @_Z6vload2jPU3AS1KDh(
 ; CHECK-CL20: call spir_func <3 x half> @_Z6vload3jPU3AS1KDh(
@@ -226,26 +226,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testFloat
 ;
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2iPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3iPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4iPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8iPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16iPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2iPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3iPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4iPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8iPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16iPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2iPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3iPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4iPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8iPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16iPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2iPfi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3iPfi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4iPfi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8iPfi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16iPfi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPU3AS1fi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPU3AS1fi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPU3AS1fi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPU3AS1fi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPU3AS1fi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPU3AS3fi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPU3AS3fi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPU3AS3fi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPU3AS3fi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPU3AS3fi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPU3AS2fi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPU3AS2fi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPU3AS2fi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPU3AS2fi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPU3AS2fi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPfi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPfi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPfi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPfi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPfi(
 ;
 ; CHECK-CL20: call spir_func <2 x float> @_Z6vload2jPU3AS1Kf(
 ; CHECK-CL20: call spir_func <3 x float> @_Z6vload3jPU3AS1Kf(
@@ -270,26 +270,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testDouble
 ;
-; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2iPU3AS1di(
-; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3iPU3AS1di(
-; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4iPU3AS1di(
-; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8iPU3AS1di(
-; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16iPU3AS1di(
-; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2iPU3AS3di(
-; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3iPU3AS3di(
-; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4iPU3AS3di(
-; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8iPU3AS3di(
-; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16iPU3AS3di(
-; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2iPU3AS2di(
-; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3iPU3AS2di(
-; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4iPU3AS2di(
-; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8iPU3AS2di(
-; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16iPU3AS2di(
-; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2iPdi(
-; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3iPdi(
-; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4iPdi(
-; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8iPdi(
-; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16iPdi(
+; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPU3AS1di(
+; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPU3AS1di(
+; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPU3AS1di(
+; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPU3AS1di(
+; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPU3AS1di(
+; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPU3AS3di(
+; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPU3AS3di(
+; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPU3AS3di(
+; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPU3AS3di(
+; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPU3AS3di(
+; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPU3AS2di(
+; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPU3AS2di(
+; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPU3AS2di(
+; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPU3AS2di(
+; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPU3AS2di(
+; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPdi(
+; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPdi(
+; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPdi(
+; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPdi(
+; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPdi(
 ;
 ; CHECK-CL20: call spir_func <2 x double> @_Z6vload2jPU3AS1Kd(
 ; CHECK-CL20: call spir_func <3 x double> @_Z6vload3jPU3AS1Kd(
diff --git a/test/OpenCL.std/vstore_half.spvasm b/test/OpenCL.std/vstore_half.spvasm
index 405f696b47..4b990edbaa 100644
--- a/test/OpenCL.std/vstore_half.spvasm
+++ b/test/OpenCL.std/vstore_half.spvasm
@@ -10,19 +10,19 @@
 ; CHECK-SPV-BACK: TypeVoid [[VoidTy:[0-9]+]]
 
 ; CHECK-LABEL: spir_kernel void @test
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPU3AS1Dh(float {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPU3AS1Dh(float {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPU3AS1Dh(float {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPU3AS1Dh(float {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPU3AS3Dh(float {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPU3AS3Dh(float {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPU3AS3Dh(float {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPU3AS3Dh(float {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPDh(float {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPDh(float {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPDh(float {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffiPDh(float {{.*}}, i32 0, ptr {{.*}})
-
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPU3AS1Dh(float {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPU3AS1Dh(float {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPU3AS1Dh(float {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPU3AS1Dh(float {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPU3AS3Dh(float {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPU3AS3Dh(float {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPU3AS3Dh(float {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPU3AS3Dh(float {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPDh(float {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPDh(float {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPDh(float {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z23__spirv_ocl_vstore_halffjPDh(float {{.*}}, i32 0, ptr {{.*}})
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half
@@ -50,19 +50,19 @@
 ; CHECK-CL20: call spir_func void @_Z11vstore_halffjPDh(float {{.*}}, i32 0, ptr {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTE
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 0)
-
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 0)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 0
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 0
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 0
@@ -90,19 +90,19 @@
 ; CHECK-CL20: call spir_func void @_Z15vstore_half_rtefjPDh(float {{.*}}, i32 0, ptr {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTZ
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 1)
-
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 1)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 1
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 1
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 1
@@ -130,19 +130,19 @@
 ; CHECK-CL20: call spir_func void @_Z15vstore_half_rtzfjPDh(float {{.*}}, i32 0, ptr {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTP
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 2)
-
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 2)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 2
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 2
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 2
@@ -170,19 +170,19 @@
 ; CHECK-CL20: call spir_func void @_Z15vstore_half_rtpfjPDh(float {{.*}}, i32 0, ptr {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTN
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfiPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 3)
-
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS1Dhi(float {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPU3AS3Dhi(float {{.*}}, i32 0, ptr addrspace(3) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstore_half_rfjPDhi(float {{.*}}, i32 0, ptr {{.*}}, i32 3)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 3
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 3
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_half_r {{.*}} {{.*}} 3
diff --git a/test/OpenCL.std/vstore_halfn.spvasm b/test/OpenCL.std/vstore_halfn.spvasm
index 9e120abc75..9005c605c2 100644
--- a/test/OpenCL.std/vstore_halfn.spvasm
+++ b/test/OpenCL.std/vstore_halfn.spvasm
@@ -12,12 +12,12 @@
 ; CHECK-SPV-BACK: TypeVoid [[VoidTy:[0-9]+]]
 
 ; CHECK-LABEL: spir_kernel void @test
-; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv2_fiPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv3_fiPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv4_fiPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv8_fiPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv16_fiPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-
+; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv2_fjPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv3_fjPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv4_fjPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv8_fjPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn
@@ -31,12 +31,12 @@
 ; CHECK-CL20: call spir_func void @_Z13vstore_half16Dv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTE
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fiPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fiPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fiPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fiPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fiPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 0
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 0
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 0
@@ -50,12 +50,12 @@
 ; CHECK-CL20: call spir_func void @_Z17vstore_half16_rteDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTZ
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fiPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fiPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fiPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fiPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fiPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 1
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 1
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 1
@@ -69,12 +69,12 @@
 ; CHECK-CL20: call spir_func void @_Z17vstore_half16_rtzDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTP
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fiPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fiPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fiPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fiPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fiPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 2
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 2
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 2
@@ -88,12 +88,12 @@
 ; CHECK-CL20: call spir_func void @_Z17vstore_half16_rtpDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTN
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fiPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fiPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fiPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fiPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fiPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 3
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 3
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 3
diff --git a/test/OpenCL.std/vstorea_halfn.spvasm b/test/OpenCL.std/vstorea_halfn.spvasm
index 5f2d87a6c5..ea7f89bbb7 100644
--- a/test/OpenCL.std/vstorea_halfn.spvasm
+++ b/test/OpenCL.std/vstorea_halfn.spvasm
@@ -12,12 +12,12 @@
 ; CHECK-SPV-BACK: TypeVoid [[VoidTy:[0-9]+]]
 
 ; CHECK-LABEL: spir_kernel void @test
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv2_fiPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv3_fiPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv4_fiPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv8_fiPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv16_fiPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv2_fjPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv3_fjPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv4_fjPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv8_fjPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z25__spirv_ocl_vstorea_halfnDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn
@@ -31,12 +31,12 @@
 ; CHECK-CL20: call spir_func void @_Z14vstorea_half16Dv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTE
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv2_fiPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv3_fiPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv4_fiPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv8_fiPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv16_fiPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
-
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 0
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 0
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 0
@@ -50,12 +50,12 @@
 ; CHECK-CL20: call spir_func void @_Z18vstorea_half16_rteDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTZ
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv2_fiPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv3_fiPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv4_fiPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv8_fiPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv16_fiPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
-
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 1
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 1
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 1
@@ -69,12 +69,12 @@
 ; CHECK-CL20: call spir_func void @_Z18vstorea_half16_rtzDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTP
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv2_fiPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv3_fiPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv4_fiPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv8_fiPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv16_fiPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
-
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 2
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 2
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 2
@@ -88,12 +88,12 @@
 ; CHECK-CL20: call spir_func void @_Z18vstorea_half16_rtpDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testRTN
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv2_fiPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv3_fiPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv4_fiPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv8_fiPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv16_fiPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
-
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+; CHECK-SPV-IR: call spir_func void @_Z27__spirv_ocl_vstorea_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
+;
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 3
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 3
 ; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstorea_halfn_r {{.*}} [[Zero]] {{.*}} 3
diff --git a/test/OpenCL.std/vstoren.spvasm b/test/OpenCL.std/vstoren.spvasm
index 46daf55b83..3d8465c47d 100644
--- a/test/OpenCL.std/vstoren.spvasm
+++ b/test/OpenCL.std/vstoren.spvasm
@@ -10,22 +10,22 @@
 ; CHECK-SPV-BACK: TypeVoid [[VoidTy:[0-9]+]]
 
 ; CHECK-LABEL: spir_kernel void @testChar
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_ciPU3AS1c(<2 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_ciPU3AS1c(<3 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_ciPU3AS1c(<4 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_ciPU3AS1c(<8 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_ciPU3AS1c(<16 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_ciPU3AS3c(<2 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_ciPU3AS3c(<3 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_ciPU3AS3c(<4 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_ciPU3AS3c(<8 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_ciPU3AS3c(<16 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_ciPc(<2 x i8> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_ciPc(<3 x i8> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_ciPc(<4 x i8> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_ciPc(<8 x i8> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_ciPc(<16 x i8> {{.*}}, i32 0, ptr {{.*}})
-
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_cjPU3AS1c(<2 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_cjPU3AS1c(<3 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_cjPU3AS1c(<4 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_cjPU3AS1c(<8 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_cjPU3AS1c(<16 x i8> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_cjPU3AS3c(<2 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_cjPU3AS3c(<3 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_cjPU3AS3c(<4 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_cjPU3AS3c(<8 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_cjPU3AS3c(<16 x i8> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_cjPc(<2 x i8> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_cjPc(<3 x i8> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_cjPc(<4 x i8> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_cjPc(<8 x i8> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_cjPc(<16 x i8> {{.*}}, i32 0, ptr {{.*}})
+;
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
@@ -59,22 +59,22 @@
 ; CHECK-CL20: call spir_func void @_Z8vstore16Dv16_cjPc(<16 x i8> {{.*}}, i32 0, ptr {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testShort
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_siPU3AS1s(<2 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_siPU3AS1s(<3 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_siPU3AS1s(<4 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_siPU3AS1s(<8 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_siPU3AS1s(<16 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_siPU3AS3s(<2 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_siPU3AS3s(<3 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_siPU3AS3s(<4 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_siPU3AS3s(<8 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_siPU3AS3s(<16 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_siPs(<2 x i16> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_siPs(<3 x i16> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_siPs(<4 x i16> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_siPs(<8 x i16> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_siPs(<16 x i16> {{.*}}, i32 0, ptr {{.*}})
-
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_sjPU3AS1s(<2 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_sjPU3AS1s(<3 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_sjPU3AS1s(<4 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_sjPU3AS1s(<8 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_sjPU3AS1s(<16 x i16> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_sjPU3AS3s(<2 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_sjPU3AS3s(<3 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_sjPU3AS3s(<4 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_sjPU3AS3s(<8 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_sjPU3AS3s(<16 x i16> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_sjPs(<2 x i16> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_sjPs(<3 x i16> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_sjPs(<4 x i16> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_sjPs(<8 x i16> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_sjPs(<16 x i16> {{.*}}, i32 0, ptr {{.*}})
+;
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
@@ -108,22 +108,22 @@
 ; CHECK-CL20: call spir_func void @_Z8vstore16Dv16_sjPs(<16 x i16> {{.*}}, i32 0, ptr {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testInt
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_iiPU3AS1i(<2 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_iiPU3AS1i(<3 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_iiPU3AS1i(<4 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_iiPU3AS1i(<8 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_iiPU3AS1i(<16 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_iiPU3AS3i(<2 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_iiPU3AS3i(<3 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_iiPU3AS3i(<4 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_iiPU3AS3i(<8 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_iiPU3AS3i(<16 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_iiPi(<2 x i32> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_iiPi(<3 x i32> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_iiPi(<4 x i32> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_iiPi(<8 x i32> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_iiPi(<16 x i32> {{.*}}, i32 0, ptr {{.*}})
-
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_ijPU3AS1i(<2 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_ijPU3AS1i(<3 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_ijPU3AS1i(<4 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_ijPU3AS1i(<8 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_ijPU3AS1i(<16 x i32> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_ijPU3AS3i(<2 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_ijPU3AS3i(<3 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_ijPU3AS3i(<4 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_ijPU3AS3i(<8 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_ijPU3AS3i(<16 x i32> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_ijPi(<2 x i32> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_ijPi(<3 x i32> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_ijPi(<4 x i32> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_ijPi(<8 x i32> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_ijPi(<16 x i32> {{.*}}, i32 0, ptr {{.*}})
+;
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
@@ -157,22 +157,22 @@
 ; CHECK-CL20: call spir_func void @_Z8vstore16Dv16_ijPi(<16 x i32> {{.*}}, i32 0, ptr {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testLong
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_liPU3AS1l(<2 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_liPU3AS1l(<3 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_liPU3AS1l(<4 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_liPU3AS1l(<8 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_liPU3AS1l(<16 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_liPU3AS3l(<2 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_liPU3AS3l(<3 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_liPU3AS3l(<4 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_liPU3AS3l(<8 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_liPU3AS3l(<16 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_liPl(<2 x i64> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_liPl(<3 x i64> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_liPl(<4 x i64> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_liPl(<8 x i64> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_liPl(<16 x i64> {{.*}}, i32 0, ptr {{.*}})
-
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_ljPU3AS1l(<2 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_ljPU3AS1l(<3 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_ljPU3AS1l(<4 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_ljPU3AS1l(<8 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_ljPU3AS1l(<16 x i64> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_ljPU3AS3l(<2 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_ljPU3AS3l(<3 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_ljPU3AS3l(<4 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_ljPU3AS3l(<8 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_ljPU3AS3l(<16 x i64> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_ljPl(<2 x i64> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_ljPl(<3 x i64> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_ljPl(<4 x i64> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_ljPl(<8 x i64> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_ljPl(<16 x i64> {{.*}}, i32 0, ptr {{.*}})
+;
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
@@ -206,22 +206,22 @@
 ; CHECK-CL20: call spir_func void @_Z8vstore16Dv16_ljPl(<16 x i64> {{.*}}, i32 0, ptr {{.*}})
  
 ; CHECK-LABEL: spir_kernel void @testHalf
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_DhiPU3AS1Dh(<2 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_DhiPU3AS1Dh(<3 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_DhiPU3AS1Dh(<4 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_DhiPU3AS1Dh(<8 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_DhiPU3AS1Dh(<16 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_DhiPU3AS3Dh(<2 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_DhiPU3AS3Dh(<3 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_DhiPU3AS3Dh(<4 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_DhiPU3AS3Dh(<8 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_DhiPU3AS3Dh(<16 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_DhiPDh(<2 x half> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_DhiPDh(<3 x half> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_DhiPDh(<4 x half> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_DhiPDh(<8 x half> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_DhiPDh(<16 x half> {{.*}}, i32 0, ptr {{.*}})
- 
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_DhjPU3AS1Dh(<2 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_DhjPU3AS1Dh(<3 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_DhjPU3AS1Dh(<4 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_DhjPU3AS1Dh(<8 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_DhjPU3AS1Dh(<16 x half> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_DhjPU3AS3Dh(<2 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_DhjPU3AS3Dh(<3 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_DhjPU3AS3Dh(<4 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_DhjPU3AS3Dh(<8 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_DhjPU3AS3Dh(<16 x half> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_DhjPDh(<2 x half> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_DhjPDh(<3 x half> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_DhjPDh(<4 x half> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_DhjPDh(<8 x half> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_DhjPDh(<16 x half> {{.*}}, i32 0, ptr {{.*}})
+;
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
@@ -255,22 +255,22 @@
 ; CHECK-CL20: call spir_func void @_Z8vstore16Dv16_DhjPDh(<16 x half> {{.*}}, i32 0, ptr {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testFloat
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_fiPU3AS1f(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_fiPU3AS1f(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_fiPU3AS1f(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_fiPU3AS1f(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_fiPU3AS1f(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_fiPU3AS3f(<2 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_fiPU3AS3f(<3 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_fiPU3AS3f(<4 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_fiPU3AS3f(<8 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_fiPU3AS3f(<16 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_fiPf(<2 x float> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_fiPf(<3 x float> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_fiPf(<4 x float> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_fiPf(<8 x float> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_fiPf(<16 x float> {{.*}}, i32 0, ptr {{.*}})
-
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_fjPU3AS1f(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_fjPU3AS1f(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_fjPU3AS1f(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_fjPU3AS1f(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_fjPU3AS1f(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_fjPU3AS3f(<2 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_fjPU3AS3f(<3 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_fjPU3AS3f(<4 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_fjPU3AS3f(<8 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_fjPU3AS3f(<16 x float> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_fjPf(<2 x float> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_fjPf(<3 x float> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_fjPf(<4 x float> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_fjPf(<8 x float> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_fjPf(<16 x float> {{.*}}, i32 0, ptr {{.*}})
+;
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
@@ -304,22 +304,22 @@
 ; CHECK-CL20: call spir_func void @_Z8vstore16Dv16_fjPf(<16 x float> {{.*}}, i32 0, ptr {{.*}})
 
 ; CHECK-LABEL: spir_kernel void @testDouble
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_diPU3AS1d(<2 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_diPU3AS1d(<3 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_diPU3AS1d(<4 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_diPU3AS1d(<8 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_diPU3AS1d(<16 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_diPU3AS3d(<2 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_diPU3AS3d(<3 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_diPU3AS3d(<4 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_diPU3AS3d(<8 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_diPU3AS3d(<16 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_diPd(<2 x double> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_diPd(<3 x double> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_diPd(<4 x double> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_diPd(<8 x double> {{.*}}, i32 0, ptr {{.*}})
-; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_diPd(<16 x double> {{.*}}, i32 0, ptr {{.*}})
-
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_djPU3AS1d(<2 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_djPU3AS1d(<3 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_djPU3AS1d(<4 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_djPU3AS1d(<8 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_djPU3AS1d(<16 x double> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_djPU3AS3d(<2 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_djPU3AS3d(<3 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_djPU3AS3d(<4 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_djPU3AS3d(<8 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_djPU3AS3d(<16 x double> {{.*}}, i32 0, ptr addrspace(3) {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_djPd(<2 x double> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv3_djPd(<3 x double> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv4_djPd(<4 x double> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv8_djPd(<8 x double> {{.*}}, i32 0, ptr {{.*}})
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv16_djPd(<16 x double> {{.*}}, i32 0, ptr {{.*}})
+;
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren
 ; CHECK-SPV-BACK ExtInst [[VoidTy]] {{.*}} [[Set]] vstoren

From be1c2d3030265f66603f8e63dcaef829785d1477 Mon Sep 17 00:00:00 2001
From: "Maksimova, Viktoria" <viktoria.maksimova@intel.com>
Date: Fri, 13 Mar 2026 04:05:48 -0700
Subject: [PATCH 4/7] [Backport to 16] [LLVM->SPV-IR] Add const to
 GroupAsyncCopy/GenericPtrMemSemantics/vload* source pointer (#3480)

Movtivation is similar to 96f5ade2:
* Align with OpenCL builtin.
* Align with their declarations in
https://github.com/intel/llvm/blob/sycl/clang/lib/Sema/SPIRVBuiltins.td.
* Targets consuming SPV-IR don't need to implement both const and
non-const builtin variants; that duplication only bloats the builtin
library without any benefit.
---
 lib/SPIRV/SPIRVUtil.cpp                      |   5 +
 test/OpenCL.std/vload_half.spvasm            |  32 +--
 test/OpenCL.std/vload_halfn.spvasm           |  40 +--
 test/OpenCL.std/vloada_halfn.spvasm          |  40 +--
 test/OpenCL.std/vloadn.spvasm                | 280 +++++++++----------
 test/transcoding/OpGenericPtrMemSemantics.ll |   2 +-
 test/transcoding/OpGroupAsyncCopy.ll         |   4 +-
 7 files changed, 204 insertions(+), 199 deletions(-)

diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
index 0d940453b6..53f1e2d56e 100644
--- a/lib/SPIRV/SPIRVUtil.cpp
+++ b/lib/SPIRV/SPIRVUtil.cpp
@@ -2538,6 +2538,7 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
       addUnsignedArg(3);
       break;
     case OpGroupAsyncCopy:
+      setArgAttr(2, SPIR::ATTR_CONST);
       addUnsignedArg(3);
       addUnsignedArg(4);
       break;
@@ -2681,6 +2682,9 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case internal::OpConvertHandleToSampledImageINTEL:
       addUnsignedArg(0);
       break;
+    case OpGenericPtrMemSemantics:
+      setArgAttr(0, SPIR::ATTR_CONST);
+      break;
     default:;
       // No special handling is needed
     }
@@ -2753,6 +2757,7 @@ class OpenCLStdToSPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpenCLLIB::Vload_halfn:
     case OpenCLLIB::Vloada_halfn:
       addUnsignedArg(0);
+      setArgAttr(1, SPIR::ATTR_CONST);
       break;
     case OpenCLLIB::Vstoren:
     case OpenCLLIB::Vstore_half:
diff --git a/test/OpenCL.std/vload_half.spvasm b/test/OpenCL.std/vload_half.spvasm
index 3932566975..005a5b6d62 100644
--- a/test/OpenCL.std/vload_half.spvasm
+++ b/test/OpenCL.std/vload_half.spvasm
@@ -6,22 +6,22 @@
 ;
 ; CHECK-LABEL: spir_kernel void @test
 ;
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
-; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2KDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPKDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPKDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPKDh(
+; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPKDh(
 ;
 ; CHECK-CL20: call spir_func float @_Z10vload_halfjPU3AS1KDh
 ; CHECK-CL20: call spir_func float @_Z10vload_halfjPU3AS1KDh
diff --git a/test/OpenCL.std/vload_halfn.spvasm b/test/OpenCL.std/vload_halfn.spvasm
index f86a9a202e..0b1af99003 100644
--- a/test/OpenCL.std/vload_halfn.spvasm
+++ b/test/OpenCL.std/vload_halfn.spvasm
@@ -6,26 +6,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @test
 ;
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPDhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPDhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPDhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPDhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPKDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPKDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPKDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPKDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPKDhi(
 ;
 ; CHECK-CL20: call spir_func <2 x float> @_Z11vload_half2jPU3AS1KDh(
 ; CHECK-CL20: call spir_func <3 x float> @_Z11vload_half3jPU3AS1KDh(
diff --git a/test/OpenCL.std/vloada_halfn.spvasm b/test/OpenCL.std/vloada_halfn.spvasm
index b93b2e20cc..317ad4946c 100644
--- a/test/OpenCL.std/vloada_halfn.spvasm
+++ b/test/OpenCL.std/vloada_halfn.spvasm
@@ -6,26 +6,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @test
 ;
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPDhi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPDhi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPDhi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPDhi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPKDhi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPKDhi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPKDhi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPKDhi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPKDhi(
 ;
 ; CHECK-CL20: call spir_func <2 x float> @_Z12vloada_half2jPU3AS1KDh(
 ; CHECK-CL20: call spir_func <3 x float> @_Z12vloada_half3jPU3AS1KDh(
diff --git a/test/OpenCL.std/vloadn.spvasm b/test/OpenCL.std/vloadn.spvasm
index 093ffd233a..9fa74e90fd 100644
--- a/test/OpenCL.std/vloadn.spvasm
+++ b/test/OpenCL.std/vloadn.spvasm
@@ -6,26 +6,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testChar
 ;
-; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPU3AS1ci(
-; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPU3AS3ci(
-; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPU3AS2ci(
-; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPci(
-; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPci(
-; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPci(
-; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPci(
-; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPci(
+; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPU3AS1Kci(
+; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPU3AS1Kci(
+; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPU3AS1Kci(
+; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPU3AS1Kci(
+; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPU3AS1Kci(
+; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPU3AS3Kci(
+; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPU3AS3Kci(
+; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPU3AS3Kci(
+; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPU3AS3Kci(
+; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPU3AS3Kci(
+; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPU3AS2Kci(
+; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPU3AS2Kci(
+; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPU3AS2Kci(
+; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPU3AS2Kci(
+; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPU3AS2Kci(
+; CHECK-SPV-IR: call spir_func <2 x i8> @_Z25__spirv_ocl_vloadn_Rchar2jPKci(
+; CHECK-SPV-IR: call spir_func <3 x i8> @_Z25__spirv_ocl_vloadn_Rchar3jPKci(
+; CHECK-SPV-IR: call spir_func <4 x i8> @_Z25__spirv_ocl_vloadn_Rchar4jPKci(
+; CHECK-SPV-IR: call spir_func <8 x i8> @_Z25__spirv_ocl_vloadn_Rchar8jPKci(
+; CHECK-SPV-IR: call spir_func <16 x i8> @_Z26__spirv_ocl_vloadn_Rchar16jPKci(
 ;
 ; CHECK-CL20: call spir_func <2 x i8> @_Z6vload2jPU3AS1Kc(
 ; CHECK-CL20: call spir_func <3 x i8> @_Z6vload3jPU3AS1Kc(
@@ -50,26 +50,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testShort
 ;
-; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPU3AS1si(
-; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPU3AS1si(
-; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPU3AS1si(
-; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPU3AS1si(
-; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPU3AS1si(
-; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPU3AS3si(
-; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPU3AS3si(
-; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPU3AS3si(
-; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPU3AS3si(
-; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPU3AS3si(
-; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPU3AS2si(
-; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPU3AS2si(
-; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPU3AS2si(
-; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPU3AS2si(
-; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPU3AS2si(
-; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPsi(
-; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPsi(
-; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPsi(
-; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPsi(
-; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPsi(
+; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPU3AS1Ksi(
+; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPU3AS1Ksi(
+; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPU3AS1Ksi(
+; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPU3AS1Ksi(
+; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPU3AS1Ksi(
+; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPU3AS3Ksi(
+; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPU3AS3Ksi(
+; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPU3AS3Ksi(
+; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPU3AS3Ksi(
+; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPU3AS3Ksi(
+; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPU3AS2Ksi(
+; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPU3AS2Ksi(
+; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPU3AS2Ksi(
+; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPU3AS2Ksi(
+; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPU3AS2Ksi(
+; CHECK-SPV-IR: call spir_func <2 x i16> @_Z26__spirv_ocl_vloadn_Rshort2jPKsi(
+; CHECK-SPV-IR: call spir_func <3 x i16> @_Z26__spirv_ocl_vloadn_Rshort3jPKsi(
+; CHECK-SPV-IR: call spir_func <4 x i16> @_Z26__spirv_ocl_vloadn_Rshort4jPKsi(
+; CHECK-SPV-IR: call spir_func <8 x i16> @_Z26__spirv_ocl_vloadn_Rshort8jPKsi(
+; CHECK-SPV-IR: call spir_func <16 x i16> @_Z27__spirv_ocl_vloadn_Rshort16jPKsi(
 ;
 ; CHECK-CL20: call spir_func <2 x i16> @_Z6vload2jPU3AS1Ks(
 ; CHECK-CL20: call spir_func <3 x i16> @_Z6vload3jPU3AS1Ks(
@@ -94,26 +94,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testInt
 ;
-; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPU3AS1ii(
-; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPU3AS3ii(
-; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPU3AS2ii(
-; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPii(
-; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPii(
-; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPii(
-; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPii(
-; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPii(
+; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPU3AS1Kii(
+; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPU3AS1Kii(
+; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPU3AS1Kii(
+; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPU3AS1Kii(
+; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPU3AS1Kii(
+; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPU3AS3Kii(
+; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPU3AS3Kii(
+; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPU3AS3Kii(
+; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPU3AS3Kii(
+; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPU3AS3Kii(
+; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPU3AS2Kii(
+; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPU3AS2Kii(
+; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPU3AS2Kii(
+; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPU3AS2Kii(
+; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPU3AS2Kii(
+; CHECK-SPV-IR: call spir_func <2 x i32> @_Z24__spirv_ocl_vloadn_Rint2jPKii(
+; CHECK-SPV-IR: call spir_func <3 x i32> @_Z24__spirv_ocl_vloadn_Rint3jPKii(
+; CHECK-SPV-IR: call spir_func <4 x i32> @_Z24__spirv_ocl_vloadn_Rint4jPKii(
+; CHECK-SPV-IR: call spir_func <8 x i32> @_Z24__spirv_ocl_vloadn_Rint8jPKii(
+; CHECK-SPV-IR: call spir_func <16 x i32> @_Z25__spirv_ocl_vloadn_Rint16jPKii(
 ;
 ; CHECK-CL20: call spir_func <2 x i32> @_Z6vload2jPU3AS1Ki(
 ; CHECK-CL20: call spir_func <3 x i32> @_Z6vload3jPU3AS1Ki(
@@ -138,26 +138,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testLong
 ;
-; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPU3AS1li(
-; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPU3AS1li(
-; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPU3AS1li(
-; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPU3AS1li(
-; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPU3AS1li(
-; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPU3AS3li(
-; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPU3AS3li(
-; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPU3AS3li(
-; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPU3AS3li(
-; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPU3AS3li(
-; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPU3AS2li(
-; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPU3AS2li(
-; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPU3AS2li(
-; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPU3AS2li(
-; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPU3AS2li(
-; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPli(
-; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPli(
-; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPli(
-; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPli(
-; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPli(
+; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPU3AS1Kli(
+; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPU3AS1Kli(
+; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPU3AS1Kli(
+; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPU3AS1Kli(
+; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPU3AS1Kli(
+; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPU3AS3Kli(
+; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPU3AS3Kli(
+; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPU3AS3Kli(
+; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPU3AS3Kli(
+; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPU3AS3Kli(
+; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPU3AS2Kli(
+; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPU3AS2Kli(
+; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPU3AS2Kli(
+; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPU3AS2Kli(
+; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPU3AS2Kli(
+; CHECK-SPV-IR: call spir_func <2 x i64> @_Z25__spirv_ocl_vloadn_Rlong2jPKli(
+; CHECK-SPV-IR: call spir_func <3 x i64> @_Z25__spirv_ocl_vloadn_Rlong3jPKli(
+; CHECK-SPV-IR: call spir_func <4 x i64> @_Z25__spirv_ocl_vloadn_Rlong4jPKli(
+; CHECK-SPV-IR: call spir_func <8 x i64> @_Z25__spirv_ocl_vloadn_Rlong8jPKli(
+; CHECK-SPV-IR: call spir_func <16 x i64> @_Z26__spirv_ocl_vloadn_Rlong16jPKli(
 ;
 ; CHECK-CL20: call spir_func <2 x i64> @_Z6vload2jPU3AS1Kl(
 ; CHECK-CL20: call spir_func <3 x i64> @_Z6vload3jPU3AS1Kl(
@@ -182,26 +182,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testHalf
 ;
-; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPU3AS1Dhi(
-; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPU3AS3Dhi(
-; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPU3AS2Dhi(
-; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPDhi(
-; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPDhi(
-; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPDhi(
-; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPDhi(
-; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPDhi(
+; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPU3AS1KDhi(
+; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPU3AS3KDhi(
+; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPU3AS2KDhi(
+; CHECK-SPV-IR: call spir_func <2 x half> @_Z25__spirv_ocl_vloadn_Rhalf2jPKDhi(
+; CHECK-SPV-IR: call spir_func <3 x half> @_Z25__spirv_ocl_vloadn_Rhalf3jPKDhi(
+; CHECK-SPV-IR: call spir_func <4 x half> @_Z25__spirv_ocl_vloadn_Rhalf4jPKDhi(
+; CHECK-SPV-IR: call spir_func <8 x half> @_Z25__spirv_ocl_vloadn_Rhalf8jPKDhi(
+; CHECK-SPV-IR: call spir_func <16 x half> @_Z26__spirv_ocl_vloadn_Rhalf16jPKDhi(
 ;
 ; CHECK-CL20: call spir_func <2 x half> @_Z6vload2jPU3AS1KDh(
 ; CHECK-CL20: call spir_func <3 x half> @_Z6vload3jPU3AS1KDh(
@@ -226,26 +226,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testFloat
 ;
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPU3AS1fi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPU3AS3fi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPU3AS2fi(
-; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPfi(
-; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPfi(
-; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPfi(
-; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPfi(
-; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPfi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPU3AS1Kfi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPU3AS1Kfi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPU3AS1Kfi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPU3AS1Kfi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPU3AS1Kfi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPU3AS3Kfi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPU3AS3Kfi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPU3AS3Kfi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPU3AS3Kfi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPU3AS3Kfi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPU3AS2Kfi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPU3AS2Kfi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPU3AS2Kfi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPU3AS2Kfi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPU3AS2Kfi(
+; CHECK-SPV-IR: call spir_func <2 x float> @_Z26__spirv_ocl_vloadn_Rfloat2jPKfi(
+; CHECK-SPV-IR: call spir_func <3 x float> @_Z26__spirv_ocl_vloadn_Rfloat3jPKfi(
+; CHECK-SPV-IR: call spir_func <4 x float> @_Z26__spirv_ocl_vloadn_Rfloat4jPKfi(
+; CHECK-SPV-IR: call spir_func <8 x float> @_Z26__spirv_ocl_vloadn_Rfloat8jPKfi(
+; CHECK-SPV-IR: call spir_func <16 x float> @_Z27__spirv_ocl_vloadn_Rfloat16jPKfi(
 ;
 ; CHECK-CL20: call spir_func <2 x float> @_Z6vload2jPU3AS1Kf(
 ; CHECK-CL20: call spir_func <3 x float> @_Z6vload3jPU3AS1Kf(
@@ -270,26 +270,26 @@
 ;
 ; CHECK-LABEL: spir_kernel void @testDouble
 ;
-; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPU3AS1di(
-; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPU3AS1di(
-; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPU3AS1di(
-; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPU3AS1di(
-; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPU3AS1di(
-; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPU3AS3di(
-; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPU3AS3di(
-; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPU3AS3di(
-; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPU3AS3di(
-; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPU3AS3di(
-; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPU3AS2di(
-; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPU3AS2di(
-; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPU3AS2di(
-; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPU3AS2di(
-; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPU3AS2di(
-; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPdi(
-; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPdi(
-; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPdi(
-; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPdi(
-; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPdi(
+; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPU3AS1Kdi(
+; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPU3AS1Kdi(
+; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPU3AS1Kdi(
+; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPU3AS1Kdi(
+; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPU3AS1Kdi(
+; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPU3AS3Kdi(
+; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPU3AS3Kdi(
+; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPU3AS3Kdi(
+; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPU3AS3Kdi(
+; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPU3AS3Kdi(
+; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPU3AS2Kdi(
+; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPU3AS2Kdi(
+; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPU3AS2Kdi(
+; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPU3AS2Kdi(
+; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPU3AS2Kdi(
+; CHECK-SPV-IR: call spir_func <2 x double> @_Z27__spirv_ocl_vloadn_Rdouble2jPKdi(
+; CHECK-SPV-IR: call spir_func <3 x double> @_Z27__spirv_ocl_vloadn_Rdouble3jPKdi(
+; CHECK-SPV-IR: call spir_func <4 x double> @_Z27__spirv_ocl_vloadn_Rdouble4jPKdi(
+; CHECK-SPV-IR: call spir_func <8 x double> @_Z27__spirv_ocl_vloadn_Rdouble8jPKdi(
+; CHECK-SPV-IR: call spir_func <16 x double> @_Z28__spirv_ocl_vloadn_Rdouble16jPKdi(
 ;
 ; CHECK-CL20: call spir_func <2 x double> @_Z6vload2jPU3AS1Kd(
 ; CHECK-CL20: call spir_func <3 x double> @_Z6vload3jPU3AS1Kd(
diff --git a/test/transcoding/OpGenericPtrMemSemantics.ll b/test/transcoding/OpGenericPtrMemSemantics.ll
index fc44cd4d40..20e72f65bb 100644
--- a/test/transcoding/OpGenericPtrMemSemantics.ll
+++ b/test/transcoding/OpGenericPtrMemSemantics.ll
@@ -11,7 +11,7 @@
 ; CHECK-SPIRV: 4 GenericPtrMemSemantics {{[0-9]+}} [[ResID:[0-9]+]] {{[0-9]+}}
 ; CHECK-SPIRV-NEXT: 5 ShiftRightLogical {{[0-9]+}} {{[0-9]+}} [[ResID]] {{[0-9]+}}
 
-; CHECK-SPV-IR: call spir_func i32 @_Z30__spirv_GenericPtrMemSemanticsPU3AS4c(ptr addrspace(4) {{.*}})
+; CHECK-SPV-IR: call spir_func i32 @_Z30__spirv_GenericPtrMemSemanticsPU3AS4Kc(ptr addrspace(4) {{.*}})
 ; CHECK-SPV-IR: lshr
 
 ; Note that round-trip conversion replaces 'get_fence (gentype *ptr)' built-in function with 'get_fence (const gentype *ptr)'.
diff --git a/test/transcoding/OpGroupAsyncCopy.ll b/test/transcoding/OpGroupAsyncCopy.ll
index 0cdc4f14f8..7241c56a36 100644
--- a/test/transcoding/OpGroupAsyncCopy.ll
+++ b/test/transcoding/OpGroupAsyncCopy.ll
@@ -13,9 +13,9 @@
 ; CHECK-LLVM: declare spir_func %opencl.event_t* @_Z29async_work_group_strided_copyPU3AS1Dv2_hPU3AS3KS_jj9ocl_event(<2 x i8> addrspace(1)*, <2 x i8> addrspace(3)*, i32, i32, %opencl.event_t*)
 ; CHECK-LLVM: declare spir_func void @_Z17wait_group_eventsiPU3AS49ocl_event(i32, %opencl.event_t* addrspace(4)*)
 
-; CHECK-SPV-IR: call spir_func %spirv.Event* @_Z22__spirv_GroupAsyncCopyiPU3AS1Dv2_cPU3AS3S_jjP13__spirv_Event(i32 2
+; CHECK-SPV-IR: call spir_func %spirv.Event* @_Z22__spirv_GroupAsyncCopyiPU3AS1Dv2_cPU3AS3KS_jjP13__spirv_Event(i32 2
 ; CHECK-SPV-IR: call spir_func void @_Z23__spirv_GroupWaitEventsiiPU3AS4P13__spirv_Event(i32 2
-; CHECK-SPV-IR: declare spir_func %spirv.Event* @_Z22__spirv_GroupAsyncCopyiPU3AS1Dv2_cPU3AS3S_jjP13__spirv_Event(i32, <2 x i8> addrspace(1)*, <2 x i8> addrspace(3)*, i32, i32, %spirv.Event*
+; CHECK-SPV-IR: declare spir_func %spirv.Event* @_Z22__spirv_GroupAsyncCopyiPU3AS1Dv2_cPU3AS3KS_jjP13__spirv_Event(i32, <2 x i8> addrspace(1)*, <2 x i8> addrspace(3)*, i32, i32, %spirv.Event*
 ; CHECK-SPV-IR: declare spir_func void @_Z23__spirv_GroupWaitEventsiiPU3AS4P13__spirv_Event(i32, i32, %spirv.Event* addrspace(4)*)
 
 ; CHECK-SPIRV-DAG: GroupAsyncCopy {{[0-9]+}} {{[0-9]+}} [[Scope:[0-9]+]]

From 1ed44fb11e154fa00d4a74f2a780e44df08f05f8 Mon Sep 17 00:00:00 2001
From: "Maksimova, Viktoria" <viktoria.maksimova@intel.com>
Date: Fri, 13 Mar 2026 04:05:48 -0700
Subject: [PATCH 5/7] [Backport to 16] Fix BFloat16 argument type demangling
 (#3563)

Ensure we get all the information about parameter types from the mangled builtin name.
---
 lib/SPIRV/SPIRVUtil.cpp                       |  5 ++
 .../bfloat16_math.ll                          |  0
 .../vload_vstore.ll                           | 61 +++++++++++++++++++
 3 files changed, 66 insertions(+)
 rename test/extensions/INTEL/{SPV_INTEL_bfloat16 => SPV_INTEL_bfloat16_arithmetic}/bfloat16_math.ll (100%)
 create mode 100644 test/extensions/INTEL/SPV_INTEL_bfloat16_arithmetic/vload_vstore.ll

diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
index 53f1e2d56e..6067bbf238 100644
--- a/lib/SPIRV/SPIRVUtil.cpp
+++ b/lib/SPIRV/SPIRVUtil.cpp
@@ -696,6 +696,7 @@ static Type *parsePrimitiveType(LLVMContext &Ctx, StringRef Name) {
       .Cases("long", "unsigned long", Type::getInt64Ty(Ctx))
       .Cases("long long", "unsigned long long", Type::getInt64Ty(Ctx))
       .Case("half", Type::getHalfTy(Ctx))
+      .Case("std::bfloat16_t", Type::getBFloatTy(Ctx))
       .Case("float", Type::getFloatTy(Ctx))
       .Case("double", Type::getDoubleTy(Ctx))
       .Case("void", Type::getInt8Ty(Ctx))
@@ -876,6 +877,10 @@ parseNode(Module *M, const llvm::itanium_demangle::Node *ParamType,
       // struct types were are looking for here.
     }
   } else if (auto *VendorTy = dyn_cast<VendorExtQualType>(ParamType)) {
+    if (auto *NameTy = dyn_cast<NameType>(VendorTy->getTy())) {
+      if (NameTy->getName() == "std::bfloat16_t")
+        PointeeTy = llvm::Type::getBFloatTy(M->getContext());
+    }
     // This is a block parameter. Decode the pointee type as if it were a
     // void (*)(void) function pointer type.
     if (VendorTy->getExt() == "block_pointer") {
diff --git a/test/extensions/INTEL/SPV_INTEL_bfloat16/bfloat16_math.ll b/test/extensions/INTEL/SPV_INTEL_bfloat16_arithmetic/bfloat16_math.ll
similarity index 100%
rename from test/extensions/INTEL/SPV_INTEL_bfloat16/bfloat16_math.ll
rename to test/extensions/INTEL/SPV_INTEL_bfloat16_arithmetic/bfloat16_math.ll
diff --git a/test/extensions/INTEL/SPV_INTEL_bfloat16_arithmetic/vload_vstore.ll b/test/extensions/INTEL/SPV_INTEL_bfloat16_arithmetic/vload_vstore.ll
new file mode 100644
index 0000000000..7b742b3f3a
--- /dev/null
+++ b/test/extensions/INTEL/SPV_INTEL_bfloat16_arithmetic/vload_vstore.ll
@@ -0,0 +1,61 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -spirv-text -o %t.spt --spirv-ext=+SPV_KHR_bfloat16,+SPV_INTEL_bfloat16_arithmetic
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv -to-binary %t.spt -o %t.spv
+; TODO: reenable the validation once the BFloat16 type is supported in ExtInst.
+; Currently fails with: ExtInst doesn't support BFloat16 type.
+; RUNx: spirv-val %t.spv
+; RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o %t.rev.ll
+; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
+; RUN: llvm-spirv -r %t.spv --spirv-target-env=SPV-IR -o - | llvm-dis -o %t.rev.ll
+; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-SPV-IR
+
+
+; CHECK-SPIRV: Capability BFloat16TypeKHR
+; CHECK-SPIRV: Extension "SPV_KHR_bfloat16"
+; CHECK-SPIRV: TypeFloat [[#BFLOAT:]] 16 0
+; CHECK-SPIRV: TypeVector [[#VEC:]] [[#BFLOAT]] 2
+; CHECK-SPIRV: TypePointer [[#PTR:]] [[#]] [[#BFLOAT]]
+
+; CHECK-LABEL: Function
+; CHECK-SPIRV: FunctionParameter [[#PTR]] [[#PTR_ARG:]]
+; CHECK-SPIRV: ExtInst [[#VEC]] [[#]] [[#]] vloadn [[#]] [[#PTR_ARG]] 2
+
+; CHECK-LABEL: Function
+; CHECK-SPIRV: FunctionParameter [[#VEC]] [[#DATA_ARG:]]
+; CHECK-SPIRV: FunctionParameter [[#PTR]] [[#PTR_ARG2:]]
+; CHECK-SPIRV: ExtInst [[#]] [[#]] [[#]] vstoren [[#DATA_ARG]] [[#]] [[#PTR_ARG2]]
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
+target triple = "spir64-unknown-unknown"
+
+; CHECK-LLVM: call spir_func <2 x bfloat> @_Z6vload2mPU3AS1KDF16b(i64 %offset, ptr addrspace(1) %ptr)
+; CHECK-LLVM: call spir_func void @_Z7vstore2Dv2_DF16bmPU3AS1DF16b(<2 x bfloat> %data, i64 %offset, ptr addrspace(1) %ptr)
+
+; CHECK-SPV-IR: call spir_func <2 x bfloat> @_Z26__spirv_ocl_vloadn_RDF16b2mPU3AS1KDF16bi(i64 %offset, ptr addrspace(1) %ptr, i32 2)
+; CHECK-SPV-IR: call spir_func void @_Z19__spirv_ocl_vstorenDv2_DF16bmPU3AS1DF16b(<2 x bfloat> %data, i64 %offset, ptr addrspace(1) %ptr)
+
+define spir_func <2 x bfloat> @test_spirv_ocl_vload2(i64 %offset, ptr addrspace(1) %ptr) {
+  %result = call spir_func <2 x bfloat> @_Z26__spirv_ocl_vloadn__RDF16blPU3AS1DF16bi(i64 %offset, ptr addrspace(1) %ptr, i32 2)
+  ret <2 x bfloat> %result
+}
+
+define spir_func void @test_spirv_ocl_vstore2(<2 x bfloat> %data, i64 %offset, ptr addrspace(1) %ptr) {
+  call spir_func void @_Z19__spirv_ocl_vstorenDv2_DF16blPU3AS1DF16b(<2 x bfloat> %data, i64 %offset, ptr addrspace(1) %ptr)
+  ret void
+}
+
+declare spir_func <2 x bfloat> @_Z26__spirv_ocl_vloadn__RDF16blPU3AS1DF16bi(i64, bfloat addrspace(1)*, i32)
+declare spir_func void @_Z19__spirv_ocl_vstorenDv2_DF16blPU3AS1DF16b(<2 x bfloat>, i64, bfloat addrspace(1)*)
+
+!opencl.enable.FP_CONTRACT = !{}
+!opencl.spir.version = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.used.extensions = !{!2}
+!opencl.used.optional.core.features = !{!3}
+!opencl.compiler.options = !{!3}
+
+!0 = !{i32 1, i32 2}
+!1 = !{i32 2, i32 0}
+!2 = !{!"cl_khr_fp16"}
+!3 = !{}

From e5d399aba0f79410347f6565dd7df5ca84638bf3 Mon Sep 17 00:00:00 2001
From: "Maksimova, Viktoria" <viktoria.maksimova@intel.com>
Date: Fri, 13 Mar 2026 04:05:48 -0700
Subject: [PATCH 6/7] [Backport to 16] Update OCL nan builtin translation to
 work with bfloat type (#3558)

To avoid name clash between builtins with `half` and `bfloat` return types, introduce return type postfix for
`bfloat nan` builtin in reverse translation to SPIR-V Friendly IR.
---
 lib/SPIRV/SPIRVUtil.cpp               |  8 +++++-
 test/transcoding/OpenCL/nan_bfloat.ll | 36 +++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100644 test/transcoding/OpenCL/nan_bfloat.ll

diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
index 6067bbf238..bba2f1f566 100644
--- a/lib/SPIRV/SPIRVUtil.cpp
+++ b/lib/SPIRV/SPIRVUtil.cpp
@@ -2704,7 +2704,7 @@ class OpenCLStdToSPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
 public:
   OpenCLStdToSPIRVFriendlyIRMangleInfo(OCLExtOpKind ExtOpId,
                                        ArrayRef<Type *> ArgTys, Type *RetTy)
-      : ExtOpId(ExtOpId), ArgTys(ArgTys) {
+      : ExtOpId(ExtOpId), ArgTys(ArgTys), RetTy(RetTy) {
 
     std::string Postfix = "";
     if (needRetTypePostfix())
@@ -2720,6 +2720,11 @@ class OpenCLStdToSPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpenCLLIB::Vloada_halfn:
     case OpenCLLIB::Vloadn:
       return true;
+    case OpenCLLIB::Nan:
+      // Only add return type mangling for bfloat16 to disambiguate from half
+      // (both are represented as i16 in LLVM). Float and half use traditional
+      // naming for backward compatibility.
+      return RetTy->getScalarType()->isBFloatTy();
     default:
       return false;
     }
@@ -2781,6 +2786,7 @@ class OpenCLStdToSPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
 private:
   OCLExtOpKind ExtOpId;
   ArrayRef<Type *> ArgTys;
+  Type *RetTy;
 };
 } // namespace
 
diff --git a/test/transcoding/OpenCL/nan_bfloat.ll b/test/transcoding/OpenCL/nan_bfloat.ll
new file mode 100644
index 0000000000..517a58a9cb
--- /dev/null
+++ b/test/transcoding/OpenCL/nan_bfloat.ll
@@ -0,0 +1,36 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_KHR_bfloat16 -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; RUN: llvm-spirv -r %t.spv --spirv-target-env=SPV-IR -o - | llvm-dis -o %t.rev.ll
+; RUN: FileCheck < %t.rev.ll %s --check-prefixes=CHECK-SPV-IR
+
+; Check OpenCL built-in nan translation.
+; Verify it's possible to distinguish between bfloat and half versions.
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64-G1"
+target triple = "spir64"
+
+; CHECK-SPIRV: TypeFloat [[#BFLOAT:]] 16 0 {{$}}
+; CHECK-SPIRV: TypeFloat [[#HALF:]] 16 {{$}}
+; CHECK-SPIRV: ExtInst [[#BFLOAT]] [[#]] [[#]] nan
+; CHECK-SPIRV: ExtInst [[#HALF]] [[#]] [[#]] nan
+
+; CHECK-SPV-IR: call spir_func bfloat @_Z22__spirv_ocl_nan_RDF16bt(
+; CHECK-SPV-IR: call spir_func half @_Z15__spirv_ocl_nant(
+
+define dso_local spir_kernel void @test_bfloat(ptr addrspace(1) align 2 %a, i16 %b) {
+entry:
+  %call = tail call spir_func bfloat @_Z23__spirv_ocl_nan__RDF16bt(i16 %b)
+  %call2 = tail call spir_func half @_Z22__spirv_ocl_nan__Rhalft(i16 %b)
+  ret void
+}
+
+declare spir_func bfloat @_Z23__spirv_ocl_nan__RDF16bt(i16)
+declare spir_func half @_Z22__spirv_ocl_nan__Rhalft(i16)
+
+
+!opencl.ocl.version = !{!0}
+
+!0 = !{i32 3, i32 0}

From f37f3b44d2647657a2781b4c58ad3587ed9598eb Mon Sep 17 00:00:00 2001
From: "Maksimova, Viktoria" <viktoria.maksimova@intel.com>
Date: Fri, 13 Mar 2026 04:05:49 -0700
Subject: [PATCH 7/7] Workaround for `bfloat16` parameter type demangling

LLVM releases before 20 don't recognise the Itanium mangling `DF16b` for `bfloat16`.
Replace it to the vendor-extended encoding `u6__bf16` before demangling, which all known demangler versions parse correctly as `NameType("__bf16")`.

AI-assisted: Claude Sonnet 4.6 (commercial SaaS)
---
 lib/SPIRV/SPIRVUtil.cpp | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
index bba2f1f566..09cb17e72c 100644
--- a/lib/SPIRV/SPIRVUtil.cpp
+++ b/lib/SPIRV/SPIRVUtil.cpp
@@ -696,7 +696,7 @@ static Type *parsePrimitiveType(LLVMContext &Ctx, StringRef Name) {
       .Cases("long", "unsigned long", Type::getInt64Ty(Ctx))
       .Cases("long long", "unsigned long long", Type::getInt64Ty(Ctx))
       .Case("half", Type::getHalfTy(Ctx))
-      .Case("std::bfloat16_t", Type::getBFloatTy(Ctx))
+      .Cases("std::bfloat16_t", "__bf16", Type::getBFloatTy(Ctx))
       .Case("float", Type::getFloatTy(Ctx))
       .Case("double", Type::getDoubleTy(Ctx))
       .Case("void", Type::getInt8Ty(Ctx))
@@ -878,7 +878,8 @@ parseNode(Module *M, const llvm::itanium_demangle::Node *ParamType,
     }
   } else if (auto *VendorTy = dyn_cast<VendorExtQualType>(ParamType)) {
     if (auto *NameTy = dyn_cast<NameType>(VendorTy->getTy())) {
-      if (NameTy->getName() == "std::bfloat16_t")
+      if (NameTy->getName() == "std::bfloat16_t" ||
+          NameTy->getName() == "__bf16")
         PointeeTy = llvm::Type::getBFloatTy(M->getContext());
     }
     // This is a block parameter. Decode the pointee type as if it were a
@@ -938,13 +939,32 @@ bool getParameterTypes(Function *F, SmallVectorImpl<Type *> &ArgTys,
   if (HasSret)
     ++ArgIter;
 
+  // "DF<N>b" mangling for bfloat<N> types (e.g. DF16b for bfloat16) is
+  // recognized by the demangler only starting from LLVM 20. Replace "DF16b"
+  // in the parameter section with the vendor-extended-type encoding "u6__bf16",
+  // which all known demangler versions parse correctly as NameType("__bf16").
+  std::string PatchedName;
+  StringRef MangledName(F->getName());
+  if (MangledName.contains("DF16b")) {
+    PatchedName = MangledName.str();
+    // Skip "_Z<N><name>" to search only in the parameter section.
+    size_t Start = PatchedName.find_first_not_of("0123456789", 2);
+    size_t Len = 0;
+    StringRef(PatchedName).substr(2, Start - 2).getAsInteger(10, Len);
+    size_t Pos = Start + Len;
+    while ((Pos = PatchedName.find("DF16b", Pos)) != std::string::npos) {
+      PatchedName.replace(Pos, 5, "u6__bf16");
+      Pos += 8;
+    }
+    MangledName = PatchedName;
+  }
+
   // Demangle the function arguments. If we get an input name of
   // "_Z12write_imagei20ocl_image1d_array_woDv2_iiDv4_i", then we expect
   // that Demangler.getFunctionParameters will return
   // "(ocl_image1d_array_wo, int __vector(2), int, int __vector(4))" (in other
   // words, the stuff between the parentheses if you ran C++ filt, including
   // the parentheses itself).
-  const StringRef MangledName(F->getName());
   ManglingParser<DefaultAllocator> Demangler(MangledName.begin(),
                                              MangledName.end());
   // We expect to see only function name encodings here. If it's not a function