Skip to content

Commit 0efc408

Browse files
YaochengerRbb666
Yaochenger
authored and
Rbb666
committed
adapt to rv64ilp32 toolchain
1 parent 393a61b commit 0efc408

File tree

13 files changed

+214
-129
lines changed

13 files changed

+214
-129
lines changed

‎bsp/qemu-virt64-riscv/Kconfig

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,3 +59,7 @@ config ARCH_USING_NEW_CTX_SWITCH
5959
config __STACKSIZE__
6060
int "stack size for interrupt"
6161
default 4096
62+
63+
config RT_USING_RV64ILP32
64+
bool "Use RV64ILP32 toolchain"
65+
default n

‎bsp/qemu-virt64-riscv/README_ZH.md

Lines changed: 53 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44

55
## 1. 简介
66

7-
RISC-V是一种开放和免费的指令集体系结构(ISA)。本工程是在QEMU的RISCV64 VIRT版本上进行的一份移植。
7+
RISC-V是一种开放和免费的指令集体系结构(ISA)。本工程是在QEMU的RISCV64 VIRT版本上进行的一份移植。本工程支持玄铁团队联合中科院软件所共同推出的全球首款rv64ilp32产品级开源工具链。
88

99
## 2. 编译说明
1010

@@ -133,8 +133,59 @@ msh />
133133
| PLIC | 支持 | - |
134134
| CLIC | 支持 | - |
135135

136-
## 5. 联系人信息
136+
## 5.如何使用rv64ilp32工具链
137+
138+
1. 工具链地址：https://github.com/ruyisdk/riscv-gnu-toolchain-rv64ilp32/tags
139+
140+
2. 使用方法：
141+
142+
- 配置工具链路径
143+
144+
- 修改ABI参数为：-mabi=ilp32d
145+
146+
- 使用menuconfig使能下述选项:
147+
148+
```shell
149+
RT_USING_RV64ILP32
150+
```
151+
152+
- 使用menuconfig失能下述选项:
153+
154+
```shell
155+
RT_USING_POSIX_PIPE
156+
RT_USING_POSIX_FS
157+
RT_USING_DFS
158+
```
159+
160+
3. 使用传统64位工具链与使用新32位工具链编译相同工程的固件大小对比：
161+
162+
传统64位工具链固件大小：
163+
164+
```bash
165+
Memory region Used Size Region Size %age Used
166+
SRAM: 225856 B 16 MB 1.35%
167+
riscv64-unknown-elf-objcopy -O binary rtthread.elf rtthread.bin
168+
riscv64-unknown-elf-size rtthread.elf
169+
text data bss dec hex filename
170+
150907 3664 71268 225839 3722f rtthread.elf
171+
```
172+
173+
新32位工具链固件大小：
174+
175+
```bash
176+
Memory region Used Size Region Size %age Used
177+
SRAM: 209376 B 16 MB 1.25%
178+
riscv64-unknown-elf-objcopy -O binary rtthread.elf rtthread.bin
179+
riscv64-unknown-elf-size rtthread.elf
180+
text data bss dec hex filename
181+
138739 1356 69276 209371 331db rtthread.elf
182+
```
183+
184+
## 6. 联系人信息
137185

138186
维护人：[bernard][1]
139187

140188
[1]: https://github.com/BernardXiong
189+
190+
191+

‎bsp/qemu-virt64-riscv/qemu-rv64ilp32-nographic.sh

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
/home/rv/opt-ilp32/bin/qemu-system-riscv64ilp32 -cpu rv64 -M virt -m 256M -nographic -kernel rtthread.elf

‎libcpu/risc-v/virt64/context_gcc.S

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,13 @@
1616
#include "stackframe.h"
1717

1818
.macro PUSH_8 reg
19-
addi sp, sp, -8
19+
addi sp, sp, -REGBYTES
2020
STORE \reg, (sp)
2121
.endm
2222

2323
.macro POP_8 reg
2424
LOAD \reg, (sp)
25-
addi sp, sp, 8
25+
addi sp, sp, REGBYTES
2626
.endm
2727

2828
.macro RESERVE_CONTEXT
@@ -44,11 +44,11 @@
4444
li s10, (SSTATUS_SPP)
4545
or s11, s11, s10
4646
PUSH_8 s11
47-
addi sp, sp, -8
47+
addi sp, sp, -REGBYTES
4848
.endm
4949

5050
.macro RESTORE_CONTEXT
51-
addi sp, sp, 8
51+
addi sp, sp, REGBYTES
5252
POP_8 s11
5353
csrw sstatus, s11
5454
POP_8 s11

‎libcpu/risc-v/virt64/cpuport.c

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2021, RT-Thread Development Team
2+
* Copyright (c) 2006-2024, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -16,6 +16,7 @@
1616
#include "stack.h"
1717
#include <sbi.h>
1818
#include <encoding.h>
19+
#include "regtypes.h"
1920

2021
#define K_SSTATUS_DEFAULT (SSTATUS_SPP | SSTATUS_SPIE | SSTATUS_SUM | SSTATUS_FS)
2122

@@ -35,7 +36,7 @@ volatile rt_ubase_t rt_interrupt_to_thread = 0;
3536
*/
3637
volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
3738

38-
void *_rt_hw_stack_init(rt_ubase_t *sp, rt_ubase_t ra, rt_ubase_t sstatus)
39+
void *_rt_hw_stack_init(rt_uintreg_t *sp, rt_uintreg_t ra, rt_uintreg_t sstatus)
3940
{
4041
(*--sp) = 0; /* tp */
4142
(*--sp) = ra; /* ra */
@@ -80,17 +81,17 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
8081
rt_uint8_t *stack_addr,
8182
void *texit)
8283
{
83-
rt_ubase_t *sp = (rt_ubase_t *)stack_addr;
84+
rt_uintreg_t *sp = (rt_uintreg_t *)stack_addr;
8485
// we use a strict alignment requirement for Q extension
85-
sp = (rt_ubase_t *)RT_ALIGN_DOWN((rt_ubase_t)sp, 16);
86+
sp = (rt_uintreg_t *)RT_ALIGN_DOWN((rt_uintreg_t)sp, 16);
8687

87-
(*--sp) = (rt_ubase_t)tentry;
88-
(*--sp) = (rt_ubase_t)parameter;
89-
(*--sp) = (rt_ubase_t)texit;
88+
(*--sp) = (rt_uintreg_t)tentry;
89+
(*--sp) = (rt_uintreg_t)parameter;
90+
(*--sp) = (rt_uintreg_t)texit;
9091

9192
/* compatible to RESTORE_CONTEXT */
9293
extern void _rt_thread_entry(void);
93-
return (rt_uint8_t *)_rt_hw_stack_init(sp, (rt_ubase_t)_rt_thread_entry, K_SSTATUS_DEFAULT);
94+
return (rt_uint8_t *)_rt_hw_stack_init(sp, (rt_uintreg_t)_rt_thread_entry, K_SSTATUS_DEFAULT);
9495
}
9596

9697
/*

‎libcpu/risc-v/virt64/cpuport.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2021, RT-Thread Development Team
2+
* Copyright (c) 2006-2024, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -17,6 +17,8 @@
1717
#ifdef ARCH_CPU_64BIT
1818
#define STORE sd
1919
#define LOAD ld
20+
#define FSTORE fsd
21+
#define FLOAD fld
2022
#define REGBYTES 8
2123
#else
2224
// error here, not portable

‎libcpu/risc-v/virt64/cpuport_gcc.S

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,11 +14,11 @@
1414

1515
START_POINT(_rt_thread_entry)
1616
LOAD ra, (sp) /* thread exit */
17-
addi sp, sp, 8
17+
addi sp, sp, REGBYTES
1818
LOAD a0, (sp) /* parameter */
19-
addi sp, sp, 8
19+
addi sp, sp, REGBYTES
2020
LOAD t0, (sp) /* tentry */
21-
addi sp, sp, 8
21+
addi sp, sp, REGBYTES
2222
mv s1, ra
2323
jalr t0
2424
jalr s1

‎libcpu/risc-v/virt64/ext_context.h

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2022, RT-Thread Development Team
2+
* Copyright (c) 2006-2024, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -28,38 +28,38 @@
2828
*/
2929

3030
#ifdef ENABLE_FPU
31-
#define FPU_CTX_F0_OFF 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */
32-
#define FPU_CTX_F1_OFF 8 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */
33-
#define FPU_CTX_F2_OFF 16 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */
34-
#define FPU_CTX_F3_OFF 24 /* offsetof(fpu_context_t, fpustatus.f[3]) - offsetof(fpu_context_t, fpustatus.f[0]) */
35-
#define FPU_CTX_F4_OFF 32 /* offsetof(fpu_context_t, fpustatus.f[4]) - offsetof(fpu_context_t, fpustatus.f[0]) */
36-
#define FPU_CTX_F5_OFF 40 /* offsetof(fpu_context_t, fpustatus.f[5]) - offsetof(fpu_context_t, fpustatus.f[0]) */
37-
#define FPU_CTX_F6_OFF 48 /* offsetof(fpu_context_t, fpustatus.f[6]) - offsetof(fpu_context_t, fpustatus.f[0]) */
38-
#define FPU_CTX_F7_OFF 56 /* offsetof(fpu_context_t, fpustatus.f[7]) - offsetof(fpu_context_t, fpustatus.f[0]) */
39-
#define FPU_CTX_F8_OFF 64 /* offsetof(fpu_context_t, fpustatus.f[8]) - offsetof(fpu_context_t, fpustatus.f[0]) */
40-
#define FPU_CTX_F9_OFF 72 /* offsetof(fpu_context_t, fpustatus.f[9]) - offsetof(fpu_context_t, fpustatus.f[0]) */
41-
#define FPU_CTX_F10_OFF 80 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */
42-
#define FPU_CTX_F11_OFF 88 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */
43-
#define FPU_CTX_F12_OFF 96 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */
44-
#define FPU_CTX_F13_OFF 104 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */
45-
#define FPU_CTX_F14_OFF 112 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */
46-
#define FPU_CTX_F15_OFF 120 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */
47-
#define FPU_CTX_F16_OFF 128 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */
48-
#define FPU_CTX_F17_OFF 136 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */
49-
#define FPU_CTX_F18_OFF 144 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */
50-
#define FPU_CTX_F19_OFF 152 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */
51-
#define FPU_CTX_F20_OFF 160 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */
52-
#define FPU_CTX_F21_OFF 168 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */
53-
#define FPU_CTX_F22_OFF 176 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */
54-
#define FPU_CTX_F23_OFF 184 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */
55-
#define FPU_CTX_F24_OFF 192 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */
56-
#define FPU_CTX_F25_OFF 200 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */
57-
#define FPU_CTX_F26_OFF 208 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */
58-
#define FPU_CTX_F27_OFF 216 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */
59-
#define FPU_CTX_F28_OFF 224 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */
60-
#define FPU_CTX_F29_OFF 232 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */
61-
#define FPU_CTX_F30_OFF 240 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */
62-
#define FPU_CTX_F31_OFF 248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */
31+
#define FPU_CTX_F0_OFF REGBYTES * 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */
32+
#define FPU_CTX_F1_OFF REGBYTES * 1 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */
33+
#define FPU_CTX_F2_OFF REGBYTES * 2 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */
34+
#define FPU_CTX_F3_OFF REGBYTES * 3 /* offsetof(fpu_context_t, fpustatus.f[3]) - offsetof(fpu_context_t, fpustatus.f[0]) */
35+
#define FPU_CTX_F4_OFF REGBYTES * 4 /* offsetof(fpu_context_t, fpustatus.f[4]) - offsetof(fpu_context_t, fpustatus.f[0]) */
36+
#define FPU_CTX_F5_OFF REGBYTES * 5 /* offsetof(fpu_context_t, fpustatus.f[5]) - offsetof(fpu_context_t, fpustatus.f[0]) */
37+
#define FPU_CTX_F6_OFF REGBYTES * 6 /* offsetof(fpu_context_t, fpustatus.f[6]) - offsetof(fpu_context_t, fpustatus.f[0]) */
38+
#define FPU_CTX_F7_OFF REGBYTES * 7 /* offsetof(fpu_context_t, fpustatus.f[7]) - offsetof(fpu_context_t, fpustatus.f[0]) */
39+
#define FPU_CTX_F8_OFF REGBYTES * 8 /* offsetof(fpu_context_t, fpustatus.f[8]) - offsetof(fpu_context_t, fpustatus.f[0]) */
40+
#define FPU_CTX_F9_OFF REGBYTES * 9 /* offsetof(fpu_context_t, fpustatus.f[9]) - offsetof(fpu_context_t, fpustatus.f[0]) */
41+
#define FPU_CTX_F10_OFF REGBYTES * 10 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */
42+
#define FPU_CTX_F11_OFF REGBYTES * 11 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */
43+
#define FPU_CTX_F12_OFF REGBYTES * 12 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */
44+
#define FPU_CTX_F13_OFF REGBYTES * 13 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */
45+
#define FPU_CTX_F14_OFF REGBYTES * 14 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */
46+
#define FPU_CTX_F15_OFF REGBYTES * 15 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */
47+
#define FPU_CTX_F16_OFF REGBYTES * 16 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */
48+
#define FPU_CTX_F17_OFF REGBYTES * 17 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */
49+
#define FPU_CTX_F18_OFF REGBYTES * 18 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */
50+
#define FPU_CTX_F19_OFF REGBYTES * 19 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */
51+
#define FPU_CTX_F20_OFF REGBYTES * 20 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */
52+
#define FPU_CTX_F21_OFF REGBYTES * 21 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */
53+
#define FPU_CTX_F22_OFF REGBYTES * 22 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */
54+
#define FPU_CTX_F23_OFF REGBYTES * 23 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */
55+
#define FPU_CTX_F24_OFF REGBYTES * 24 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */
56+
#define FPU_CTX_F25_OFF REGBYTES * 25 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */
57+
#define FPU_CTX_F26_OFF REGBYTES * 26 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */
58+
#define FPU_CTX_F27_OFF REGBYTES * 27 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */
59+
#define FPU_CTX_F28_OFF REGBYTES * 28 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */
60+
#define FPU_CTX_F29_OFF REGBYTES * 29 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */
61+
#define FPU_CTX_F30_OFF REGBYTES * 30 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */
62+
#define FPU_CTX_F31_OFF REGBYTES * 31 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */
6363
#endif /* ENABLE_FPU */
6464

6565
/**
@@ -84,9 +84,9 @@
8484

8585
/**
8686
* @brief save vector extension hardware state
87-
*
87+
*
8888
* @param dst register storing bottom of storage block
89-
*
89+
*
9090
*/
9191
.macro SAVE_VECTOR, dst
9292
mv t1, \dst
@@ -117,9 +117,9 @@
117117

118118
/**
119119
* @brief restore vector extension hardware states
120-
*
120+
*
121121
* @param dst register storing bottom of storage block
122-
*
122+
*
123123
*/
124124
.macro RESTORE_VECTOR, dst
125125
// restore vector registers first since it will modify vector states
@@ -152,4 +152,4 @@
152152

153153
#endif /* __ASSEMBLY__ */
154154

155-
#endif /* __EXT_CONTEXT_H__ */
155+
#endif /* __EXT_CONTEXT_H__ */

‎libcpu/risc-v/virt64/interrupt.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2021, RT-Thread Development Team
2+
* Copyright (c) 2006-2024, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -15,6 +15,7 @@
1515

1616
#include <rthw.h>
1717
#include "stack.h"
18+
#include "regtypes.h"
1819

1920
enum
2021
{
@@ -41,6 +42,6 @@ int rt_hw_plic_irq_disable(int irq_number);
4142
void rt_hw_interrupt_init(void);
4243
void rt_hw_interrupt_mask(int vector);
4344
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
44-
void handle_trap(rt_size_t xcause, rt_size_t xtval, rt_size_t xepc, struct rt_hw_stack_frame *sp);
45+
void handle_trap(rt_uintreg_t xcause, rt_uintreg_t xtval, rt_uintreg_t xepc, struct rt_hw_stack_frame *sp);
4546

4647
#endif

‎libcpu/risc-v/virt64/regtypes.h

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/*
2+
* Copyright (c) 2006-2024, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2024-07-15 WangShun The first version
9+
*/
10+
11+
#ifndef REGTYPES_H__
12+
#define REGTYPES_H__
13+
#include <rtconfig.h>
14+
#if defined(RT_USING_RV64ILP32)
15+
typedef unsigned long long rt_uintreg_t;
16+
#else
17+
typedef unsigned long rt_uintreg_t;
18+
#endif
19+
#endif /* REGTYPES_H__ */

‎libcpu/risc-v/virt64/riscv.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2021, RT-Thread Development Team
2+
* Copyright (c) 2006-2024, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -12,9 +12,15 @@
1212
#define __RISCV_H__
1313

1414
#include <encoding.h>
15+
#include <rtconfig.h>
1516

17+
#if defined(RT_USING_RV64ILP32)
18+
#define __SIZE(bit) (1ULL << (bit))
19+
#define __MASK(bit) (__SIZE(bit) - 1ULL)
20+
#else
1621
#define __SIZE(bit) (1UL << (bit))
1722
#define __MASK(bit) (__SIZE(bit) - 1UL)
23+
#endif /* RT_USING_RV64ILP32 */
1824
#define __UMASK(bit) (~(__MASK(bit)))
1925
#define __MASKVALUE(value,maskvalue) ((value) & (maskvalue))
2026
#define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue)))

0 commit comments

Comments
 (0)