1515#define PIN_GET (pin ) ((uint8_t)(((uint8_t)pin) & 0x07U))
1616#define PORT_GET (pin ) ((uint8_t)(((uint8_t)pin) >> 3U))
1717
18- #define __IFX_PORT_MAX 15u
18+ #if defined(SOC_XMC7200D_E272K8384AA )
19+ #define __IFX_PORT_MAX 35u
20+ #else
21+ #define __IFX_PORT_MAX 14u
22+ #endif
1923
2024#define PIN_IFXPORT_MAX __IFX_PORT_MAX
2125
2226static cyhal_gpio_callback_data_t irq_cb_data [PIN_IFXPORT_MAX ];
2327
24- static const struct pin_irq_map pin_irq_map [] =
28+ static struct pin_irq_map pin_irq_map [] =
2529{
2630 {CYHAL_PORT_0 , ioss_interrupts_gpio_0_IRQn },
2731#if !defined (SOC_CY8C6245LQI_S3D72 ) && !defined (SOC_CY8C6244LQI_S4D92 )
@@ -44,6 +48,27 @@ static const struct pin_irq_map pin_irq_map[] =
4448 {CYHAL_PORT_13 , ioss_interrupts_gpio_13_IRQn },
4549#endif
4650 {CYHAL_PORT_14 , ioss_interrupts_gpio_14_IRQn },
51+ #if defined(SOC_XMC7200D_E272K8384AA )
52+ {CYHAL_PORT_15 , ioss_interrupts_gpio_15_IRQn },
53+ {CYHAL_PORT_16 , ioss_interrupts_gpio_16_IRQn },
54+ {CYHAL_PORT_17 , ioss_interrupts_gpio_17_IRQn },
55+ {CYHAL_PORT_18 , ioss_interrupts_gpio_18_IRQn },
56+ {CYHAL_PORT_19 , ioss_interrupts_gpio_19_IRQn },
57+ {CYHAL_PORT_20 , ioss_interrupts_gpio_20_IRQn },
58+ {CYHAL_PORT_21 , ioss_interrupts_gpio_21_IRQn },
59+ {CYHAL_PORT_22 , ioss_interrupts_gpio_23_IRQn },
60+ {CYHAL_PORT_24 , ioss_interrupts_gpio_24_IRQn },
61+ {CYHAL_PORT_25 , ioss_interrupts_gpio_25_IRQn },
62+ {CYHAL_PORT_26 , ioss_interrupts_gpio_26_IRQn },
63+ {CYHAL_PORT_27 , ioss_interrupts_gpio_27_IRQn },
64+ {CYHAL_PORT_28 , ioss_interrupts_gpio_28_IRQn },
65+ {CYHAL_PORT_29 , ioss_interrupts_gpio_29_IRQn },
66+ {CYHAL_PORT_30 , ioss_interrupts_gpio_30_IRQn },
67+ {CYHAL_PORT_31 , ioss_interrupts_gpio_31_IRQn },
68+ {CYHAL_PORT_32 , ioss_interrupts_gpio_32_IRQn },
69+ {CYHAL_PORT_33 , ioss_interrupts_gpio_33_IRQn },
70+ {CYHAL_PORT_34 , ioss_interrupts_gpio_34_IRQn },
71+ #endif
4772};
4873
4974static struct rt_pin_irq_hdr pin_irq_handler_tab [] =
@@ -64,6 +89,27 @@ static struct rt_pin_irq_hdr pin_irq_handler_tab[] =
6489 {-1 , 0 , RT_NULL , RT_NULL },
6590 {-1 , 0 , RT_NULL , RT_NULL },
6691 {-1 , 0 , RT_NULL , RT_NULL },
92+ #if defined(SOC_XMC7200D_E272K8384AA )
93+ {-1 , 0 , RT_NULL , RT_NULL },
94+ {-1 , 0 , RT_NULL , RT_NULL },
95+ {-1 , 0 , RT_NULL , RT_NULL },
96+ {-1 , 0 , RT_NULL , RT_NULL },
97+ {-1 , 0 , RT_NULL , RT_NULL },
98+ {-1 , 0 , RT_NULL , RT_NULL },
99+ {-1 , 0 , RT_NULL , RT_NULL },
100+ {-1 , 0 , RT_NULL , RT_NULL },
101+ {-1 , 0 , RT_NULL , RT_NULL },
102+ {-1 , 0 , RT_NULL , RT_NULL },
103+ {-1 , 0 , RT_NULL , RT_NULL },
104+ {-1 , 0 , RT_NULL , RT_NULL },
105+ {-1 , 0 , RT_NULL , RT_NULL },
106+ {-1 , 0 , RT_NULL , RT_NULL },
107+ {-1 , 0 , RT_NULL , RT_NULL },
108+ {-1 , 0 , RT_NULL , RT_NULL },
109+ {-1 , 0 , RT_NULL , RT_NULL },
110+ {-1 , 0 , RT_NULL , RT_NULL },
111+ {-1 , 0 , RT_NULL , RT_NULL },
112+ #endif
67113};
68114
69115rt_inline void pin_irq_handler (int irqno )
@@ -275,12 +321,10 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
275321
276322#if !defined(COMPONENT_CAT1C )
277323 IRQn_Type irqn = (IRQn_Type )(irqmap -> irqno + PORT_GET (irqmap -> port ));
278- #endif
279324 irq_cb_data [irqn ].callback = irq_callback ;
280325 irq_cb_data [irqn ].callback_arg = (rt_uint16_t * )& pin_irq_map [gpio_port ].port ;
281-
282326 cyhal_gpio_register_callback (gpio_pin , & irq_cb_data [irqn ]);
283-
327+ #endif
284328 Cy_GPIO_ClearInterrupt (CYHAL_GET_PORTADDR (gpio_pin ), CYHAL_GET_PIN (gpio_pin ));
285329
286330 switch (pin_irq_handler_tab [gpio_port ].mode )
@@ -313,9 +357,8 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
313357
314358#if !defined(COMPONENT_CAT1C )
315359 IRQn_Type irqn = (IRQn_Type )(irqmap -> irqno + PORT_GET (irqmap -> port ));
316- #endif
317360 _cyhal_irq_disable (irqn );
318-
361+ #endif
319362 rt_hw_interrupt_enable (level );
320363 }
321364 else
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