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clk: meson: g12a: add mpll register init sequences
Add the required init of each MPLL of the g12a. Signed-off-by: Jerome Brunet <[email protected]>
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drivers/clk/meson/g12a.c

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Original file line numberDiff line numberDiff line change
@@ -1001,6 +1001,10 @@ static struct clk_fixed_factor g12a_mpll_prediv = {
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},
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};
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static const struct reg_sequence g12a_mpll0_init_regs[] = {
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{ .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },
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};
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static struct clk_regmap g12a_mpll0_div = {
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.data = &(struct meson_clk_mpll_data){
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.sdm = {
@@ -1024,6 +1028,8 @@ static struct clk_regmap g12a_mpll0_div = {
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.width = 1,
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},
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.lock = &meson_clk_lock,
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.init_regs = g12a_mpll0_init_regs,
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.init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
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},
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.hw.init = &(struct clk_init_data){
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.name = "mpll0_div",
@@ -1047,6 +1053,10 @@ static struct clk_regmap g12a_mpll0 = {
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},
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};
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static const struct reg_sequence g12a_mpll1_init_regs[] = {
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{ .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },
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};
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static struct clk_regmap g12a_mpll1_div = {
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.data = &(struct meson_clk_mpll_data){
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.sdm = {
@@ -1070,6 +1080,8 @@ static struct clk_regmap g12a_mpll1_div = {
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.width = 1,
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},
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.lock = &meson_clk_lock,
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.init_regs = g12a_mpll1_init_regs,
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.init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
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},
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.hw.init = &(struct clk_init_data){
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.name = "mpll1_div",
@@ -1093,6 +1105,10 @@ static struct clk_regmap g12a_mpll1 = {
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},
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};
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static const struct reg_sequence g12a_mpll2_init_regs[] = {
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{ .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
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};
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static struct clk_regmap g12a_mpll2_div = {
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.data = &(struct meson_clk_mpll_data){
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.sdm = {
@@ -1116,6 +1132,8 @@ static struct clk_regmap g12a_mpll2_div = {
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.width = 1,
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},
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.lock = &meson_clk_lock,
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.init_regs = g12a_mpll2_init_regs,
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.init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
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},
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.hw.init = &(struct clk_init_data){
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.name = "mpll2_div",
@@ -1139,6 +1157,10 @@ static struct clk_regmap g12a_mpll2 = {
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},
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};
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1160+
static const struct reg_sequence g12a_mpll3_init_regs[] = {
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{ .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
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};
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static struct clk_regmap g12a_mpll3_div = {
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.data = &(struct meson_clk_mpll_data){
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.sdm = {
@@ -1162,6 +1184,8 @@ static struct clk_regmap g12a_mpll3_div = {
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.width = 1,
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},
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.lock = &meson_clk_lock,
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.init_regs = g12a_mpll3_init_regs,
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.init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
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},
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.hw.init = &(struct clk_init_data){
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.name = "mpll3_div",

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