Skip to content

Commit 84db90c

Browse files
committed
cmd/compile: remove issueSpill
1 parent c81c027 commit 84db90c

File tree

1 file changed

+2
-4
lines changed

1 file changed

+2
-4
lines changed

src/cmd/compile/internal/ssa/regalloc.go

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1301,7 +1301,7 @@ func (s *regAllocState) regalloc(f *Func) {
13011301
}
13021302
b.Values = append(b.Values, v)
13031303
s.advanceUses(v)
1304-
goto issueSpill
1304+
continue
13051305
}
13061306
if v.Op == OpGetG && s.f.Config.hasGReg {
13071307
// use hardware g register
@@ -1311,7 +1311,7 @@ func (s *regAllocState) regalloc(f *Func) {
13111311
s.assignReg(s.GReg, v, v)
13121312
b.Values = append(b.Values, v)
13131313
s.advanceUses(v)
1314-
goto issueSpill
1314+
continue
13151315
}
13161316
if v.Op == OpArg {
13171317
// Args are "pre-spilled" values. We don't allocate
@@ -1669,8 +1669,6 @@ func (s *regAllocState) regalloc(f *Func) {
16691669
v.SetArg(i, a) // use register version of arguments
16701670
}
16711671
b.Values = append(b.Values, v)
1672-
1673-
issueSpill:
16741672
}
16751673

16761674
// Copy the control values - we need this so we can reduce the

0 commit comments

Comments
 (0)