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[wirelength_analyzer] Add support for DIFFINBUF (#52)
* Add support for DIFFINBUF cell types (used on differential inputs) Signed-off-by: Eddie Hung <[email protected]> * Update docs too Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]>
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docs/score.md

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@@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell.
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|`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6` | (all) <- (all) | Look Up Table |
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|`CARRY8` | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic |
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|`MUXF7`, `MUXF8`, `MUXF9` | (all) <- (all) | Intrasite Mux |
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|`IBUFCTRL`, `INBUF`, `OBUFT` | (all) <- (all) | I/O Buffer |
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|`IBUFCTRL`, `INBUF`, `OBUFT`, `DIFFINBUF` | (all) <- (all) | I/O Buffer |
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|`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,<br>`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic |
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|`DSP_MULTIPLIER`, `DSP_PREADD` | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic |
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|`PCIE40E4` | (none) <- (none) | PCIe Hard Macro |

wirelength_analyzer/xcvup_device_data.py

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@@ -81,6 +81,7 @@ def __contains__(self, item):
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'IBUFCTRL': self.all_to_all,
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'INBUF': self.all_to_all,
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'OBUFT': self.all_to_all,
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'DIFFINBUF': self.all_to_all,
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# The following cell types are BELs that make up a DSP macro.
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# Such DSPs contains a number of optional pipelining registers,

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