blunt fix

Author: Martien de Jong

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -8556,19 +8556,12 @@ LegalizerHelper::lowerMemset(MachineInstr &MI, Register Dst, Register Val,
                              bool IsVolatile) {
   auto &MF = *MI.getParent()->getParent();
   const auto &TLI = *MF.getSubtarget().getTargetLowering();
-  auto &DL = MF.getDataLayout();
-  LLVMContext &C = MF.getFunction().getContext();
 
   assert(KnownLen != 0 && "Have a zero length memset length!");
 
-  bool DstAlignCanChange = false;
-  MachineFrameInfo &MFI = MF.getFrameInfo();
+  const bool DstAlignCanChange = false;
   bool OptSize = shouldLowerMemFuncForSize(MF);
 
-  MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI);
-  if (FIDef && !MFI.isFixedObjectIndex(FIDef->getOperand(1).getIndex()))
-    DstAlignCanChange = true;
-
   unsigned Limit = TLI.getMaxStoresPerMemset(OptSize);
   std::vector<LLT> MemOps;
 
@@ -8587,19 +8580,6 @@ LegalizerHelper::lowerMemset(MachineInstr &MI, Register Dst, Register Val,
                                      MF.getFunction().getAttributes(), TLI))
     return UnableToLegalize;
 
-  if (DstAlignCanChange) {
-    // Get an estimate of the type from the LLT.
-    Type *IRTy = getTypeForLLT(MemOps[0], C);
-    Align NewAlign = DL.getABITypeAlign(IRTy);
-    if (NewAlign > Alignment) {
-      Alignment = NewAlign;
-      unsigned FI = FIDef->getOperand(1).getIndex();
-      // Give the stack frame object a larger alignment if needed.
-      if (MFI.getObjectAlign(FI) < Alignment)
-        MFI.setObjectAlignment(FI, Alignment);
-    }
-  }
-
   MachineIRBuilder MIB(MI);
   // Find the largest store and generate the bit pattern for it.
   LLT LargestTy = MemOps[0];

llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-memset.mir

@@ -17,23 +17,19 @@
   ; CHECK-LABEL: f:
   ; CHECK:         .p2align 4
   ; CHECK-NEXT:  // %bb.0: // %entry
-  ; CHECK-NEXT:    mova r0, #0; nopb ; nops ; paddxm [sp], #128; nopv
-  ; CHECK-NEXT:    vbcst.32 x0, r0
-  ; CHECK-NEXT:    mov p1, sp
-  ; CHECK-NEXT:    vextract.32 r0, x0, #0, vaddsign1
-  ; CHECK-NEXT:    mova m0, #-96; vextract.32 r1, x0, #1, vaddsign1
-  ; CHECK-NEXT:    padda [p1], m0; vextract.32 r2, x0, #2, vaddsign1
-  ; CHECK-NEXT:    mova m0, #4; st lr, [sp, #-128]; mov p0, p1 // 4-byte Folded Spill
-  ; CHECK-NEXT:    padda [p1], m0; st r0, [p1, #0]; vextract.32 r0, x0, #3, vaddsign1
-  ; CHECK-NEXT:    st r1, [p1], #4; vextract.32 r1, x0, #4, vaddsign1
-  ; CHECK-NEXT:    st r2, [p1], #4; vextract.32 r2, x0, #5, vaddsign1
+  ; CHECK-NEXT:    mova m0, #-60; nopb ; nops ; paddxm [sp], #64; nopv
+  ; CHECK-NEXT:    nopx ; mov p1, sp
+  ; CHECK-NEXT:    mova m0, #4; paddb [p1], m0; movx r0, #0; st lr, [sp, #-64] // 4-byte Folded Spill
+  ; CHECK-NEXT:    padda [p1], m0; st r0, [p1, #0]; mov p0, p1
+  ; CHECK-NEXT:    st r0, [p1], #4
+  ; CHECK-NEXT:    st r0, [p1], #4
   ; CHECK-NEXT:    st r0, [p1], #4; jl #g
-  ; CHECK-NEXT:    st r1, [p1], #4; vextract.32 r0, x0, #6, vaddsign1 // Delay Slot 5
-  ; CHECK-NEXT:    st r2, [p1], #4; vextract.32 r1, x0, #7, vaddsign1 // Delay Slot 4
+  ; CHECK-NEXT:    st r0, [p1], #4 // Delay Slot 5
+  ; CHECK-NEXT:    st r0, [p1], #4 // Delay Slot 4
   ; CHECK-NEXT:    st r0, [p1], #4 // Delay Slot 3
-  ; CHECK-NEXT:    st r1, [p1, #0] // Delay Slot 2
+  ; CHECK-NEXT:    st r0, [p1, #0] // Delay Slot 2
   ; CHECK-NEXT:    nop // Delay Slot 1
-  ; CHECK-NEXT:    lda lr, [sp, #-128]; nopb ; nops ; nopxm ; nopv // 4-byte Folded Reload
+  ; CHECK-NEXT:    lda lr, [sp, #-64]; nopb ; nops ; nopxm ; nopv // 4-byte Folded Reload
   ; CHECK-NEXT:    nopx
   ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    nop
@@ -44,7 +40,7 @@
   ; CHECK-NEXT:    nop // Delay Slot 5
   ; CHECK-NEXT:    nop // Delay Slot 4
   ; CHECK-NEXT:    nop // Delay Slot 3
-  ; CHECK-NEXT:    paddxm [sp], #-128 // Delay Slot 2
+  ; CHECK-NEXT:    paddxm [sp], #-64 // Delay Slot 2
   ; CHECK-NEXT:    nop // Delay Slot 1
   entry:
     %s = alloca %struct.S, align 4