Skip to content

Commit 94531e6

Browse files
LucasSteLucasSte
committed
[SOL] Add feature flag for disabling lddw (llvm#77)
* Fix incorrect obj-dump * Read flag from elf
1 parent de834a2 commit 94531e6

File tree

10 files changed

+57
-31
lines changed

10 files changed

+57
-31
lines changed

‎llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ class SBFDisassembler : public MCDisassembler {
6767
uint8_t getInstClass(uint64_t Inst) const { return (Inst >> 56) & 0x7; };
6868
uint8_t getInstSize(uint64_t Inst) const { return (Inst >> 59) & 0x3; };
6969
uint8_t getInstMode(uint64_t Inst) const { return (Inst >> 61) & 0x7; };
70+
bool isMov32(uint64_t Inst) const { return (Inst >> 56) == 0xb4; }
7071
};
7172

7273
} // end anonymous namespace
@@ -175,6 +176,10 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
175176
STI.getFeatureBits()[SBF::ALU32])
176177
Result = decodeInstruction(DecoderTableSBFALU3264, Instr, Insn, Address,
177178
this, STI);
179+
else if (isMov32(Insn) && !STI.getFeatureBits()[SBF::ALU32] &&
180+
STI.getFeatureBits()[SBF::FeatureDisableLddw])
181+
Result =
182+
decodeInstruction(DecoderTableSBFv264, Instr, Insn, Address, this, STI);
178183
else
179184
Result =
180185
decodeInstruction(DecoderTableSBF64, Instr, Insn, Address, this, STI);

‎llvm/lib/Target/SBF/SBF.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,9 @@ def FeatureDisableNeg : SubtargetFeature<"no-neg", "DisableNeg", "true",
4444
def FeatureReverseSubImm : SubtargetFeature<"reverse-sub", "ReverseSubImm", "true",
4545
"Reverse the operands in the 'sub reg, imm' instruction">;
4646

47+
def FeatureDisableLddw : SubtargetFeature<"no-lddw", "NoLddw", "true",
48+
"Disable the lddw instruction">;
49+
4750
class Proc<string Name, list<SubtargetFeature> Features>
4851
: Processor<Name, NoItineraries, Features>;
4952

@@ -53,7 +56,7 @@ def : Proc<"v2", []>;
5356
def : Proc<"v3", []>;
5457
def : Proc<"probe", []>;
5558
def : Proc<"sbfv2", [FeatureSolana, FeatureDynamicFrames, FeatureSdiv, FeatureRelocAbs64, FeatureStaticSyscalls,
56-
FeatureDisableNeg, FeatureReverseSubImm]>;
59+
FeatureDisableNeg, FeatureReverseSubImm, FeatureDisableLddw]>;
5760

5861
//===----------------------------------------------------------------------===//
5962
// Assembly printer

‎llvm/lib/Target/SBF/SBFInstrInfo.td

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,9 @@ def SBFIsBigEndian : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">;
5454
def SBFHasALU32 : Predicate<"Subtarget->getHasAlu32()">;
5555
def SBFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">;
5656
def SBFSubtargetSolana : Predicate<"Subtarget->isSolana()">;
57+
def SBFHasLddw : Predicate<"!Subtarget->getNoLddw()">;
58+
def SBFNoLddw : Predicate<"Subtarget->getNoLddw()">;
59+
5760
def SBFv2 : Predicate<"Subtarget->isSBFv2()">;
5861
def NoSBFv2 : Predicate<"!Subtarget->isSBFv2()">;
5962
def SBFHasNeg : Predicate<"!Subtarget->getDisableNeg()">;
@@ -322,13 +325,13 @@ let Constraints = "$dst = $src2" in {
322325
defm XOR : ALU<SBF_XOR, "xor", xor>;
323326
defm SRA : ALU<SBF_ARSH, "arsh", sra>;
324327

325-
let Predicates = [SBFv2] in {
328+
let Predicates = [SBFNoLddw] in {
326329
def HOR : ALU_RI<SBF_ALU64, SBF_HOR,
327330
(outs GPR:$dst),
328331
(ins GPR:$src2, i32imm:$imm),
329332
"hor64 $dst, $imm",
330333
[]>;
331-
let DecoderNamespace = "AddrLoad" in {
334+
let DecoderNamespace = "SBFv2" in {
332335
def HOR_addr : ALU_RI<SBF_ALU64, SBF_HOR,
333336
(outs GPR:$dst),
334337
(ins GPR:$src2, u64imm:$imm),
@@ -405,7 +408,7 @@ class LD_IMM64<bits<4> Pseudo, string Mnemonic>
405408
}
406409

407410
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
408-
def LD_imm64 : LD_IMM64<0, "lddw">, Requires<[NoSBFv2]>;
411+
def LD_imm64 : LD_IMM64<0, "lddw">, Requires<[SBFHasLddw]>;
409412
def MOV_rr : ALU_RR<SBF_ALU64, SBF_MOV,
410413
(outs GPR:$dst),
411414
(ins GPR:$src),
@@ -934,14 +937,15 @@ let isCodeGenOnly = 1 in {
934937
def MOV_32_64 : ALU_RR<SBF_ALU, SBF_MOV,
935938
(outs GPR:$dst), (ins GPR32:$src),
936939
"mov32 $dst, $src", []>;
937-
let Predicates = [SBFv2] in {
938-
def MOV_32_64_imm : ALU_RI<SBF_ALU, SBF_MOV,
940+
def MOV_32_64_addr : ALU_RI<SBF_ALU, SBF_MOV,
941+
(outs GPR:$dst), (ins u64imm:$imm),
942+
"mov32 $dst, $imm", []>, Requires<[SBFNoLddw]>;
943+
}
944+
945+
let DecoderNamespace = "SBFv2", Predicates = [SBFNoLddw] in {
946+
def MOV_32_64_imm : ALU_RI<SBF_ALU, SBF_MOV,
939947
(outs GPR:$dst), (ins i32imm:$imm),
940948
"mov32 $dst, $imm", []>;
941-
def MOV_32_64_addr : ALU_RI<SBF_ALU, SBF_MOV,
942-
(outs GPR:$dst), (ins u64imm:$imm),
943-
"mov32 $dst, $imm", []>;
944-
}
945949
}
946950

947951
// In SBFv2, a CopyToReg of a 64-bit value is split in two instructions:
@@ -950,14 +954,14 @@ let isCodeGenOnly = 1 in {
950954
// These instructions copy the value 0x1122334455667788 to a register.
951955
def : Pat<(i64 imm:$imm),
952956
(HOR (MOV_32_64_imm (i32 (Lower32 $imm))),
953-
(i32 (Upper32 $imm)))>, Requires<[SBFv2]>;
957+
(i32 (Upper32 $imm)))>, Requires<[SBFNoLddw]>;
954958

955959
// load 64-bit global address into register.
956960
def : Pat<(SBFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>,
957-
Requires<[NoSBFv2]>;
961+
Requires<[SBFHasLddw]>;
958962
def : Pat<(SBFWrapper tglobaladdr:$in),
959963
(HOR_addr (MOV_32_64_addr tglobaladdr:$in),
960-
tglobaladdr:$in)>, Requires<[SBFv2]>;
964+
tglobaladdr:$in)>, Requires<[SBFNoLddw]>;
961965

962966

963967
def : Pat<(i64 (sext GPR32:$src)),

‎llvm/lib/Target/SBF/SBFSubtarget.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,9 @@ class SBFSubtarget : public SBFGenSubtargetInfo {
8282
// reg - imm'.
8383
bool ReverseSubImm;
8484

85+
// wether we should use the LDDW instruction
86+
bool NoLddw;
87+
8588
public:
8689
// This constructor initializes the data members to match that
8790
// of the specified triple.
@@ -104,6 +107,7 @@ class SBFSubtarget : public SBFGenSubtargetInfo {
104107
bool isSBFv2() const { return IsSBFv2; }
105108
bool getDisableNeg() const { return DisableNeg; }
106109
bool getReverseSubImm() const { return ReverseSubImm; }
110+
bool getNoLddw() const { return NoLddw; }
107111

108112
const SBFInstrInfo *getInstrInfo() const override { return &InstrInfo; }
109113
const SBFFrameLowering *getFrameLowering() const override {

‎llvm/test/CodeGen/SBF/objdump_cond_op.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
3434
%10 = load i32, i32* @gbl, align 4
3535
br i1 %9, label %15, label %11
3636

37-
; CHECK: mov32 w1, 0x0
37+
; CHECK: mov32 r1, 0x0
3838
; CHECK: hor64 r1, 0x0
3939
; CHECK: ldxw r0, [r1 + 0x0]
4040
; CHECK: mul64 r0, r0
@@ -46,7 +46,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
4646
br label %13
4747

4848
; CHECK-LABEL: <LBB0_2>:
49-
; CHECK: mov32 w3, 0x0
49+
; CHECK: mov32 r3, 0x0
5050
; CHECK: hor64 r3, 0x0
5151
; CHECK: ldxw r0, [r3 + 0x0]
5252
; CHECK: lsh64 r2, 0x20
@@ -59,7 +59,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
5959
store i32 %14, i32* @gbl, align 4
6060
br label %15
6161
; CHECK-LABEL: <LBB0_4>:
62-
; CHECK: mov32 w1, 0x0
62+
; CHECK: mov32 r1, 0x0
6363
; CHECK: hor64 r1, 0x0
6464
; CHECK: stxw [r1 + 0x0], r0
6565

‎llvm/test/CodeGen/SBF/objdump_imm_hex.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -26,17 +26,17 @@ define i32 @test(i64, i64) local_unnamed_addr #0 {
2626
; CHECK-LABEL: test
2727
%3 = icmp eq i64 %0, -6067004223159161907
2828
br i1 %3, label %4, label %8
29-
; CHECK-DEC: b4 03 00 00 cd ab cd ab mov32 w3, -0x54325433
29+
; CHECK-DEC: b4 03 00 00 cd ab cd ab mov32 r3, -0x54325433
3030
; CHECK-DEC: f7 03 00 00 cd ab cd ab hor64 r3, -0x54325433
3131
; CHECK-DEC: 5d 31 07 00 00 00 00 00 jne r1, r3, +0x7
32-
; CHECK-HEX: b4 03 00 00 cd ab cd ab mov32 w3, -0x54325433
32+
; CHECK-HEX: b4 03 00 00 cd ab cd ab mov32 r3, -0x54325433
3333
; CHECK-HEX: f7 03 00 00 cd ab cd ab hor64 r3, -0x54325433
3434
; CHECK-HEX: 5d 31 07 00 00 00 00 00 jne r1, r3, +0x7
3535

3636
; <label>:4: ; preds = %2
37-
; CHECK-DEC: b4 01 00 00 00 00 00 00 mov32 w1, 0x0
37+
; CHECK-DEC: b4 01 00 00 00 00 00 00 mov32 r1, 0x0
3838
; CHECK-DEC: f7 01 00 00 00 00 00 00 hor64 r1, 0x0
39-
; CHECK-HEX: b4 01 00 00 00 00 00 00 mov32 w1, 0x0
39+
; CHECK-HEX: b4 01 00 00 00 00 00 00 mov32 r1, 0x0
4040
; CHECK-HEX: f7 01 00 00 00 00 00 00 hor64 r1, 0x0
4141
; CHECK-REL: fixup A - offset: 0, value: gbl, kind: FK_SecRel_8
4242
%5 = load i32, i32* @gbl, align 4
@@ -48,16 +48,16 @@ define i32 @test(i64, i64) local_unnamed_addr #0 {
4848

4949
; <label>:8: ; preds = %2
5050
%9 = icmp eq i64 %1, 188899839028173
51-
; CHECK-DEC: b4 01 00 00 cd ab cd ab mov32 w1, -0x54325433
51+
; CHECK-DEC: b4 01 00 00 cd ab cd ab mov32 r1, -0x54325433
5252
; CHECK-DEC: f7 01 00 00 cd ab 00 00 hor64 r1, 0xabcd
53-
; CHECK-HEX: b4 01 00 00 cd ab cd ab mov32 w1, -0x54325433
53+
; CHECK-HEX: b4 01 00 00 cd ab cd ab mov32 r1, -0x54325433
5454
; CHECK-HEX: f7 01 00 00 cd ab 00 00 hor64 r1, 0xabcd
5555
br i1 %9, label %10, label %16
5656

5757
; <label>:10: ; preds = %8
58-
; CHECK-DEC: b4 01 00 00 00 00 00 00 mov32 w1, 0x0
58+
; CHECK-DEC: b4 01 00 00 00 00 00 00 mov32 r1, 0x0
5959
; CHECK-DEC: f7 01 00 00 00 00 00 00 hor64 r1, 0x0
60-
; CHECK-HEX: b4 01 00 00 00 00 00 00 mov32 w1, 0x0
60+
; CHECK-HEX: b4 01 00 00 00 00 00 00 mov32 r1, 0x0
6161
; CHECK-HEX: f7 01 00 00 00 00 00 00 hor64 r1, 0x0
6262
; CHECK-REL: fixup A - offset: 0, value: gbl, kind: FK_SecRel_8
6363
%11 = load i32, i32* @gbl, align 4

‎llvm/test/CodeGen/SBF/objdump_static_var.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,12 @@
1010
; Function Attrs: norecurse nounwind
1111
define dso_local i32 @test() local_unnamed_addr #0 {
1212
%1 = load volatile i64, i64* @a, align 8, !tbaa !2
13-
; CHECK: mov32 w1, 0x0
13+
; CHECK: mov32 r1, 0x0
1414
; CHECK: R_SBF_64_64 a
1515
; CHECK: hor64 r1, 0x0
1616
; CHECK: ldxdw r1, [r1 + 0x0]
1717
%2 = load volatile i32, i32* @b, align 4, !tbaa !6
18-
; CHECK: mov32 w2, 0x0
18+
; CHECK: mov32 r2, 0x0
1919
; CHECK: R_SBF_64_64 b
2020
; CHECK: hor64 r2, 0x0
2121
; CHECK: ldxw r0, [r2 + 0x0]

‎llvm/test/MC/SBF/insn-unit-32.s

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# RUN: llvm-mc -triple sbf --mcpu=sbfv2 -filetype=obj -o %t %s
2-
# RUN: llvm-objdump -d -r %t | FileCheck %s
3-
# RUN: llvm-objdump --mattr=+alu32 -d -r %t | FileCheck %s
2+
# RUN: llvm-objdump -d -r %t | FileCheck %s --check-prefixes=CHECK,CHECK-alu64
3+
# RUN: llvm-objdump --mattr=+alu32 -d -r %t | FileCheck %s --check-prefixes=CHECK,CHECK-alu32
44

55
// ======== BPF_ALU Class ========
66
neg32 w1 // BPF_NEG
@@ -51,8 +51,10 @@
5151
// CHECK: 64 06 00 00 3f 00 00 00 lsh32 w6, 0x3f
5252
// CHECK: 74 07 00 00 20 00 00 00 rsh32 w7, 0x20
5353
// CHECK: a4 08 00 00 00 00 00 00 xor32 w8, 0x0
54-
// CHECK: b4 09 00 00 01 00 00 00 mov32 w9, 0x1
55-
// CHECK: b4 09 00 00 ff ff ff ff mov32 w9, -0x1
54+
// CHECK-alu64: b4 09 00 00 01 00 00 00 mov32 r9, 0x1
55+
// CHECK-alu64: b4 09 00 00 ff ff ff ff mov32 r9, -0x1
56+
// CHECK-alu32: b4 09 00 00 01 00 00 00 mov32 w9, 0x1
57+
// CHECK-alu32: b4 09 00 00 ff ff ff ff mov32 w9, -0x1
5658
// CHECK: c4 0a 00 00 40 00 00 00 arsh32 w10, 0x40
5759

5860
jeq w0, w1, Llabel0 // BPF_JEQ | BPF_X

‎llvm/test/MC/SBF/sbf-alu.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# RUN: llvm-mc %s -triple=sbf-solana-solana --mcpu=sbfv2 --show-encoding \
22
# RUN: | FileCheck %s --check-prefix=CHECK-ASM-NEW
33
# RUN: llvm-mc %s -triple=sbf-solana-solana --mcpu=sbfv2 -filetype=obj \
4-
# RUN: | llvm-objdump -d -r - \
4+
# RUN: | llvm-objdump -d -r --mattr=+alu32 - \
55
# RUN: | FileCheck --check-prefix=CHECK-OBJ-NEW %s
66

77

‎llvm/tools/llvm-objdump/llvm-objdump.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2447,6 +2447,14 @@ static void disassembleObject(ObjectFile *Obj, bool InlineRelocs) {
24472447
}
24482448

24492449
DisassemblerTarget PrimaryTarget(TheTarget, *Obj, TripleName, MCPU, Features);
2450+
// The SBF target specifies the cpu type as an ELF flag, which is not parsed automatically in LLVM objdump.
2451+
// We must set the CPU type here so that the disassembler can decode the SBFv2 features correctly.
2452+
if (MCPU.empty() && Obj->isELF() && Obj->getArch() == Triple::sbf) {
2453+
const auto *Elf64 = dyn_cast<ELF64LEObjectFile>(Obj);
2454+
if (Elf64->getPlatformFlags() & ELF::EF_SBF_V2) {
2455+
MCPU = "sbfv2";
2456+
}
2457+
}
24502458

24512459
// If we have an ARM object file, we need a second disassembler, because
24522460
// ARM CPUs have two different instruction sets: ARM mode, and Thumb mode.

0 commit comments

Comments
 (0)