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[SOL] Enable mod instruction (llvm#87)
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8 files changed

+81
-11
lines changed

8 files changed

+81
-11
lines changed

‎llvm/lib/Target/SBF/SBFISelLowering.cpp

-1
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,6 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,
123123
if (Subtarget->isSolana() && !STI.getHasPqrClass()) {
124124
setOperationAction(ISD::SDIV, VT, Expand);
125125
setOperationAction(ISD::SREM, VT, Expand);
126-
setOperationAction(ISD::UREM, VT, Expand);
127126
setOperationAction(ISD::MULHU, VT, Expand);
128127
setOperationAction(ISD::MULHS, VT, Expand);
129128
}

‎llvm/lib/Target/SBF/SBFInstrFormats.td

+1
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ def SBF_AND : SBFArithOp<0x5>;
3939
def SBF_LSH : SBFArithOp<0x6>;
4040
def SBF_RSH : SBFArithOp<0x7>;
4141
def SBF_NEG : SBFArithOp<0x8>;
42+
def SBF_MOD : SBFArithOp<0x9>;
4243
def SBF_XOR : SBFArithOp<0xa>;
4344
def SBF_MOV : SBFArithOp<0xb>;
4445
def SBF_ARSH : SBFArithOp<0xc>;

‎llvm/lib/Target/SBF/SBFInstrInfo.td

+1
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,7 @@ let Constraints = "$dst = $src2" in {
324324
let Predicates = [SBFNoPqrInstr] in {
325325
defm MUL : ALU<SBF_MUL, "mul", mul>;
326326
defm DIV : ALU<SBF_DIV, "div", udiv>;
327+
defm MOD : ALU<SBF_MOD, "mod", urem>;
327328
}
328329

329330
let Predicates = [SBFPqrInstr] in {

‎llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll

+26
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,16 @@
5151
; return a / 0xf;
5252
; }
5353
;
54+
; unsigned rem(unsigned a, unsigned b)
55+
; {
56+
; return a % b;
57+
; }
58+
;
59+
; unsigned rem_i(unsigned a)
60+
; {
61+
; return a % 0xf;
62+
; }
63+
;
5464
; int or(int a, int b)
5565
; {
5666
; return a | b;
@@ -194,6 +204,22 @@ entry:
194204
ret i32 %div
195205
}
196206

207+
; Function Attrs: norecurse nounwind readnone
208+
define dso_local i32 @rem(i32 %a, i32 %b) local_unnamed_addr #0 {
209+
entry:
210+
%rem = urem i32 %a, %b
211+
; CHECK: mod32 w{{[0-9]+}}, w{{[0-9]+}}
212+
ret i32 %rem
213+
}
214+
215+
; Function Attrs: norecurse nounwind readnone
216+
define dso_local i32 @rem_i(i32 %a) local_unnamed_addr #0 {
217+
entry:
218+
%rem = urem i32 %a, 15
219+
; CHECK: mod32 w{{[0-9]+}}, 15
220+
ret i32 %rem
221+
}
222+
197223
; Function Attrs: norecurse nounwind readnone
198224
define dso_local i32 @or(i32 %a, i32 %b) local_unnamed_addr #0 {
199225
entry:

‎llvm/test/CodeGen/SBF/mod-64.ll

+17
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
; RUN: llc -O2 -march=sbf < %s | FileCheck %s
2+
3+
; Function Attrs: norecurse nounwind readnone
4+
define dso_local i64 @rem(i64 %a, i64 %b) local_unnamed_addr #0 {
5+
entry:
6+
%rem = urem i64 %a, %b
7+
; CHECK: mod64 r{{[0-9]+}}, r{{[0-9]+}}
8+
ret i64 %rem
9+
}
10+
11+
; Function Attrs: norecurse nounwind readnone
12+
define dso_local i64 @rem_i(i64 %a) local_unnamed_addr #0 {
13+
entry:
14+
%rem = urem i64 %a, 15
15+
; CHECK: mod64 r{{[0-9]+}}, 15
16+
ret i64 %rem
17+
}

‎llvm/test/CodeGen/SBF/pqr-class.ll

+5-10
Original file line numberDiff line numberDiff line change
@@ -16,15 +16,13 @@ entry:
1616
; CHECK-v2: lmul64 r{{[0-9]+}}, r2
1717
; CHECK-V2: lmul64 r{{[0-9]+}}, 7
1818

19+
; CHECK-v1: mod64 r{{[0-9]+}}, r{{[0-9]+}}
1920
; CHECK-v1: div64 r{{[0-9]+}}, r{{[0-9]+}}
20-
; CHECK-v1: mul64 r{{[0-9]+}}, r{{[0-9]+}}
21-
; CHECK-v1: sub64 r{{[0-9]+}}, r{{[0-9]+}}
2221
; CHECK-v1: add64 r{{[0-9]+}}, r{{[0-9]+}}
23-
; CHECK-v1: div64 r{{[0-9]+}}, 17
24-
; CHECK-v1: mul64 r{{[0-9]+}}, 17
2522
; CHECK-v1: mov64 r{{[0-9]+}}, r{{[0-9]+}}
26-
; CHECK-v1: sub64 r{{[0-9]+}}, r{{[0-9]+}}
23+
; CHECK-v1: mod64 r{{[0-9]+}}, 17
2724
; CHECK-v1: div64 r{{[0-9]+}}, 7
25+
; CHECK-v1: add64 r{{[0-9]+}}, r{{[0-9]+}}
2826
; CHECK-v1: mul64 r{{[0-9]+}}, r{{[0-9]+}}
2927
; CHECK-v1: mul64 r{{[0-9]+}}, 7
3028

@@ -79,14 +77,11 @@ entry:
7977
; CHECK-v2: lmul32 w{{[0-9]+}}, w{{[0-9]+}}
8078
; CHECK-v2: lmul32 w{{[0-9]+}}, 7
8179

80+
; CHECK-v1: mod32 w{{[0-9]+}}, w{{[0-9]+}}
8281
; CHECK-v1: div32 w{{[0-9]+}}, w{{[0-9]+}}
83-
; CHECK-v1: mul32 w{{[0-9]+}}, w{{[0-9]+}}
84-
; CHECK-v1: sub32 w{{[0-9]+}}, w{{[0-9]+}}
8582
; CHECK-v1: add32 w{{[0-9]+}}, w{{[0-9]+}}
86-
; CHECK-v1: div32 w{{[0-9]+}}, 17
87-
; CHECK-v1: mul32 w{{[0-9]+}}, 17
8883
; CHECK-v1: mov32 w{{[0-9]+}}, w{{[0-9]+}}
89-
; CHECK-v1: sub32 w{{[0-9]+}}, w{{[0-9]+}}
84+
; CHECK-v1: mod32 w{{[0-9]+}}, 17
9085
; CHECK-v1: div32 w{{[0-9]+}}, 7
9186
; CHECK-v1: add32 w{{[0-9]+}}, w{{[0-9]+}}
9287
; CHECK-v1: mul32 w{{[0-9]+}}, w{{[0-9]+}}

‎llvm/test/MC/Disassembler/SBF/sbf-alu.txt

+14
Original file line numberDiff line numberDiff line change
@@ -241,3 +241,17 @@
241241
0xdc,0x00,0x00,0x00,0x10,0x00,0x00,0x00
242242
0xdc,0x01,0x00,0x00,0x20,0x00,0x00,0x00
243243
0xdc,0x02,0x00,0x00,0x40,0x00,0x00,0x00
244+
245+
246+
# CHECK-NEW: mod64 r3, r1
247+
0x9f,0x13,0x00,0x00,0x00,0x00,0x00,0x00
248+
249+
# CHECK-NEW: mod64 r3, 123
250+
0x97,0x03,0x00,0x00,0x7b,0x00,0x00,0x00
251+
252+
# CHECK-NEW: mod32 w6, w2
253+
0x9c,0x26,0x00,0x00,0x00,0x00,0x00,0x00
254+
255+
# CHECK-NEW: mod32 w5, -12
256+
0x94,0x05,0x00,0x00,0x85,0xff,0xff,0xff
257+

‎llvm/test/MC/SBF/sbf-alu.s

+17
Original file line numberDiff line numberDiff line change
@@ -318,3 +318,20 @@ mov32 w5, -123
318318
be16 r0
319319
be32 r1
320320
be64 r2
321+
322+
323+
# CHECK-OBJ-NEW: mod64 r3, r1
324+
# CHECK-ASM-NEW: encoding: [0x9f,0x13,0x00,0x00,0x00,0x00,0x00,0x00]
325+
mod64 r3, r1
326+
327+
# CHECK-OBJ-NEW: mod64 r3, 0x7b
328+
# CHECK-ASM-NEW: encoding: [0x97,0x03,0x00,0x00,0x7b,0x00,0x00,0x00]
329+
mod64 r3, 123
330+
331+
# CHECK-OBJ-NEW: mod32 w6, w2
332+
# CHECK-ASM-NEW: encoding: [0x9c,0x26,0x00,0x00,0x00,0x00,0x00,0x00]
333+
mod32 w6, w2
334+
335+
# CHECK-OBJ-NEW: mod32 w5, -0x7b
336+
# CHECK-ASM-NEW: encoding: [0x94,0x05,0x00,0x00,0x85,0xff,0xff,0xff]
337+
mod32 w5, -123

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