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alexforencichalexforencich
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Add support for file list files
Signed-off-by: Alex Forencich <[email protected]>
1 parent c1c3dc0 commit 664ab9f

24 files changed

+207
-48
lines changed

‎rtl/axis_arb_mux.f

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
axis_arb_mux.v
2+
arbiter.v
3+
priority_encoder.v

‎rtl/axis_async_fifo_adapter.f

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
axis_async_fifo_adapter.v
2+
axis_async_fifo.v
3+
axis_adapter.v

‎rtl/axis_cobs_encode.f

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
axis_cobs_encode.v
2+
axis_fifo.v

‎rtl/axis_fifo_adapter.f

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
axis_fifo_adapter.v
2+
axis_fifo.v
3+
axis_adapter.v

‎rtl/axis_frame_length_adjust_fifo.f

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
axis_frame_length_adjust_fifo.v
2+
axis_frame_length_adjust.v
3+
axis_fifo.v

‎rtl/axis_pipeline_register.f

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
axis_pipeline_register.v
2+
axis_register.v

‎rtl/axis_ram_switch.f

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
axis_ram_switch.v
2+
axis_adapter.v
3+
arbiter.v
4+
priority_encoder.v

‎rtl/axis_switch.f

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
axis_switch.v
2+
axis_register.v
3+
arbiter.v
4+
priority_encoder.v

‎tb/axis_arb_mux/Makefile

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,9 +33,13 @@ WRAPPER = $(DUT)_wrap_$(PORTS)
3333
TOPLEVEL = $(WRAPPER)
3434
MODULE = test_$(DUT)
3535
VERILOG_SOURCES += $(WRAPPER).v
36-
VERILOG_SOURCES += ../../rtl/$(DUT).v
37-
VERILOG_SOURCES += ../../rtl/arbiter.v
38-
VERILOG_SOURCES += ../../rtl/priority_encoder.v
36+
VERILOG_SOURCES += ../../rtl/$(DUT).f
37+
38+
# handle file list files
39+
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
40+
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
41+
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
42+
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
3943

4044
# module parameters
4145
export PARAM_DATA_WIDTH := 8

‎tb/axis_arb_mux/test_axis_arb_mux.py

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -316,6 +316,19 @@ def incrementing_payload(length):
316316
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
317317

318318

319+
def process_f_files(files):
320+
lst = {}
321+
for f in files:
322+
if f[-2:].lower() == '.f':
323+
with open(f, 'r') as fp:
324+
l = fp.read().split()
325+
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
326+
lst[os.path.basename(f)] = f
327+
else:
328+
lst[os.path.basename(f)] = f
329+
return list(lst.values())
330+
331+
319332
@pytest.mark.parametrize("round_robin", [0, 1])
320333
@pytest.mark.parametrize("data_width", [8, 16, 32])
321334
@pytest.mark.parametrize("ports", [1, 4])
@@ -335,11 +348,11 @@ def test_axis_arb_mux(request, ports, data_width, round_robin):
335348

336349
verilog_sources = [
337350
wrapper_file,
338-
os.path.join(rtl_dir, f"{dut}.v"),
339-
os.path.join(rtl_dir, "arbiter.v"),
340-
os.path.join(rtl_dir, "priority_encoder.v"),
351+
os.path.join(rtl_dir, f"{dut}.f"),
341352
]
342353

354+
verilog_sources = process_f_files(verilog_sources)
355+
343356
parameters = {}
344357

345358
parameters['DATA_WIDTH'] = data_width

‎tb/axis_async_fifo_adapter/Makefile

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
2929
DUT = axis_async_fifo_adapter
3030
TOPLEVEL = $(DUT)
3131
MODULE = test_$(DUT)
32-
VERILOG_SOURCES += ../../rtl/$(DUT).v
33-
VERILOG_SOURCES += ../../rtl/axis_async_fifo.v
34-
VERILOG_SOURCES += ../../rtl/axis_adapter.v
32+
VERILOG_SOURCES += ../../rtl/$(DUT).f
33+
34+
# handle file list files
35+
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
36+
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
37+
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
38+
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
3539

3640
# module parameters
3741
export PARAM_S_DATA_WIDTH := 8

‎tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -662,6 +662,19 @@ def incrementing_payload(length):
662662
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
663663

664664

665+
def process_f_files(files):
666+
lst = {}
667+
for f in files:
668+
if f[-2:].lower() == '.f':
669+
with open(f, 'r') as fp:
670+
l = fp.read().split()
671+
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
672+
lst[os.path.basename(f)] = f
673+
else:
674+
lst[os.path.basename(f)] = f
675+
return list(lst.values())
676+
677+
665678
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
666679
"drop_when_full", "mark_when_full"),
667680
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
@@ -676,11 +689,11 @@ def test_axis_async_fifo_adapter(request, s_data_width, m_data_width,
676689
toplevel = dut
677690

678691
verilog_sources = [
679-
os.path.join(rtl_dir, f"{dut}.v"),
680-
os.path.join(rtl_dir, "axis_async_fifo.v"),
681-
os.path.join(rtl_dir, "axis_adapter.v"),
692+
os.path.join(rtl_dir, f"{dut}.f"),
682693
]
683694

695+
verilog_sources = process_f_files(verilog_sources)
696+
684697
parameters = {}
685698

686699
parameters['S_DATA_WIDTH'] = s_data_width

‎tb/axis_cobs_encode/Makefile

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
2929
DUT = axis_cobs_encode
3030
TOPLEVEL = $(DUT)
3131
MODULE = test_$(DUT)
32-
VERILOG_SOURCES += ../../rtl/$(DUT).v
33-
VERILOG_SOURCES += ../../rtl/axis_fifo.v
32+
VERILOG_SOURCES += ../../rtl/$(DUT).f
33+
34+
# handle file list files
35+
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
36+
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
37+
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
38+
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
3439

3540
# module parameters
3641
export PARAM_APPEND_ZERO := 0

‎tb/axis_cobs_encode/test_axis_cobs_encode.py

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -217,17 +217,31 @@ def prbs_payload(length):
217217
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
218218

219219

220+
def process_f_files(files):
221+
lst = {}
222+
for f in files:
223+
if f[-2:].lower() == '.f':
224+
with open(f, 'r') as fp:
225+
l = fp.read().split()
226+
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
227+
lst[os.path.basename(f)] = f
228+
else:
229+
lst[os.path.basename(f)] = f
230+
return list(lst.values())
231+
232+
220233
@pytest.mark.parametrize("append_zero", [0, 1])
221234
def test_axis_cobs_encode(request, append_zero):
222235
dut = "axis_cobs_encode"
223236
module = os.path.splitext(os.path.basename(__file__))[0]
224237
toplevel = dut
225238

226239
verilog_sources = [
227-
os.path.join(rtl_dir, f"{dut}.v"),
228-
os.path.join(rtl_dir, "axis_fifo.v"),
240+
os.path.join(rtl_dir, f"{dut}.f"),
229241
]
230242

243+
verilog_sources = process_f_files(verilog_sources)
244+
231245
parameters = {}
232246

233247
parameters['APPEND_ZERO'] = append_zero

‎tb/axis_fifo_adapter/Makefile

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
2929
DUT = axis_fifo_adapter
3030
TOPLEVEL = $(DUT)
3131
MODULE = test_$(DUT)
32-
VERILOG_SOURCES += ../../rtl/$(DUT).v
33-
VERILOG_SOURCES += ../../rtl/axis_fifo.v
34-
VERILOG_SOURCES += ../../rtl/axis_adapter.v
32+
VERILOG_SOURCES += ../../rtl/$(DUT).f
33+
34+
# handle file list files
35+
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
36+
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
37+
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
38+
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
3539

3640
# module parameters
3741
export PARAM_S_DATA_WIDTH := 8

‎tb/axis_fifo_adapter/test_axis_fifo_adapter.py

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -445,6 +445,19 @@ def incrementing_payload(length):
445445
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
446446

447447

448+
def process_f_files(files):
449+
lst = {}
450+
for f in files:
451+
if f[-2:].lower() == '.f':
452+
with open(f, 'r') as fp:
453+
l = fp.read().split()
454+
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
455+
lst[os.path.basename(f)] = f
456+
else:
457+
lst[os.path.basename(f)] = f
458+
return list(lst.values())
459+
460+
448461
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
449462
"drop_when_full", "mark_when_full"),
450463
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
@@ -459,11 +472,11 @@ def test_axis_fifo_adapter(request, s_data_width, m_data_width,
459472
toplevel = dut
460473

461474
verilog_sources = [
462-
os.path.join(rtl_dir, f"{dut}.v"),
463-
os.path.join(rtl_dir, "axis_fifo.v"),
464-
os.path.join(rtl_dir, "axis_adapter.v"),
475+
os.path.join(rtl_dir, f"{dut}.f"),
465476
]
466477

478+
verilog_sources = process_f_files(verilog_sources)
479+
467480
parameters = {}
468481

469482
parameters['S_DATA_WIDTH'] = s_data_width

‎tb/axis_frame_length_adjust_fifo/Makefile

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
2929
DUT = axis_frame_length_adjust_fifo
3030
TOPLEVEL = $(DUT)
3131
MODULE = test_$(DUT)
32-
VERILOG_SOURCES += ../../rtl/$(DUT).v
33-
VERILOG_SOURCES += ../../rtl/axis_frame_length_adjust.v
34-
VERILOG_SOURCES += ../../rtl/axis_fifo.v
32+
VERILOG_SOURCES += ../../rtl/$(DUT).f
33+
34+
# handle file list files
35+
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
36+
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
37+
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
38+
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
3539

3640
# module parameters
3741
export PARAM_DATA_WIDTH := 8

‎tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -290,18 +290,31 @@ def incrementing_payload(length):
290290
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
291291

292292

293+
def process_f_files(files):
294+
lst = {}
295+
for f in files:
296+
if f[-2:].lower() == '.f':
297+
with open(f, 'r') as fp:
298+
l = fp.read().split()
299+
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
300+
lst[os.path.basename(f)] = f
301+
else:
302+
lst[os.path.basename(f)] = f
303+
return list(lst.values())
304+
305+
293306
@pytest.mark.parametrize("data_width", [8, 16, 32])
294307
def test_axis_frame_length_adjust_fifo(request, data_width):
295308
dut = "axis_frame_length_adjust_fifo"
296309
module = os.path.splitext(os.path.basename(__file__))[0]
297310
toplevel = dut
298311

299312
verilog_sources = [
300-
os.path.join(rtl_dir, f"{dut}.v"),
301-
os.path.join(rtl_dir, f"axis_frame_length_adjust.v"),
302-
os.path.join(rtl_dir, f"axis_fifo.v"),
313+
os.path.join(rtl_dir, f"{dut}.f"),
303314
]
304315

316+
verilog_sources = process_f_files(verilog_sources)
317+
305318
parameters = {}
306319

307320
parameters['DATA_WIDTH'] = data_width

‎tb/axis_pipeline_register/Makefile

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,13 @@ COCOTB_HDL_TIMEPRECISION = 1ps
2929
DUT = axis_pipeline_register
3030
TOPLEVEL = $(DUT)
3131
MODULE = test_$(DUT)
32-
VERILOG_SOURCES += ../../rtl/$(DUT).v
33-
VERILOG_SOURCES += ../../rtl/axis_register.v
32+
VERILOG_SOURCES += ../../rtl/$(DUT).f
33+
34+
# handle file list files
35+
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
36+
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
37+
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
38+
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
3439

3540
# module parameters
3641
export PARAM_DATA_WIDTH := 8

‎tb/axis_pipeline_register/test_axis_pipeline_register.py

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,19 @@ def incrementing_payload(length):
212212
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
213213

214214

215+
def process_f_files(files):
216+
lst = {}
217+
for f in files:
218+
if f[-2:].lower() == '.f':
219+
with open(f, 'r') as fp:
220+
l = fp.read().split()
221+
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
222+
lst[os.path.basename(f)] = f
223+
else:
224+
lst[os.path.basename(f)] = f
225+
return list(lst.values())
226+
227+
215228
@pytest.mark.parametrize("reg_type", [0, 1, 2])
216229
@pytest.mark.parametrize("data_width", [8, 16, 32])
217230
@pytest.mark.parametrize("length", [0, 1, 2])
@@ -221,10 +234,11 @@ def test_axis_pipeline_register(request, length, data_width, reg_type):
221234
toplevel = dut
222235

223236
verilog_sources = [
224-
os.path.join(rtl_dir, f"{dut}.v"),
225-
os.path.join(rtl_dir, "axis_register.v"),
237+
os.path.join(rtl_dir, f"{dut}.f"),
226238
]
227239

240+
verilog_sources = process_f_files(verilog_sources)
241+
228242
parameters = {}
229243

230244
parameters['DATA_WIDTH'] = data_width

‎tb/axis_ram_switch/Makefile

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -34,10 +34,13 @@ WRAPPER = $(DUT)_wrap_$(S_COUNT)x$(M_COUNT)
3434
TOPLEVEL = $(WRAPPER)
3535
MODULE = test_$(DUT)
3636
VERILOG_SOURCES += $(WRAPPER).v
37-
VERILOG_SOURCES += ../../rtl/$(DUT).v
38-
VERILOG_SOURCES += ../../rtl/axis_adapter.v
39-
VERILOG_SOURCES += ../../rtl/arbiter.v
40-
VERILOG_SOURCES += ../../rtl/priority_encoder.v
37+
VERILOG_SOURCES += ../../rtl/$(DUT).f
38+
39+
# handle file list files
40+
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
41+
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
42+
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
43+
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
4144

4245
# module parameters
4346
export PARAM_FIFO_DEPTH := 4096

‎tb/axis_ram_switch/test_axis_ram_switch.py

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -323,6 +323,19 @@ def incrementing_payload(length):
323323
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
324324

325325

326+
def process_f_files(files):
327+
lst = {}
328+
for f in files:
329+
if f[-2:].lower() == '.f':
330+
with open(f, 'r') as fp:
331+
l = fp.read().split()
332+
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
333+
lst[os.path.basename(f)] = f
334+
else:
335+
lst[os.path.basename(f)] = f
336+
return list(lst.values())
337+
338+
326339
@pytest.mark.parametrize("m_data_width", [8, 32])
327340
@pytest.mark.parametrize("s_data_width", [8, 32])
328341
@pytest.mark.parametrize("m_count", [1, 4])
@@ -343,12 +356,11 @@ def test_axis_ram_switch(request, s_count, m_count, s_data_width, m_data_width):
343356

344357
verilog_sources = [
345358
wrapper_file,
346-
os.path.join(rtl_dir, f"{dut}.v"),
347-
os.path.join(rtl_dir, "axis_adapter.v"),
348-
os.path.join(rtl_dir, "arbiter.v"),
349-
os.path.join(rtl_dir, "priority_encoder.v"),
359+
os.path.join(rtl_dir, f"{dut}.f"),
350360
]
351361

362+
verilog_sources = process_f_files(verilog_sources)
363+
352364
parameters = {}
353365

354366
parameters['FIFO_DEPTH'] = 4096

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