Add support for file list files

Signed-off-by: Alex Forencich <[email protected]>

Author: alexforencich

rtl/axis_arb_mux.f

@@ -0,0 +1,3 @@
+axis_arb_mux.v
+arbiter.v
+priority_encoder.v

rtl/axis_async_fifo_adapter.f

@@ -0,0 +1,3 @@
+axis_async_fifo_adapter.v
+axis_async_fifo.v
+axis_adapter.v

rtl/axis_cobs_encode.f

@@ -0,0 +1,2 @@
+axis_cobs_encode.v
+axis_fifo.v

rtl/axis_fifo_adapter.f

@@ -0,0 +1,3 @@
+axis_fifo_adapter.v
+axis_fifo.v
+axis_adapter.v

rtl/axis_frame_length_adjust_fifo.f

@@ -0,0 +1,3 @@
+axis_frame_length_adjust_fifo.v
+axis_frame_length_adjust.v
+axis_fifo.v

rtl/axis_pipeline_register.f

@@ -0,0 +1,2 @@
+axis_pipeline_register.v
+axis_register.v

rtl/axis_ram_switch.f

@@ -0,0 +1,4 @@
+axis_ram_switch.v
+axis_adapter.v
+arbiter.v
+priority_encoder.v

rtl/axis_switch.f

@@ -0,0 +1,4 @@
+axis_switch.v
+axis_register.v
+arbiter.v
+priority_encoder.v

tb/axis_arb_mux/Makefile

@@ -33,9 +33,13 @@ WRAPPER  = $(DUT)_wrap_$(PORTS)
 TOPLEVEL = $(WRAPPER)
 MODULE   = test_$(DUT)
 VERILOG_SOURCES += $(WRAPPER).v
-VERILOG_SOURCES += ../../rtl/$(DUT).v
-VERILOG_SOURCES += ../../rtl/arbiter.v
-VERILOG_SOURCES += ../../rtl/priority_encoder.v
+VERILOG_SOURCES += ../../rtl/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_DATA_WIDTH := 8

tb/axis_arb_mux/test_axis_arb_mux.py

@@ -316,6 +316,19 @@ def incrementing_payload(length):
 rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
 
 
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
 @pytest.mark.parametrize("round_robin", [0, 1])
 @pytest.mark.parametrize("data_width", [8, 16, 32])
 @pytest.mark.parametrize("ports", [1, 4])
@@ -335,11 +348,11 @@ def test_axis_arb_mux(request, ports, data_width, round_robin):
 
     verilog_sources = [
         wrapper_file,
-        os.path.join(rtl_dir, f"{dut}.v"),
-        os.path.join(rtl_dir, "arbiter.v"),
-        os.path.join(rtl_dir, "priority_encoder.v"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['DATA_WIDTH'] = data_width