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lines changed Original file line number Diff line number Diff line change @@ -31,7 +31,7 @@ THE SOFTWARE.
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*/
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module i2c_master (
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input wire clk,
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- input wire rst ,
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+ input wire rst_n ,
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/*
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* Host interface
@@ -633,7 +633,7 @@ I/O pin. This would prevent devices from stretching the clock period.
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i2c_phy phy_instance (
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.clk(clk),
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- .rst(rst) ,
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+ .rst_n ,
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.phy_start_bit(phy_start_bit),
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.phy_stop_bit(phy_stop_bit),
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.phy_write_bit(phy_write_bit),
@@ -654,8 +654,8 @@ I/O pin. This would prevent devices from stretching the clock period.
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);
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- always @(posedge clk or posedge rst ) begin
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- if (rst ) begin
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+ always @(posedge clk or negedge rst_n ) begin
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+ if (~ rst_n ) begin
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state_reg <= STATE_IDLE;
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s_axis_cmd_ready_reg <= 1'b0 ;
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s_axis_data_tready_reg <= 1'b0 ;
Original file line number Diff line number Diff line change 2
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`timescale 1ns / 1ps
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module i2c_phy (
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input wire clk,
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- input wire rst ,
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+ input wire rst_n ,
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// Control signals
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input wire phy_start_bit,
@@ -315,9 +315,9 @@ module i2c_phy (
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end
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- always @(posedge clk or posedge rst ) begin
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+ always @(posedge clk or negedge rst_n ) begin
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- if (rst ) begin
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+ if (~ rst_n ) begin
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phy_rx_data_reg <= 1'b0 ;
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phy_state_reg <= PHY_STATE_IDLE;
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delay_reg <= 17'd0 ;
Original file line number Diff line number Diff line change @@ -7,7 +7,7 @@ module i2c_phy_tb;
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// Signals
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reg clk = 0 ;
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- reg rst = 0 ;
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+ reg rst = 1 ;
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reg phy_start_bit = 0 ;
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reg phy_stop_bit = 0 ;
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reg phy_write_bit = 0 ;
@@ -62,7 +62,7 @@ module i2c_phy_tb;
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// Instantiate the i2c_phy module
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i2c_phy uut (
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.clk (clk),
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- .rst (rst ),
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+ .rst (rst_n ),
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.phy_start_bit (phy_start_bit),
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.phy_stop_bit (phy_stop_bit),
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.phy_write_bit (phy_write_bit),
@@ -83,7 +83,7 @@ module i2c_phy_tb;
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);
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task initialize ;
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begin
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- rst = 1 ;
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+ rst = 0 ;
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phy_start_bit = 0 ;
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phy_stop_bit = 0 ;
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phy_write_bit = 0 ;
@@ -95,10 +95,10 @@ module i2c_phy_tb;
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task reset ;
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begin
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- rst = 1 ;
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- # (CLK_PERIOD * 5 );
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rst = 0 ;
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# (CLK_PERIOD * 5 );
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+ rst = 1 ;
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+ # (CLK_PERIOD * 5 );
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end
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endtask
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task write_operation (input tx_data);
Original file line number Diff line number Diff line change @@ -37,7 +37,7 @@ module i2c_single_reg #(
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parameter DEBUG = 0
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) (
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input wire clk,
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- input wire rst ,
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+ input wire rst_n ,
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/*
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* I2C interface
@@ -102,8 +102,8 @@ module i2c_single_reg #(
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wire start_bit = sda_negedge && scl_i_reg;
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wire stop_bit = sda_posedge && scl_i_reg;
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- always @(posedge clk or negedge rst ) begin
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- if (rst ) begin
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+ always @(posedge clk or negedge rst_n ) begin
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+ if (~ rst_n ) begin
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state_reg <= STATE_IDLE;
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sda_o_reg <= 1'b1 ;
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end else begin
Original file line number Diff line number Diff line change @@ -33,7 +33,7 @@ module i2c_slave #(
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parameter FILTER_LEN = 4
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) (
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input wire clk,
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- input wire rst ,
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+ input wire rst_n ,
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/*
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* Host interface
@@ -446,8 +446,8 @@ I/O pin. This would prevent devices from stretching the clock period.
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end
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end
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- always @(posedge clk or negedge rst ) begin
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- if (rst ) begin
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+ always @(posedge clk or negedge rst_n ) begin
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+ if (~ rst_n ) begin
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state_reg <= STATE_IDLE;
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s_axis_data_tready_reg <= 1'b0 ;
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m_axis_data_tvalid_reg <= 1'b0 ;
Original file line number Diff line number Diff line change @@ -15,6 +15,8 @@ module i2c_master_tb;
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reg clk = 0 ;
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reg rst = 0 ;
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+ wire rst_n;
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+ assign rst_n=~ rst;
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reg [7 :0 ] current_test = 0 ;
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// I2C master signals
@@ -92,7 +94,7 @@ module i2c_master_tb;
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.DEBUG(1 )
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) i2c_reg (
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.clk(clk),
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- .rst(rst) ,
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+ .rst_n ,
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.scl_i(scl_wire),
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.scl_o(scl_o_3),
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.scl_t(scl_t_3),
@@ -184,7 +186,7 @@ module i2c_master_tb;
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.FILTER_LEN(4 )
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) i2c_slave_inst (
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.clk(clk),
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- .rst(rst) ,
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+ .rst_n ,
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.release_bus(release_bus_4),
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.s_axis_data_tdata(s_axis_data_tdata_4),
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.s_axis_data_tvalid(s_axis_data_tvalid_4),
@@ -363,7 +365,7 @@ module i2c_master_tb;
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i2c_master UUT (
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.clk(clk),
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- .rst(rst) ,
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+ .rst_n ,
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.s_axis_cmd_address(s_axis_cmd_address),
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.s_axis_cmd_start(s_axis_cmd_start),
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.s_axis_cmd_read(s_axis_cmd_read),
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