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Commit 72fc6bc

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negative reset
1 parent 14a8648 commit 72fc6bc

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6 files changed

+23
-21
lines changed

6 files changed

+23
-21
lines changed

rtl/i2c_master.v

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ THE SOFTWARE.
3131
*/
3232
module i2c_master (
3333
input wire clk,
34-
input wire rst,
34+
input wire rst_n,
3535

3636
/*
3737
* Host interface
@@ -633,7 +633,7 @@ I/O pin. This would prevent devices from stretching the clock period.
633633

634634
i2c_phy phy_instance (
635635
.clk(clk),
636-
.rst(rst),
636+
.rst_n,
637637
.phy_start_bit(phy_start_bit),
638638
.phy_stop_bit(phy_stop_bit),
639639
.phy_write_bit(phy_write_bit),
@@ -654,8 +654,8 @@ I/O pin. This would prevent devices from stretching the clock period.
654654
);
655655

656656

657-
always @(posedge clk or posedge rst) begin
658-
if (rst) begin
657+
always @(posedge clk or negedge rst_n) begin
658+
if (~rst_n) begin
659659
state_reg <= STATE_IDLE;
660660
s_axis_cmd_ready_reg <= 1'b0;
661661
s_axis_data_tready_reg <= 1'b0;

rtl/i2c_phy.v

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
`timescale 1ns / 1ps
33
module i2c_phy (
44
input wire clk,
5-
input wire rst,
5+
input wire rst_n,
66

77
// Control signals
88
input wire phy_start_bit,
@@ -315,9 +315,9 @@ module i2c_phy (
315315
end
316316

317317

318-
always @(posedge clk or posedge rst) begin
318+
always @(posedge clk or negedge rst_n) begin
319319

320-
if (rst) begin
320+
if (~rst_n) begin
321321
phy_rx_data_reg <= 1'b0;
322322
phy_state_reg <= PHY_STATE_IDLE;
323323
delay_reg <= 17'd0;

rtl/i2c_phy_tb.sv

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ module i2c_phy_tb;
77

88
// Signals
99
reg clk = 0;
10-
reg rst = 0;
10+
reg rst = 1;
1111
reg phy_start_bit = 0;
1212
reg phy_stop_bit = 0;
1313
reg phy_write_bit = 0;
@@ -62,7 +62,7 @@ module i2c_phy_tb;
6262
// Instantiate the i2c_phy module
6363
i2c_phy uut (
6464
.clk(clk),
65-
.rst(rst),
65+
.rst(rst_n),
6666
.phy_start_bit(phy_start_bit),
6767
.phy_stop_bit(phy_stop_bit),
6868
.phy_write_bit(phy_write_bit),
@@ -83,7 +83,7 @@ module i2c_phy_tb;
8383
);
8484
task initialize;
8585
begin
86-
rst = 1;
86+
rst = 0;
8787
phy_start_bit = 0;
8888
phy_stop_bit = 0;
8989
phy_write_bit = 0;
@@ -95,10 +95,10 @@ module i2c_phy_tb;
9595

9696
task reset;
9797
begin
98-
rst = 1;
99-
#(CLK_PERIOD * 5);
10098
rst = 0;
10199
#(CLK_PERIOD * 5);
100+
rst = 1;
101+
#(CLK_PERIOD * 5);
102102
end
103103
endtask
104104
task write_operation(input tx_data);

rtl/i2c_single_reg.v

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ module i2c_single_reg #(
3737
parameter DEBUG = 0
3838
) (
3939
input wire clk,
40-
input wire rst,
40+
input wire rst_n,
4141

4242
/*
4343
* I2C interface
@@ -102,8 +102,8 @@ module i2c_single_reg #(
102102
wire start_bit = sda_negedge && scl_i_reg;
103103
wire stop_bit = sda_posedge && scl_i_reg;
104104

105-
always @(posedge clk or negedge rst) begin
106-
if (rst) begin
105+
always @(posedge clk or negedge rst_n) begin
106+
if (~rst_n) begin
107107
state_reg <= STATE_IDLE;
108108
sda_o_reg <= 1'b1;
109109
end else begin

rtl/i2c_slave.v

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ module i2c_slave #(
3333
parameter FILTER_LEN = 4
3434
) (
3535
input wire clk,
36-
input wire rst,
36+
input wire rst_n,
3737

3838
/*
3939
* Host interface
@@ -446,8 +446,8 @@ I/O pin. This would prevent devices from stretching the clock period.
446446
end
447447
end
448448

449-
always @(posedge clk or negedge rst) begin
450-
if (rst) begin
449+
always @(posedge clk or negedge rst_n) begin
450+
if (~rst_n) begin
451451
state_reg <= STATE_IDLE;
452452
s_axis_data_tready_reg <= 1'b0;
453453
m_axis_data_tvalid_reg <= 1'b0;

tb/i2c_master_tb.v

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@ module i2c_master_tb;
1515

1616
reg clk = 0;
1717
reg rst = 0;
18+
wire rst_n;
19+
assign rst_n=~rst;
1820
reg [7:0] current_test = 0;
1921

2022
// I2C master signals
@@ -92,7 +94,7 @@ module i2c_master_tb;
9294
.DEBUG(1)
9395
) i2c_reg (
9496
.clk(clk),
95-
.rst(rst),
97+
.rst_n,
9698
.scl_i(scl_wire),
9799
.scl_o(scl_o_3),
98100
.scl_t(scl_t_3),
@@ -184,7 +186,7 @@ module i2c_master_tb;
184186
.FILTER_LEN(4)
185187
) i2c_slave_inst (
186188
.clk(clk),
187-
.rst(rst),
189+
.rst_n,
188190
.release_bus(release_bus_4),
189191
.s_axis_data_tdata(s_axis_data_tdata_4),
190192
.s_axis_data_tvalid(s_axis_data_tvalid_4),
@@ -363,7 +365,7 @@ module i2c_master_tb;
363365

364366
i2c_master UUT (
365367
.clk(clk),
366-
.rst(rst),
368+
.rst_n,
367369
.s_axis_cmd_address(s_axis_cmd_address),
368370
.s_axis_cmd_start(s_axis_cmd_start),
369371
.s_axis_cmd_read(s_axis_cmd_read),

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