drivers: adc: ad7768: Fix DCLK divider register encoding

Fix off-by-one error in AD7768_INTERFACE_CFG_DCLK_DIV_MODE macro.
The macro was incorrectly calculating register values, causing wrong
DCLK division settings to be written to hardware.

Corrected mapping:
- Divide by 8 → 0 (bits 00)
- Divide by 4 → 1 (bits 01)
- Divide by 2 → 2 (bits 10)
- Divide by 1 → 3 (bits 11)

Fixes: 5f17a1b ("drivers: adc: ad7768: Update driver")
Signed-off-by: Antoniu Miclaus <[email protected]>

Author: amiclaus

drivers/adc/ad7768/ad7768.h

@@ -102,7 +102,7 @@
 #define AD7768_INTERFACE_CFG_CRC_SEL(x)			(((x) & 0x3) << 2)
 #define AD7768_INTERFACE_CFG_DCLK_DIV(x)		(((x) & 0x3) << 0)
 #define AD7768_INTERFACE_CFG_DCLK_DIV_MSK		NO_OS_GENMASK(1, 0)
-#define AD7768_INTERFACE_CFG_DCLK_DIV_MODE(x)		(4 - no_os_find_first_set_bit(x))
+#define AD7768_INTERFACE_CFG_DCLK_DIV_MODE(x)		(3 - no_os_find_first_set_bit(x))
 #define AD7768_MAX_DCLK_DIV				8
 
 #define AD7768_RESOLUTION				24