[AVR] Support 8 and 16-bit atomic loads and stores

Author: Dylan McKay

lib/Target/AVR/AVRExpandPseudoInsts.cpp

@@ -15,6 +15,7 @@
 
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 
 #include "AVR.h"
@@ -30,8 +31,15 @@ namespace llvm {
 class AVRExpandPseudo : public MachineFunctionPass {
 public:
   static char ID;
+
   const AVRRegisterInfo *TRI;
   const TargetInstrInfo *TII;
+
+  /// The register to be used for temporary storage.
+  const unsigned SCRATCH_REGISTER = AVR::R0;
+  /// The IO address of the status register.
+  const unsigned SREG_ADDR = 0x3f;
+
   AVRExpandPseudo() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override;
@@ -57,6 +65,13 @@ class AVRExpandPseudo : public MachineFunctionPass {
                               unsigned DstReg) {
     return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
   }
+
+  MachineRegisterInfo &getRegInfo(Block &MBB) { return MBB.getParent()->getRegInfo(); }
+
+  template<typename Func>
+  bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
+
+  bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
 };
 
 char AVRExpandPseudo::ID = 0;
@@ -80,9 +95,16 @@ bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
   TRI = static_cast<const AVRRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
   TII = TM.getSubtargetImpl()->getInstrInfo();
 
-  typedef MachineFunction::iterator FuncIt;
-  for (FuncIt MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
-    Modified |= expandMBB(*MFI);
+  for(Block &MBB : MF) {
+    bool ContinueExpanding = true;
+
+    // Continue expanding the block until all pseudos are expanded.
+    do {
+      bool BlockModified = expandMBB(MBB);
+      Modified |= BlockModified;
+
+      ContinueExpanding = BlockModified;
+    } while(ContinueExpanding);
   }
 
   return Modified;
@@ -799,6 +821,60 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
   return true;
 }
 
+template<typename Func>
+bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
+  // Remove the pseudo instruction.
+  MachineInstr &MI = *MBBI;
+
+  // Store the SREG.
+  buildMI(MBB, MBBI, AVR::INRdA)
+    .addReg(SCRATCH_REGISTER, RegState::Define)
+    .addImm(SREG_ADDR);
+
+  // Disable exceptions.
+  buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
+
+  f(MI);
+
+  // Restore the status reg.
+  buildMI(MBB, MBBI, AVR::OUTARr)
+    .addImm(SREG_ADDR)
+    .addReg(SCRATCH_REGISTER);
+
+  MI.eraseFromParent();
+  return true;
+}
+
+bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI) {
+  return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
+      auto Op1 = MI.getOperand(0);
+      auto Op2 = MI.getOperand(1);
+
+      buildMI(MBB, MBBI, Opcode).addOperand(Op1).addOperand(Op2);
+  });
+}
+
+template<>
+bool AVRExpandPseudo::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
+  return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
+}
+
+
+template<>
+bool AVRExpandPseudo::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
+  return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
+}
+
+template<>
+bool AVRExpandPseudo::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
+  return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
+}
+
+template<>
+bool AVRExpandPseudo::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
+  return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
+}
+
 template <>
 bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
@@ -1305,7 +1381,7 @@ bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
 
   buildMI(MBB, MBBI, AVR::INRdA)
     .addReg(AVR::R0, RegState::Define)
-    .addImm(0x3f)
+    .addImm(SREG_ADDR)
     .setMIFlags(Flags);
 
   buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
@@ -1316,7 +1392,7 @@ bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
     .setMIFlags(Flags);
 
   buildMI(MBB, MBBI, AVR::OUTARr)
-    .addImm(0x3f)
+    .addImm(SREG_ADDR)
     .addReg(AVR::R0, RegState::Kill)
     .setMIFlags(Flags);
 
@@ -1359,6 +1435,10 @@ bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
     EXPAND(AVR::LDWRdPtrPd);
   case AVR::LDDWRdYQ: //:FIXME: remove this once PR13375 gets fixed
     EXPAND(AVR::LDDWRdPtrQ);
+    EXPAND(AVR::AtomicLoad8);
+    EXPAND(AVR::AtomicLoad16);
+    EXPAND(AVR::AtomicStore8);
+    EXPAND(AVR::AtomicStore16);
     EXPAND(AVR::STSWKRr);
     EXPAND(AVR::STWPtrRr);
     EXPAND(AVR::STWPtrPiRr);

lib/Target/AVR/AVRInstrInfo.td

@@ -1237,6 +1237,28 @@ isReMaterializable = 1 in
                  Requires<[HasSRAM]>;
 }
 
+def AtomicLoad8  :  Pseudo<(outs GPR8:$rd),
+                           (ins PTRREGS:$rr),
+                           "atomic_load $rd, $rr",
+                           [(set GPR8:$rd, (atomic_load i16:$rr))]>;
+
+def AtomicLoad16 : Pseudo<(outs DREGS:$rd),
+                          (ins PTRREGS:$rr),
+                          "atomic_load $rd, $rr",
+                          [(set DREGS:$rd, (atomic_load i16:$rr))]>;
+
+def AtomicStore8  : Pseudo<(outs),
+                           (ins LDSTPtrReg:$rd, GPR8:$rr),
+                           "atomic_store $rd, $rr",
+                           [(atomic_store i16:$rd, GPR8:$rr)]>,
+                    Requires<[HasSRAM]>;
+
+def AtomicStore16 : Pseudo<(outs),
+                           (ins LDSTPtrReg:$rd, DREGS:$rr),
+                           "atomic_store $rd, $rr",
+                           [(atomic_store i16:$rd, DREGS:$rr)]>,
+                    Requires<[HasSRAM]>;
+
 // Indirect store from register to data space.
 def STSKRr : F32DM<0b1,
                    (outs),

test/CodeGen/AVR/atomics.ll

@@ -0,0 +1,46 @@
+; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+
+; Tests atomic operations on AVR
+
+; CHECK-LABEL: atomic_load8
+; CHECK:      in r0, 63
+; CHECK-NEXT: cli
+; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
+; CHECK-NEXT: out 63, r0
+define i8 @atomic_load8(i8* %foo) {
+  %val = load atomic i8, i8* %foo unordered, align 1
+  ret i8 %val
+}
+
+; CHECK-LABEL: atomic_load16
+; CHECK:      in r0, 63
+; CHECK-NEXT: cli
+; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
+; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]+
+; CHECK-NEXT: out 63, r0
+define i16 @atomic_load16(i16* %foo) {
+  %val = load atomic i16, i16* %foo unordered, align 2
+  ret i16 %val
+}
+
+; CHECK-LABEL: atomic_store8
+; CHECK:      in r0, 63
+; CHECK-NEXT: cli
+; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
+; CHECK-NEXT: out 63, r0
+define void @atomic_store8(i8* %foo) {
+  store atomic i8 1, i8* %foo unordered, align 1
+  ret void
+}
+
+; CHECK-LABEL: atomic_store16
+; CHECK:      in r0, 63
+; CHECK-NEXT: cli
+; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
+; CHECK-NEXT: std [[RD:(X|Y|Z)]]+1, [[RR:r[0-9]+]]
+; CHECK-NEXT: out 63, r0
+define void @atomic_store16(i16* %foo) {
+  store atomic i16 1, i16* %foo unordered, align 2
+  ret void
+}
+