[layout][AArch64] Do not convert ADDS/SUBS back to three-address

The `ADDS/SUBS` MIR instructions are usually used in implementing conditions
since they set the condition flags. Because X86 uses `CMP`-like instructions
for the same purpose, which follow the two-address format, we avoid
converting these AArch64 instructions back to the three-address format
during the `twoaddressinstruction` pass. This way, they retain the
two-address format which we have imposed.

Author: blackgeorge-boom

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -5625,14 +5625,18 @@ MachineInstr *AArch64InstrInfo::convertToThreeAddress(
   switch (MIOpc) {
   default:
     llvm_unreachable("Unreachable!");
-  case AArch64::ADDXrr:
-  case AArch64::ADDWrr:
   case AArch64::ADDSXrr:
   case AArch64::ADDSWrr:
-  case AArch64::SUBXrr:
-  case AArch64::SUBWrr:
   case AArch64::SUBSXrr:
   case AArch64::SUBSWrr:
+    // For the instructions that set the flags, do not turn them back into the
+    // three-address format, since the equivalent X86 instructions (usually
+    // CMP-like) have the two-address format.
+    return nullptr;
+  case AArch64::ADDXrr:
+  case AArch64::ADDWrr:
+  case AArch64::SUBXrr:
+  case AArch64::SUBWrr:
     assert(MI.getNumOperands() >= 3 && "Unknown add/sub instruction!");
     unsigned Opc = MIOpc;