Fix incorrect BRAM reporting (fastmachinelearning#798)

Author: bo3z

hls4ml/templates/vivado/build_prj.tcl

@@ -236,15 +236,15 @@ if {$opt(export)} {
 
 if {$opt(vsynth)} {
     puts "***** VIVADO SYNTHESIS *****"
-    if {[file exist ${project_name}_prj/solution1/syn/vhdl]} {
+    if {[file exist ${project_name}_prj/solution1/syn/verilog]} {
         set time_start [clock clicks -milliseconds]
         exec vivado -mode batch -source vivado_synth.tcl >@ stdout
         set time_end [clock clicks -milliseconds]
         report_time "VIVADO SYNTHESIS" $time_start $time_end
     } else {
-        puts "ERROR: Cannot find generated VHDL files. Did you run C synthesis?"
+        puts "ERROR: Cannot find generated Verilog files. Did you run C synthesis?"
         exit 1
     }
 }
 
-exit
+exit

hls4ml/templates/vivado/nnet_utils/nnet_dense_resource.h

@@ -26,10 +26,13 @@ void dense_resource_rf_leq_nin(data_T data[CONFIG_T::n_in], res_T res[CONFIG_T::
     assert((multiplier_limit == block_factor) && "This function is correct only for RF <= N_IN");
 
     #pragma HLS function_instantiate variable=weights,biases
-    //#pragma HLS RESOURCE variable=weights core=RAM_2P_BRAM Commenting out the deisgnation HLS seems to choose correctly
     #pragma HLS ARRAY_RESHAPE   variable=weights block factor=block_factor
     #pragma HLS ARRAY_PARTITION variable=biases complete
 
+    if (CONFIG_T::reuse_factor > 1) {
+        #pragma HLS RESOURCE variable=weights core=ROM_nP_BRAM
+    }
+
     typename CONFIG_T::accum_t acc[CONFIG_T::n_out];
     #pragma HLS ARRAY_PARTITION variable=acc complete
 
@@ -97,10 +100,13 @@ void dense_resource_rf_gt_nin_rem0(data_T data[CONFIG_T::n_in], res_T res[CONFIG
     assert((rufactor > nin && rufactor % nin == 0) && "This function is correct only for RF > N_IN && RF % N_IN == 0");
 
     #pragma HLS function_instantiate variable=weights,biases
-    //#pragma HLS RESOURCE variable=weights core=RAM_2P_BRAM Commenting out the deisgnation HLS seems to choose correctly
     #pragma HLS ARRAY_RESHAPE   variable=weights block factor=block_factor
     #pragma HLS ARRAY_PARTITION variable=biases complete
 
+    if (CONFIG_T::reuse_factor > 1) {
+        #pragma HLS RESOURCE variable=weights core=ROM_nP_BRAM
+    }
+
     typename CONFIG_T::accum_t acc[CONFIG_T::n_out];
     #pragma HLS ARRAY_PARTITION variable=acc complete
 
@@ -176,10 +182,13 @@ void dense_resource_rf_gt_nin(data_T data[CONFIG_T::n_in], res_T res[CONFIG_T::n
     assert((rufactor > nin) && "This function is correct only for RF > N_IN");
 
     #pragma HLS function_instantiate variable=weights,biases
-    //#pragma HLS RESOURCE variable=weights core=RAM_2P_BRAM Commenting out the deisgnation HLS seems to choose correctly
     #pragma HLS ARRAY_RESHAPE   variable=weights block factor=block_factor
     #pragma HLS ARRAY_PARTITION variable=biases complete
 
+    if (CONFIG_T::reuse_factor > 1) {
+        #pragma HLS RESOURCE variable=weights core=ROM_nP_BRAM
+    }
+
     typename CONFIG_T::accum_t acc[CONFIG_T::n_out];
     #pragma HLS ARRAY_PARTITION variable=acc complete
 

hls4ml/templates/vivado/vivado_synth.tcl

@@ -1,6 +1,6 @@
 set tcldir [file dirname [info script]]
 source [file join $tcldir project.tcl]
 
-add_files ${project_name}_prj/solution1/syn/vhdl
+add_files ${project_name}_prj/solution1/syn/verilog
 synth_design -top ${project_name} -part $part
-report_utilization -file vivado_synth.rpt
+report_utilization -file vivado_synth.rpt