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# RISC-V Architecture Test SIG
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# :red_circle: IMPORTANT DISCLAIMER :red_circle:
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The current default branch [master] will be completely replaced with branch [riscof-dev](https://github.com/riscv-non-isa/riscv-arch-test/tree/riscof-dev) on **1st MAY 2022**.
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This transition essentially migrates the current framework to the RISCOF framework.
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This provides a much richer and configurable environment for targets to test their compatibility.
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The current framework will be archived and **NO LONGER SUPPORTED AFTER 1st MAY 2022.**
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It is therefore recommended that ALL model/target owners migrate their targets to the riscof environment ASAP.
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More information on porting your target to RISCOF is available here: https://riscof.readthedocs.io/en/stable/
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# RISC-V Architecture Test SIG
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This is a repository for the work of the RISC-V Foundation Architecture Test SIG. The repository owners are:
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For contributions and reporting issues please refer to [CONTRIBUTION.md](CONTRIBUTION.md)
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## Test Disclaimers
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The following are the exhaustive list of disclaimers that can be used as waivers by target owners
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have compressed extension support enabled by default. Targets without the compressed extension
3. The machine mode trap handler used in the privilege tests assumes one of the following conditions.
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Targets not satisfying any of the following conditions are bound to fail the entire
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## Quick Links:
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- RISCOF \[[DOCS](https://riscof.readthedocs.io/en/latest/)\]\[[REPO](https://gitlab.com/incoresemi/riscof/)\]: This is the next version of the architectural test framework currently under development
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- RISCV-ISAC \[[DOCS](https://riscv-isac.readthedocs.io/en/latest/index.html)\]\[[REPO](https://github.com/riscv/riscv-isac)\] : This is an ISA level coverage extraction tool for RISC-V which used to generate the coverage statistics of the architectural tests.
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- RISCV-CTG: \[[DOCS](https://riscv-ctg.readthedocs.io/en/latest/index.html)\]\[[REPO](https://github.com/riscv/riscv-ctg)\]: This is a RISC-V Architectural Test generator used to generate some of the tests already checked into this repository. Docs to be updated soon !!
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- RISCOF \[[DOCS](https://riscof.readthedocs.io/en/latest/)\]\[[REPO](https://github.com/riscv-software-src/riscof)\]: This is the next version of the architectural test framework currently under development
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- RISCV-ISAC \[[DOCS](https://riscv-isac.readthedocs.io/en/latest/index.html)\]\[[REPO](https://github.com/riscv-software-src/riscv-isac)\] : This is an ISA level coverage extraction tool for RISC-V which used to generate the coverage statistics of the architectural tests.
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- RISCV-CTG: \[[DOCS](https://riscv-ctg.readthedocs.io/en/latest/index.html)\]\[[REPO](https://github.com/riscv-software-src/riscv-ctg)\]: This is a RISC-V Architectural Test generator used to generate some of the tests already checked into this repository.
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-[Videos](https://youtu.be/VIW1or1Oubo): This Global Forum 2020 video provides an introduction to the above mentioned tools
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-[riscvOVPsim](https://github.com/riscv-ovpsim/imperas-riscv-tests): Imperas freeware RISC-V reference simulator for compliance testing
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-[riscvOVPsimPlus](https://www.ovpworld.org/riscvOVPsimPlus/): Imperas enhanced freeware RISC-V reference simulator for test development and verification
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