Add orig_insn_map: mapping from original to new insn indices.

This is needed in the Cranelift client code in order to track
source-location mapping for debug info: we need to be able to shuffle
the source locations into the new locations after the regalloc has done
its instruction-stream editing. The `target_map` result is not quite
good enough, because it only provides old --> new mappings at a basic
block granularity.

Author: cfallin

lib/src/backtracking.rs

@@ -2803,7 +2803,7 @@ pub fn alloc_main<F: Function>(
     // ======== BEGIN Create the RegAllocResult ========
 
     match final_insns_and_targetmap__or_err {
-        Ok((ref final_insns, ref _targetmap)) => {
+        Ok((ref final_insns, ..)) => {
             info!(
                 "alloc_main:   out: VLRs: {} initially, {} processed",
                 num_vlrs_initial, num_vlrs_processed
@@ -2829,7 +2829,7 @@ pub fn alloc_main<F: Function>(
         }
     }
 
-    let (final_insns, target_map) = match final_insns_and_targetmap__or_err {
+    let (final_insns, target_map, orig_insn_map) = match final_insns_and_targetmap__or_err {
         Err(e) => {
             info!("alloc_main: fail");
             return Err(e);
@@ -2891,6 +2891,7 @@ pub fn alloc_main<F: Function>(
     let ra_res = RegAllocResult {
         insns: final_insns,
         target_map,
+        orig_insn_map,
         clobbered_registers,
         num_spill_slots: spill_slot_allocator.slots.len() as u32,
         block_annotations,

lib/src/inst_stream.rs

@@ -432,7 +432,14 @@ fn map_vregs_to_rregs<F: Function>(
 fn add_spills_reloads_and_moves<F: Function>(
     func: &mut F,
     mut insts_to_add: Vec<InstToInsertAndPoint>,
-) -> Result<(Vec<F::Inst>, TypedIxVec<BlockIx, InstIx>), String> {
+) -> Result<
+    (
+        Vec<F::Inst>,
+        TypedIxVec<BlockIx, InstIx>,
+        TypedIxVec<InstIx, Option<InstIx>>,
+    ),
+    String,
+> {
     // Construct the final code by interleaving the mapped code with the the
     // spills, reloads and moves that we have been requested to insert.  To do
     // that requires having the latter sorted by InstPoint.
@@ -447,6 +454,7 @@ fn add_spills_reloads_and_moves<F: Function>(
 
     let mut insns: Vec<F::Inst> = vec![];
     let mut target_map: TypedIxVec<BlockIx, InstIx> = TypedIxVec::new();
+    let mut orig_insn_map: TypedIxVec<InstIx, Option<InstIx>> = TypedIxVec::new();
 
     for iix in func.insn_indices() {
         // Is `iix` the first instruction in a block?  Meaning, are we
@@ -463,15 +471,18 @@ fn add_spills_reloads_and_moves<F: Function>(
             && insts_to_add[curITA].point == InstPoint::new_reload(iix)
         {
             insns.push(insts_to_add[curITA].inst.construct(func));
+            orig_insn_map.push(None);
             curITA += 1;
         }
         // Copy the inst at `iix` itself
+        orig_insn_map.push(Some(iix));
         insns.push(func.get_insn(iix).clone());
         // And copy the extra insts that are to be placed at the spill point of
         // `iix`.
         while curITA < insts_to_add.len() && insts_to_add[curITA].point == InstPoint::new_spill(iix)
         {
             insns.push(insts_to_add[curITA].inst.construct(func));
+            orig_insn_map.push(None);
             curITA += 1;
         }
 
@@ -485,7 +496,7 @@ fn add_spills_reloads_and_moves<F: Function>(
     debug_assert!(curITA == insts_to_add.len());
     debug_assert!(curB.get() == func.blocks().len() as u32);
 
-    Ok((insns, target_map))
+    Ok((insns, target_map, orig_insn_map))
 }
 
 //=============================================================================
@@ -501,7 +512,14 @@ pub(crate) fn edit_inst_stream<F: Function>(
     reg_universe: &RealRegUniverse,
     has_multiple_blocks_per_frag: bool,
     use_checker: bool,
-) -> Result<(Vec<F::Inst>, TypedIxVec<BlockIx, InstIx>), RegAllocError> {
+) -> Result<
+    (
+        Vec<F::Inst>,
+        TypedIxVec<BlockIx, InstIx>,
+        TypedIxVec<InstIx, Option<InstIx>>,
+    ),
+    RegAllocError,
+> {
     map_vregs_to_rregs(
         func,
         frag_map,

lib/src/lib.rs

@@ -313,6 +313,12 @@ pub struct RegAllocResult<F: Function> {
     /// branch targets appropriately.
     pub target_map: TypedIxVec<BlockIx, InstIx>,
 
+    /// Full mapping from new instruction indices to original instruction
+    /// indices. May be needed by the client to, for example, update metadata
+    /// such as debug/source-location info as the instructions are spliced
+    /// and reordered.
+    pub orig_insn_map: TypedIxVec</* new */ InstIx, /* orig */ Option<InstIx>>,
+
     /// Which real registers were overwritten? This will contain all real regs
     /// that appear as defs or modifies in register slots of the output
     /// instruction list.  This will only list registers that are available to

lib/src/linear_scan.rs

@@ -3251,7 +3251,7 @@ fn apply_registers<F: Function>(
         use_checker,
     );
 
-    let (final_insns, target_map) = match final_insns_and_targetmap_or_err {
+    let (final_insns, target_map, orig_insn_map) = match final_insns_and_targetmap_or_err {
         Err(e) => return Err(e),
         Ok(pair) => pair,
     };
@@ -3295,6 +3295,7 @@ fn apply_registers<F: Function>(
     let ra_res = RegAllocResult {
         insns: final_insns,
         target_map,
+        orig_insn_map,
         clobbered_registers,
         num_spill_slots,
         block_annotations: None,