winch(x64): Ensure correct operand size on memory alignment check (#13337)

Prior to this commit, the alignment check implementation part of the
threads proposal was erroneously relying on the byte access size to
calcuate the effective address, this would result in a panic at
Cranelift's emission layer when mixing immediates and access sizes
smaller than 4-bytes.

The fix relies on the heap size for the arithmetic operations related
to calculating the effective address and alignment calculation,
mirroring what the heap address calculation will use prior to a memory
access.

Author: saulecabrera

tests/disas/winch/x64/atomic/load/i32_atomic_load16_u.wat

@@ -20,8 +20,8 @@
 ;;       movq    %rsi, 0x10(%rsp)
 ;;       movl    %edx, 0xc(%rsp)
 ;;       movl    0xc(%rsp), %eax
-;;       andw    $1, %ax
-;;       cmpw    $0, %ax
+;;       andl    $1, %eax
+;;       cmpl    $0, %eax
 ;;       jne     0x65
 ;;   46: movl    0xc(%rsp), %eax
 ;;       movq    0x30(%r14), %r11

tests/disas/winch/x64/atomic/load/i64_atomic_load.wat

@@ -14,22 +14,22 @@
 ;;       movq    0x18(%r11), %r11
 ;;       addq    $0x10, %r11
 ;;       cmpq    %rsp, %r11
-;;       ja      0x5e
+;;       ja      0x5c
 ;;   1c: movq    %rdi, %r14
 ;;       subq    $0x10, %rsp
 ;;       movq    %rdi, 8(%rsp)
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0, %eax
-;;       andq    $7, %rax
-;;       cmpq    $0, %rax
-;;       jne     0x60
-;;   44: movl    $0, %eax
+;;       andl    $7, %eax
+;;       cmpl    $0, %eax
+;;       jne     0x5e
+;;   42: movl    $0, %eax
 ;;       movq    0x38(%r14), %rcx
 ;;       movl    %eax, %eax
 ;;       addq    %rax, %rcx
 ;;       movq    (%rcx), %rax
 ;;       addq    $0x10, %rsp
 ;;       popq    %rbp
 ;;       retq
+;;   5c: ud2
 ;;   5e: ud2
-;;   60: ud2

tests/disas/winch/x64/atomic/load/i64_atomic_load16_u.wat

@@ -20,8 +20,8 @@
 ;;       movq    %rdi, 8(%rsp)
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0, %eax
-;;       andw    $1, %ax
-;;       cmpw    $0, %ax
+;;       andl    $1, %eax
+;;       cmpl    $0, %eax
 ;;       jne     0x5f
 ;;   42: movl    $0, %eax
 ;;       movq    0x38(%r14), %rcx

tests/disas/winch/x64/atomic/load/large_offset.wat

@@ -0,0 +1,53 @@
+;;! target = "x86_64"
+;;! test = "winch"
+
+(module
+  (memory 2)
+  (func (export "f") (param i32) (result i32)
+    local.get 0
+    i32.atomic.load16_u offset=0x80000000
+  )
+)
+;; wasm[0]::function[0]:
+;;       pushq   %rbp
+;;       movq    %rsp, %rbp
+;;       movq    8(%rdi), %r11
+;;       movq    0x18(%r11), %r11
+;;       addq    $0x20, %r11
+;;       cmpq    %rsp, %r11
+;;       ja      0x9c
+;;   1c: movq    %rdi, %r14
+;;       subq    $0x20, %rsp
+;;       movq    %rdi, 0x18(%rsp)
+;;       movq    %rsi, 0x10(%rsp)
+;;       movl    %edx, 0xc(%rsp)
+;;       movl    0xc(%rsp), %eax
+;;       movl    $0x80000000, %r11d
+;;       addl    %r11d, %eax
+;;       andl    $1, %eax
+;;       cmpl    $0, %eax
+;;       jne     0x9e
+;;   4f: movl    0xc(%rsp), %eax
+;;       movq    0x40(%r14), %rcx
+;;       movl    %eax, %edx
+;;       movl    $0x80000002, %r11d
+;;       addq    %r11, %rdx
+;;       jb      0xa0
+;;   68: cmpq    %rcx, %rdx
+;;       ja      0xa2
+;;   71: movq    0x38(%r14), %rbx
+;;       movl    %eax, %eax
+;;       addq    %rax, %rbx
+;;       movl    $0x80000000, %r11d
+;;       addq    %r11, %rbx
+;;       movl    $0, %esi
+;;       cmpq    %rcx, %rdx
+;;       cmovaq  %rsi, %rbx
+;;       movzwq  (%rbx), %rax
+;;       addq    $0x20, %rsp
+;;       popq    %rbp
+;;       retq
+;;   9c: ud2
+;;   9e: ud2
+;;   a0: ud2
+;;   a2: ud2

tests/disas/winch/x64/atomic/rmw/add/i32_atomic_rmw16_addu.wat

@@ -19,8 +19,8 @@
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0x2a, %eax
 ;;       movl    $0, %ecx
-;;       andw    $1, %cx
-;;       cmpw    $0, %cx
+;;       andl    $1, %ecx
+;;       cmpl    $0, %ecx
 ;;       jne     0x6c
 ;;   48: movl    $0, %ecx
 ;;       movq    0x30(%r14), %r11

tests/disas/winch/x64/atomic/rmw/add/i64_atomic_rmw16_addu.wat

@@ -19,8 +19,8 @@
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0x2a, %eax
 ;;       movl    $0, %ecx
-;;       andw    $1, %cx
-;;       cmpw    $0, %cx
+;;       andl    $1, %ecx
+;;       cmpl    $0, %ecx
 ;;       jne     0x6d
 ;;   48: movl    $0, %ecx
 ;;       movq    0x30(%r14), %r11

tests/disas/winch/x64/atomic/rmw/add/i64_atomic_rmw_add.wat

@@ -12,17 +12,17 @@
 ;;       movq    0x18(%r11), %r11
 ;;       addq    $0x10, %r11
 ;;       cmpq    %rsp, %r11
-;;       ja      0x69
+;;       ja      0x67
 ;;   1c: movq    %rdi, %r14
 ;;       subq    $0x10, %rsp
 ;;       movq    %rdi, 8(%rsp)
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0x2a, %eax
 ;;       movl    $0, %ecx
-;;       andq    $7, %rcx
-;;       cmpq    $0, %rcx
-;;       jne     0x6b
-;;   4a: movl    $0, %ecx
+;;       andl    $7, %ecx
+;;       cmpl    $0, %ecx
+;;       jne     0x69
+;;   48: movl    $0, %ecx
 ;;       movq    0x30(%r14), %r11
 ;;       movq    (%r11), %rdx
 ;;       movl    %ecx, %ecx
@@ -31,5 +31,5 @@
 ;;       addq    $0x10, %rsp
 ;;       popq    %rbp
 ;;       retq
+;;   67: ud2
 ;;   69: ud2
-;;   6b: ud2

tests/disas/winch/x64/atomic/rmw/and/i32_atomic_rmw16_andu.wat

@@ -19,8 +19,8 @@
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0x2a, %eax
 ;;       movl    $0, %ecx
-;;       andw    $1, %cx
-;;       cmpw    $0, %cx
+;;       andl    $1, %ecx
+;;       cmpl    $0, %ecx
 ;;       jne     0x91
 ;;   48: movl    $0, %ecx
 ;;       movq    0x30(%r14), %r11

tests/disas/winch/x64/atomic/rmw/and/i64_atomic_rmw16_andu.wat

@@ -19,8 +19,8 @@
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0x2a, %eax
 ;;       movl    $0, %ecx
-;;       andw    $1, %cx
-;;       cmpw    $0, %cx
+;;       andl    $1, %ecx
+;;       cmpl    $0, %ecx
 ;;       jne     0x80
 ;;   48: movl    $0, %ecx
 ;;       movq    0x30(%r14), %r11

tests/disas/winch/x64/atomic/rmw/and/i64_atomic_rmw_and.wat

@@ -12,17 +12,17 @@
 ;;       movq    0x18(%r11), %r11
 ;;       addq    $0x18, %r11
 ;;       cmpq    %rsp, %r11
-;;       ja      0x7a
+;;       ja      0x78
 ;;   1c: movq    %rdi, %r14
 ;;       subq    $0x10, %rsp
 ;;       movq    %rdi, 8(%rsp)
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0x2a, %eax
 ;;       movl    $0, %ecx
-;;       andq    $7, %rcx
-;;       cmpq    $0, %rcx
-;;       jne     0x7c
-;;   4a: movl    $0, %ecx
+;;       andl    $7, %ecx
+;;       cmpl    $0, %ecx
+;;       jne     0x7a
+;;   48: movl    $0, %ecx
 ;;       movq    0x30(%r14), %r11
 ;;       movq    (%r11), %rdx
 ;;       movl    %ecx, %ecx
@@ -33,9 +33,9 @@
 ;;       movq    %rax, %r11
 ;;       andq    %rcx, %r11
 ;;       lock cmpxchgq %r11, (%rdx)
-;;       jne     0x60
-;;   71: addq    $0x10, %rsp
+;;       jne     0x5e
+;;   6f: addq    $0x10, %rsp
 ;;       popq    %rbp
 ;;       retq
+;;   78: ud2
 ;;   7a: ud2
-;;   7c: ud2