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examples.txt
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# Example simulations
# Direct-mapped (LRU; 1 word per block)
cache-simulator --cache-size 4 --num-blocks-per-set 1 --num-words-per-block 1 --word-addrs 0 8 0 6 8
WordAddr BinAddr Tag Index Offset Hit/Miss
--------------------------------------------------------------------------------
0 0000 00 00 n/a miss
8 1000 10 00 n/a miss
0 0000 00 00 n/a miss
6 0110 01 10 n/a miss
8 1000 10 00 n/a miss
Cache
--------------------------------------------------------------------------------
00 01 10 11
--------------------------------------------------------------------------------
8 6
# 2-way set associative (LRU; 1 word per block)
cache-simulator --cache-size 4 --num-blocks-per-set 2 --num-words-per-block 1 --word-addrs 0 8 0 6 8
WordAddr BinAddr Tag Index Offset Hit/Miss
--------------------------------------------------------------------------------
0 0000 000 0 n/a miss
8 1000 100 0 n/a miss
0 0000 000 0 n/a HIT
6 0110 011 0 n/a miss
8 1000 100 0 n/a miss
Cache
--------------------------------------------------------------------------------
0 1
--------------------------------------------------------------------------------
8 6
# Fully associative (LRU; 1 word per block)
cache-simulator --cache-size 4 --num-blocks-per-set 4 --num-words-per-block 1 --word-addrs 0 8 0 6 8
WordAddr BinAddr Tag Index Offset Hit/Miss
--------------------------------------------------------------------------------
0 0000 0000 n/a n/a miss
8 1000 1000 n/a n/a miss
0 0000 0000 n/a n/a HIT
6 0110 0110 n/a n/a miss
8 1000 1000 n/a n/a HIT
Cache
--------------------------------------------------------------------------------
0 8 6
# Direct-mapped (LRU; 2 words per block)
cache-simulator --cache-size 16 --num-blocks-per-set 1 --num-words-per-block 2 --word-addrs 3 180 43 2 191 88 190 14 181 44 186 253
WordAddr BinAddr Tag Index Offset Hit/Miss
--------------------------------------------------------------------------------
3 0000 0011 0000 001 1 miss
180 1011 0100 1011 010 0 miss
43 0010 1011 0010 101 1 miss
2 0000 0010 0000 001 0 HIT
191 1011 1111 1011 111 1 miss
88 0101 1000 0101 100 0 miss
190 1011 1110 1011 111 0 HIT
14 0000 1110 0000 111 0 miss
181 1011 0101 1011 010 1 HIT
44 0010 1100 0010 110 0 miss
186 1011 1010 1011 101 0 miss
253 1111 1101 1111 110 1 miss
Cache
--------------------------------------------------------------------------------
000 001 010 011 100 101 110 111
--------------------------------------------------------------------------------
2,3 180,181 88,89 186,187 252,253 14,15
# 3-way set associative (LRU; 2 words per block)
cache-simulator --cache-size 24 --num-blocks-per-set 3 --num-words-per-block 2 --word-addrs 3 180 43 2 191 88 190 14 181 44 186 253
WordAddr BinAddr Tag Index Offset Hit/Miss
--------------------------------------------------------------------------------
3 0000 0011 00000 01 1 miss
180 1011 0100 10110 10 0 miss
43 0010 1011 00101 01 1 miss
2 0000 0010 00000 01 0 HIT
191 1011 1111 10111 11 1 miss
88 0101 1000 01011 00 0 miss
190 1011 1110 10111 11 0 HIT
14 0000 1110 00001 11 0 miss
181 1011 0101 10110 10 1 HIT
44 0010 1100 00101 10 0 miss
186 1011 1010 10111 01 0 miss
253 1111 1101 11111 10 1 miss
Cache
--------------------------------------------------------------------------------
00 01 10 11
--------------------------------------------------------------------------------
88,89 2,3 42,43 186,187 180,181 44,45 252,253 190,191 14,15
# Fully associative (LRU; 2 words per block)
cache-simulator --cache-size 8 --num-blocks-per-set 4 --num-words-per-block 2 --word-addrs 3 180 43 2 191 88 190 14 181 44 186 253
WordAddr BinAddr Tag Index Offset Hit/Miss
--------------------------------------------------------------------------------
3 0000 0011 000 0001 n/a 1 miss
180 1011 0100 101 1010 n/a 0 miss
43 0010 1011 001 0101 n/a 1 miss
2 0000 0010 000 0001 n/a 0 HIT
191 1011 1111 101 1111 n/a 1 miss
88 0101 1000 010 1100 n/a 0 miss
190 1011 1110 101 1111 n/a 0 HIT
14 0000 1110 000 0111 n/a 0 miss
181 1011 0101 101 1010 n/a 1 miss
44 0010 1100 001 0110 n/a 0 miss
186 1011 1010 101 1101 n/a 0 miss
253 1111 1101 111 1110 n/a 1 miss
Cache
--------------------------------------------------------------------------------
180,181 44,45 252,253 186,187
# Fully associative (MRU; 2 words per block)
cache-simulator --cache-size 8 --num-blocks-per-set 4 --num-words-per-block 2 --replacement-policy mru --word-addrs 3 180 43 2 191 88 190 14 181 44 186 253
WordAddr BinAddr Tag Index Offset Hit/Miss
--------------------------------------------------------------------------------
3 0000 0011 000 0001 n/a 1 miss
180 1011 0100 101 1010 n/a 0 miss
43 0010 1011 001 0101 n/a 1 miss
2 0000 0010 000 0001 n/a 0 HIT
191 1011 1111 101 1111 n/a 1 miss
88 0101 1000 010 1100 n/a 0 miss
190 1011 1110 101 1111 n/a 0 miss
14 0000 1110 000 0111 n/a 0 miss
181 1011 0101 101 1010 n/a 1 HIT
44 0010 1100 001 0110 n/a 0 miss
186 1011 1010 101 1101 n/a 0 miss
253 1111 1101 111 1110 n/a 1 miss
Cache
--------------------------------------------------------------------------------
2,3 252,253 42,43 14,15