Apply review suggestion for issue 1037 reference

Add explicit link to GitHub issue 1037 in the MCI
reset mux glitch paragraph per review feedback.
Reword integrator responsibility guidance.

Resolves #1094

Author: ekarabu

docs/CaliptraSSIntegrationSpecification.md

@@ -1759,7 +1759,7 @@ The two regions have different access protection. The size of the regions is dyn
 
     The integrator should use `SOC_DFT_EN` to gate entry into scan mode (e.g., to enable scan chain access), but must **not** rely on `SOC_DFT_EN` or any other Caliptra Subsystem output remaining stable once scan mode is active. The SoC's DFT architecture is responsible for ensuring that its DFT control signals are driven in a stable manner during scan. For example, if `SOC_DFT_EN` is used to gate IJTAG or other DFT access, the SoC should latch or otherwise stabilize the signal before entering scan mode.
 
-    Additionally, the MCI reset mux logic that selects between normal and scan-mode reset paths uses standard RTL assign statements. Depending on the synthesis tool and target technology, these may not synthesize into glitch-free mux cells, potentially causing glitches on reset lines during `scan_mode` transitions. Integrators should verify their gate-level netlist and, if necessary, ensure glitch-free mux behavior on these reset paths through synthesis constraints or cell replacements.
+    Additionally, the MCI reset mux logic that selects between normal and scan-mode reset paths uses standard RTL assign statements. Depending on the synthesis tool and target technology, these may not synthesize into glitch-free mux cells, potentially causing glitches on reset lines during `scan_mode` transitions, as reported in [GitHub issue 1037](https://github.com/chipsalliance/caliptra-ss/issues/1037). Integrators should analyze their gate-level netlist to confirm logic safety against glitches when entering scan_mode. Integrators are responsible for tooling adjustments to produce glitch-free mux behavior on these reset paths.
 
   - **Integrator RTL modification requirements**