chipsalliance
diff --git a/‎.github/workflow_metadata/pr_hash‎
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diff --git a/‎.github/workflow_metadata/pr_timestamp‎
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diff --git a/‎src/integration/stimulus/L0_Promote_caliptra_ss_top_tb_regression.yml‎
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diff --git a/‎src/integration/stimulus/L1_Nightly_Random_caliptra_ss_top_tb_regression.yml‎
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diff --git a/‎src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv‎
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diff --git a/‎src/integration/test_suites/caliptra_ss_mcu_sram_to_sha/caliptra_ss_mcu_sram_to_sha.c‎
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diff --git a/‎src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.c‎
Lines changed: 132 additions & 41 deletions b/‎src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.c‎
Lines changed: 132 additions & 41 deletions
diff --git a/‎src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.h‎
Lines changed: 36 additions & 6 deletions b/‎src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.h‎
Lines changed: 36 additions & 6 deletions
@@ -1 +1 @@
-29ff3ff273ae018898f753bc3bee8b36382f407b7cbd87dba40a554e3d1f54097e15203a0f0c3af562ffc8ec659b7d4c
+7fcfd012bfb833fef21486eca87c4010e32a45dbcd5e2813c99564e65f5b85924dac101aeb484f95ac3ab58565c4a4b6
@@ -1 +1 @@
-1743783955
+1743803703
@@ -26,6 +26,8 @@ contents:
         - ../test_suites/caliptra_ss_fuse_ctrl_axi_id/caliptra_ss_fuse_ctrl_axi_id.yml
         - ../test_suites/caliptra_ss_fuse_ctrl_zeroization/caliptra_ss_fuse_ctrl_zeroization.yml
         - ../test_suites/caliptra_ss_fuse_ctrl_unexpected_reset/caliptra_ss_fuse_ctrl_unexpected_reset.yml
+        - ../test_suites/smoke_test_mcu_sram_byte_write/smoke_test_mcu_sram_byte_write.yml
+        - ../test_suites/smoke_test_mcu_sram_protected_region/smoke_test_mcu_sram_protected_region.yml
         - ../test_suites/smoke_test_mcu_mbox_valid_user/smoke_test_mcu_mbox0_valid_user.yml
         - ../test_suites/smoke_test_mcu_mbox_write_user_lock/smoke_test_mcu_mbox0_write_user_lock.yml
         - ../test_suites/smoke_test_mcu_mbox_usr_lock_out_zero/smoke_test_mcu_mbox0_usr_lock_out_zero.yml
 
@@ -6,7 +6,7 @@ contents:
       tags: ["L1", "caliptra_ss_top_tb", "Random", "Nightly"]
       path: ""
       weight: 100
-      generations: 50
+      generations: 60
       formats:
         generate: "reseed {template}.yml -seed {seed}"
         path: "{template_basename}__{seed}.yml"
@@ -15,4 +15,5 @@ contents:
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_RMA/smoke_test_lcc_RMA: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_test_unlocked0_prov/caliptra_ss_fuse_ctrl_test_unlocked0_prov: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_unexpected_reset/caliptra_ss_fuse_ctrl_unexpected_reset: { weight: 100 }
+        $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_sram_protected_region/smoke_test_mcu_sram_protected_region: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_mcu_sram_to_sha/caliptra_ss_mcu_sram_to_sha: { weight: 100 }
@@ -29,6 +29,8 @@ $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_writeblank/c
 $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_axi_id/caliptra_ss_fuse_ctrl_axi_id                                 , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_zeroization/caliptra_ss_fuse_ctrl_zeroization                       , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_unexpected_reset/caliptra_ss_fuse_ctrl_unexpected_reset             , Random         , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
+$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_sram_byte_write/smoke_test_mcu_sram_byte_write                             , Directed       , None          , L0  , None, caliptra_ss_top_tb, Promote        , None     , 100
+$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_sram_protected_region/smoke_test_mcu_sram_protected_region                 , Random         , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_valid_user/smoke_test_mcu_mbox0_valid_user                            , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_valid_user/smoke_test_mcu_mbox1_valid_user                            , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_write_user_lock/smoke_test_mcu_mbox0_write_user_lock                  , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
 
@@ -45,7 +45,7 @@ void main (void) {
 
     VPRINTF(LOW, "MCU: Caliptra bringup\n")
 
-    mcu_cptra_fuse_init();
+    mcu_cptra_init_d();
 
     //Halt the core to wait for Caliptra to finish the test
     __asm__ volatile ("csrwi    %0, %1" \
 
@@ -50,21 +50,50 @@ void reset_fc_lcc_rtl(void) {
     mcu_sleep(160);
 }
 
-void mcu_mci_boot_go() {
- 
-    // Configure EXEC Region before initializing Caliptra
-    lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_SRAM_EXEC_REGION_SIZE , 100);
-    VPRINTF(LOW, "MCU: Configure EXEC REGION Size\n");
+void write_read_check(uintptr_t rdptr, uint32_t data){
+    VPRINTF(LOW, "write_read_check: Address: 0x%x -- Data: 0x%x\n", rdptr, data);
+
+    lsu_write_32(rdptr, data);
+
+    read_check(rdptr, data);
 
+}
 
+uintptr_t get_random_address(uint32_t rnd, uintptr_t start_address, uintptr_t end_address) {
+    // Return address that is DWORD aligned
+    uintptr_t range = end_address - start_address + 1;
+    uintptr_t offset = rnd % range;
+    uintptr_t address = (start_address + offset) & ~3;
+    return address;
+}
+
+void read_check(uintptr_t rdptr, uint32_t expected_rddata){
+    uint32_t data;
+    data = lsu_read_32(rdptr);
+    VPRINTF(LOW, "read_check: Address: 0x%x -- Expected: 0x%x Actual: 0x%x\n", rdptr, expected_rddata, data);
+    if (expected_rddata != data) {
+        VPRINTF(FATAL, "MCU: FATAL - read_check: Data mismatch at address: 0x%x -- Expected: 0x%x Actual: 0x%x\n", rdptr, expected_rddata, data);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+void mcu_set_fw_sram_exec_region_size(uint32_t size) {
+    VPRINTF(LOW, "MCU: Configure EXEC REGION Size 0x%x\n", size);
+    lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_SRAM_EXEC_REGION_SIZE , size);
+}
+
+
+void mcu_set_cptra_dma_axi_user(uint32_t value) {
+    VPRINTF(LOW, "MCU: Configure CPTRA DMA AXI USER 0x%x\n", value);
+    lsu_write_32(SOC_SOC_IFC_REG_SS_CALIPTRA_DMA_AXI_USER, value);
+}
+
+void mcu_mci_boot_go() {
     // writing SOC_MCI_TOP_MCI_REG_CPTRA_BOOT_GO register of MCI for CPTRA Boot FSM to bring Caliptra out of reset
     uint32_t cptra_boot_go;
     VPRINTF(LOW, "MCU: Writing MCI SOC_MCI_TOP_MCI_REG_CPTRA_BOOT_GO\n");
     lsu_write_32(SOC_MCI_TOP_MCI_REG_CPTRA_BOOT_GO, 1);
-    
-    VPRINTF(LOW, "MCU: Reading SOC_MCI_TOP_MCI_REG_CPTRA_BOOT_GO");
-    cptra_boot_go = lsu_read_32(SOC_MCI_TOP_MCI_REG_CPTRA_BOOT_GO);
-    VPRINTF(LOW, "MCU: SOC_MCI_TOP_MCI_REG_CPTRA_BOOT_GO set to %x\n", cptra_boot_go);
 }
 
 void mcu_mci_poll_exec_lock() {
@@ -117,52 +146,113 @@ void mcu_cptra_advance_brkpoint() {
 
 }
 
-void mcu_cptra_fuse_init_axi_user(uint32_t cptra_axi_user){
-    ////////////////////////////////////
-    // Fuse and Boot Bringup
+void mcu_cptra_user_init() {
+    // MBOX: Setup valid AXI USER
+    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0, 0x1); // FIXME this should come from a param for LSU AxUSER
+//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1, 1);
+//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2, 2);
+//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3, 3);
+    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0, SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK);
+//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1, SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK);
+//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2, SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK);
+//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3, SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK);
+    VPRINTF(LOW, "MCU: Configured MBOX Valid AXI USER\n");
+
+}
+
+void mcu_cptra_init(mcu_cptra_init_args args) {
+    // DO NOT CALL DIRECTLY. USE THE mcu_cptra_init_d MACRO TO CALL THE FUNCTION
+    
+    // 4 MAIN OPTIONS:
     //
-    mcu_cptra_wait_for_fuses();
+    // 1. Always disabled unless a new value is specified:
+    //    - Add a boolean cfg_<feature>.
+    //    - Add a <type> <feature_value>.
+    //    - Skip configuration unless cfg_<feature> is set, then set the <feature_value>.
+    //    - Use for features that most tests don't care about and will have a set value.
+    //
+    // 2. Always disabled unless enabled:
+    //    - Add a boolean cfg_enable_<feature>.
+    //    - Skip configuration unless cfg_enable_<feature> is set, then enable the feature.
+    //    - Use for features that most tests don't care about and don't have an actual 
+    //      value but when enabled will initiate a configuration within the design.
+    //
+    // 3. Always enabled unless specified:
+    //    - Add a cfg_skip_<feature>.
+    //    - Always program the register unless the skip is set.
+    //    - Use when most tests want the feature
+    //    - Use for features that are either DO or SKIP.
+    //
+    // 4. Always enabled unless overridden:
+    //    - Add a cfg_override_<feature>.
+    //    - Add a <feature_value>.
+    //    - Use when most tests whant the feature.
+    //    - Always configure to a default value. If cfg_override_<feature> is set, 
+    //      write the <feature_value> into the register.
 
-    lsu_write_32(SOC_SOC_IFC_REG_SS_CALIPTRA_DMA_AXI_USER, cptra_axi_user);
+    
 
-    // Initialize fuses
-    // TODO set actual fuse values
-    mcu_cptra_set_fuse_done();
+    VPRINTF(LOW, "MCU: INIT CONFIGURING START\n");
+    
+    /////////////////////////////////
+    // MCU CONFIGURATION
+    /////////////////////////////////
+    if (args.cfg_mcu_fw_sram_exec_reg_size) {
+        VPRINTF(LOW, "MCU: args.mcu_fw_sram_exec_reg_size 0x%x\n", args.mcu_fw_sram_exec_reg_size);
+        mcu_set_fw_sram_exec_region_size(args.mcu_fw_sram_exec_reg_size); 
+    }
 
-    mcu_cptra_advance_brkpoint();
-}
+    if (args.cfg_mcu_mbox0_valid_user) {
+        mcu_mbox_configure_valid_axi(0, args.mcu_mbox0_valid_user);
+    }
 
-void mcu_cptra_fuse_init() {
-    enum boot_fsm_state_e boot_fsm_ps;
+    if (args.cfg_mcu_mbox1_valid_user) {
+        mcu_mbox_configure_valid_axi(1, args.mcu_mbox1_valid_user);
+    }
+
+    /////////////////////////////////
+    // BRING CPTRA OUT OF RESET
+    /////////////////////////////////
+    mcu_mci_boot_go();
 
-    ////////////////////////////////////
-    // Fuse and Boot Bringup
-    //
     mcu_cptra_wait_for_fuses();
 
+    /////////////////////////////////
+    // CPTRA FUSE CONFIGURATION
+    /////////////////////////////////
+    if (args.cfg_cptra_dma_axi_user){
+        mcu_set_cptra_dma_axi_user(args.cptra_dma_axi_user);
+    }
 
-    // Initialize fuses
-    // TODO set actual fuse values
-    mcu_cptra_set_fuse_done();
+    if (args.cfg_enable_cptra_mbox_user_init){
+        mcu_cptra_user_init();
+    }
 
-    mcu_cptra_advance_brkpoint();
+    /////////////////////////////////
+    // CPTRA LOCK FUSE CONFIGURATION
+    /////////////////////////////////
+    if (!args.cfg_skip_set_fuse_done) {
+        mcu_cptra_set_fuse_done();
+    }
+    else{
+        VPRINTF(LOW, "MCU: INIT CONFIGURING: Skip Set fuse done\n");
+    }
 
-}
+    /////////////////////////////////
+    // CPTRA ENSURE BREAKPOINT SET  
+    /////////////////////////////////
+    if (!args.cfg_skip_set_fuse_done) {
+        mcu_cptra_advance_brkpoint();
+    }
+    else{
+        VPRINTF(LOW, "MCU: INIT CONFIGURING: Skip advance CPTRA advance breakpoint\n");
+    }
 
-void mcu_cptra_user_init() {
-    // MBOX: Setup valid AXI USER
-    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0, 0x1); // FIXME this should come from a param for LSU AxUSER
-//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1, 1);
-//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2, 2);
-//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3, 3);
-    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0, SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK);
-//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1, SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK);
-//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2, SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK);
-//    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3, SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK);
-    VPRINTF(LOW, "MCU: Configured MBOX Valid AXI USER\n");
 
+    VPRINTF(LOW, "MCU: INIT CONFIGURING END\n");
 }
 
+
 void mcu_mbox_clear_lock_out_of_reset(uint32_t mbox_num) {
     // MBOX: Write DLEN  (normally would be max SRAM size but using smaller size for test run time)
     lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_DLEN + MCU_MBOX_NUM_STRIDE*mbox_num, 32);
@@ -227,6 +317,7 @@ void mcu_mbox_clear_mbox_cmd_avail_interrupt(uint32_t mbox_num) {
 
 void mcu_mbox_configure_valid_axi(uint32_t mbox_num, uint32_t *axi_user_id) {
 
+    VPRINTF(LOW, "MCU: Configuring Valid AXI USERs in Mbox%x:  0 - 0x%x; 1 - 0x%x; 2 - 0x%x; 3 - 0x%x; 4 - 0x%x;\n", mbox_num, axi_user_id[0], axi_user_id[1], axi_user_id[2], axi_user_id[3], axi_user_id[4]);
     lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_VALID_AXI_USER_0 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, axi_user_id[0]);
     lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_VALID_AXI_USER_1 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, axi_user_id[1]);
     lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_VALID_AXI_USER_2 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, axi_user_id[2]);
@@ -238,8 +329,8 @@ void mcu_mbox_configure_valid_axi(uint32_t mbox_num, uint32_t *axi_user_id) {
     lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_2 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, MCI_REG_MBOX0_AXI_USER_LOCK_2_LOCK_MASK);
     lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_3 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, MCI_REG_MBOX0_AXI_USER_LOCK_3_LOCK_MASK);
     lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_4 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, MCI_REG_MBOX0_AXI_USER_LOCK_4_LOCK_MASK);
+    VPRINTF(LOW, "MCU: DONE Configuring Valid AXI USERs in Mbox%x\n", mbox_num);
 
-    VPRINTF(LOW, "MCU: Configured Valid AXI USERs in Mbox%x:  0 - 0x%x; 1 - 0x%x; 2 - 0x%x; 3 - 0x%x; 4 - 0x%x;\n", mbox_num, axi_user_id[0], axi_user_id[1], axi_user_id[2], axi_user_id[3], axi_user_id[4]);
 }
 
 bool mcu_mbox_acquire_lock(uint32_t mbox_num, uint32_t attempt_count) {
 
@@ -22,6 +22,34 @@
 #include <stdbool.h>
 
 extern uint32_t state;
+
+typedef struct {
+    // FW_SRAM_EXEC_REGION_SIZE
+    bool cfg_mcu_fw_sram_exec_reg_size;
+    uint32_t mcu_fw_sram_exec_reg_size;
+
+    // CPTRA DMA AXI USER 
+    bool cfg_cptra_dma_axi_user;
+    uint32_t cptra_dma_axi_user;
+    
+    // MCU MBOX VALID USER 
+    bool cfg_mcu_mbox0_valid_user;
+    uint32_t *mcu_mbox0_valid_user;
+    bool cfg_mcu_mbox1_valid_user;
+    uint32_t *mcu_mbox1_valid_user;
+
+    // SOC_IFC MBOX
+    bool cfg_enable_cptra_mbox_user_init;
+
+    // FUSE DONE
+    bool cfg_skip_set_fuse_done;
+
+} mcu_cptra_init_args;
+// MAIN CPTRA INIT FUNCTION EVERYONE SHOULD USER 
+// TO LOAD FUSES!!!
+void mcu_cptra_init(mcu_cptra_init_args args);
+#define mcu_cptra_init_d(...) mcu_cptra_init((mcu_cptra_init_args){__VA_ARGS__});
+
 uint32_t xorshift32(void);
 
 // Bitfield indicating which MCU Mboxes are valid for the given test
@@ -38,11 +66,12 @@ void reset_fc_lcc_rtl(void);
 void mcu_cptra_wait_for_fuses() ;
 void mcu_cptra_set_fuse_done() ;
 void mcu_cptra_advance_brkpoint() ;
-void mcu_cptra_fuse_init_axi_user(uint32_t cptra_axi_user);
+void mcu_set_fw_sram_exec_region_size(uint32_t size);
+void mcu_set_cptra_dma_axi_user(uint32_t value);
 void mcu_mci_boot_go();
+void read_check(uintptr_t rdptr, uint32_t expected_rddata);
 void mcu_mci_poll_exec_lock();
 void mcu_mci_req_reset();
-void mcu_cptra_fuse_init();
 void mcu_cptra_user_init();
 void mcu_cptra_poll_mb_ready();
 void mcu_cptra_mbox_cmd();
@@ -59,12 +88,11 @@ void mcu_mbox_configure_valid_axi(uint32_t mbox_num, uint32_t *axi_user_id);
 bool mcu_mbox_acquire_lock(uint32_t mbox_num, uint32_t attempt_count);
 bool mcu_mbox_wait_for_user_to_be_mcu(uint32_t mbox_num, uint32_t attempt_count);
 void mcu_mbox_clear_mbox_cmd_avail_interrupt(uint32_t mbox_num);
+void write_read_check(uintptr_t rdptr, uint32_t data);
+uintptr_t get_random_address(uint32_t rnd, uintptr_t start_address, uintptr_t end_address);
 void mcu_mbox_clear_execute(uint32_t mbox_num);
 
 
-#define TB_CMD_SHA_VECTOR_TO_MCU_SRAM   0x80
-
-
 #define TB_CMD_SHA_VECTOR_TO_MCU_SRAM   0x80
 
 #define FC_LCC_CMD_OFFSET 0xB0
@@ -79,11 +107,13 @@ void mcu_mbox_clear_execute(uint32_t mbox_num);
 #define CMD_LC_FORCE_RMA_SCRAP_PPD      FC_LCC_CMD_OFFSET + 0x0a
 #define CMD_FC_TRIGGER_ESCALATION       FC_LCC_CMD_OFFSET + 0x0b
 
+#define TB_CMD_DISABLE_MCU_SRAM_PROT_ASSERTS 0xC0
+
+
 #define TB_CMD_DISABLE_INJECT_ECC_ERROR     0xe0
 #define TB_CMD_INJECT_ECC_ERROR_SINGLE_DCCM 0xe2
 #define TB_CMD_INJECT_ECC_ERROR_DOUBLE_DCCM 0xe3
 
-
 #define MCU_MBOX_NUM_STRIDE             (SOC_MCI_TOP_MCU_MBOX1_CSR_BASE_ADDR - SOC_MCI_TOP_MCU_MBOX0_CSR_BASE_ADDR)
 #define MCU_MBOX_AXI_CFG_STRIDE         (SOC_MCI_TOP_MCI_REG_MBOX1_AXI_USER_LOCK_0 - SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_0)
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	`1`	`+7fcfd012bfb833fef21486eca87c4010e32a45dbcd5e2813c99564e65f5b85924dac101aeb484f95ac3ab58565c4a4b6`