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ekarabuekarabu
committed
added manuf to prod
1 parent cce16b1 commit 544fa42

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7 files changed

+77
-15
lines changed

7 files changed

+77
-15
lines changed

‎src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ module caliptra_ss_lc_ctrl
3535
// Life cycle controller clock
3636
input clk_i,
3737
input rst_ni,
38-
input RMA_strap,
38+
input Allow_RMA_on_PPD,
3939
// Clock for KMAC interface
4040
// input clk_kmac_i,
4141
// input rst_kmac_ni,
@@ -875,7 +875,7 @@ module caliptra_ss_lc_ctrl
875875
) u_caliptra_ss_lc_ctrl_fsm (
876876
.clk_i,
877877
.rst_ni,
878-
.RMA_strap,
878+
.Allow_RMA_on_PPD,
879879
.init_req_i ( caliptra_ss_lc_init ),
880880
.init_done_o ( caliptra_ss_lc_done_d ),
881881
.idle_o ( caliptra_ss_lc_idle_d ),

‎src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_fsm.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ module caliptra_ss_lc_ctrl_fsm
2323
// need the clock and reset for the assertions.
2424
input clk_i,
2525
input rst_ni,
26-
input RMA_strap,
26+
input Allow_RMA_on_PPD,
2727
// Initialization request from power manager.
2828
input init_req_i,
2929
output logic init_done_o,
@@ -464,7 +464,7 @@ module caliptra_ss_lc_ctrl_fsm
464464
// Flash RMA state. Note that we check the flash response again
465465
// two times later below.
466466
FlashRmaSt: begin
467-
if (trans_target_i == {DecLcStateNumRep{DecLcStRma}} && RMA_strap) begin
467+
if (trans_target_i == {DecLcStateNumRep{DecLcStRma}} && Allow_RMA_on_PPD) begin
468468
caliptra_ss_lc_flash_rma_req = On;
469469
if (caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_flash_rma_ack_buf[0])) begin
470470
fsm_state_d = TokenCheck0St;
@@ -491,7 +491,7 @@ module caliptra_ss_lc_ctrl_fsm
491491
(trans_target_i == {DecLcStateNumRep{DecLcStRma}} &&
492492
caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_flash_rma_req_o) &&
493493
caliptra_ss_lc_tx_test_true_strict(caliptra_ss_lc_flash_rma_ack_buf[1])
494-
&& RMA_strap)) begin
494+
&& Allow_RMA_on_PPD)) begin
495495
if (hashed_token_i == hashed_token_mux &&
496496
!token_hash_err_i &&
497497
&hashed_token_valid_mux) begin
@@ -532,7 +532,7 @@ module caliptra_ss_lc_ctrl_fsm
532532
(caliptra_ss_lc_flash_rma_req_o != Off || caliptra_ss_lc_flash_rma_ack_buf[2] != Off)) ||
533533
(trans_target_i == {DecLcStateNumRep{DecLcStRma}} &&
534534
(caliptra_ss_lc_flash_rma_req_o != On || caliptra_ss_lc_flash_rma_ack_buf[2] != On)
535-
&& RMA_strap)) begin
535+
&& Allow_RMA_on_PPD)) begin
536536
fsm_state_d = PostTransSt;
537537
flash_rma_error_o = 1'b1;
538538
end else if (otp_prog_ack_i) begin

‎src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_pkg.sv‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -334,7 +334,15 @@ package caliptra_ss_lc_ctrl_pkg;
334334
// DEV
335335
ZeroTokenIdx, // -> SCRAP
336336
RmaTokenIdx, // -> RMA
337-
{19{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END
337+
338+
// {19{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV, PROD, PROD_END
339+
340+
// ============== This is how we enable from DEV to PROD ==============================
341+
InvalidTokenIdx, // -> PROD_END
342+
TestExitTokenIdx, // -> PROD
343+
{17{InvalidTokenIdx}}, // -> TEST_LOCKED0-6, TEST_UNLOCKED0-7, DEV
344+
// ====================================================================================
345+
338346
// TEST_UNLOCKED0-7, TEST_LOCKED0-6
339347
`TEST_UNLOCKED(7),
340348
`TEST_LOCKED(6),

‎src/caliptra_ss_lc_ctrl/rtl/caliptra_ss_lc_ctrl_state_pkg.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -303,8 +303,8 @@ package caliptra_ss_lc_ctrl_state_pkg;
303303
LcStTestLocked6 = {A19, A18, A17, A16, A15, A14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
304304
LcStTestUnlocked7 = {A19, A18, A17, A16, A15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
305305
LcStDev = {A19, A18, A17, A16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
306-
LcStProd = {A19, A18, A17, B16, A15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
307-
LcStProdEnd = {A19, A18, B17, A16, A15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
306+
LcStProd = {A19, A18, A17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
307+
LcStProdEnd = {A19, A18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
308308
LcStRma = {B19, B18, A17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
309309
LcStScrap = {B19, B18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}
310310
} caliptra_ss_lc_state_e;

‎src/integration/test_suites/caliptra_ss_lc_ctrl_st_trans/caliptra_ss_lc_ctrl_st_trans.c‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,56 @@ void TESTUNLOCK0_to_DEV(){
239239

240240
}
241241

242+
void TESTUNLOCK0_to_PROD(){
243+
uint32_t reg_value;
244+
uint32_t status_val;
245+
uint32_t loop_ctrl;
246+
247+
uint32_t next_lc_state = 17; // PROD
248+
uint32_t next_lc_state_5bit = next_lc_state & 0x1F; // Extract 5-bit value (DecLcStateWidth = 5)
249+
uint32_t targeted_state_5 =
250+
(next_lc_state_5bit << 25) |
251+
(next_lc_state_5bit << 20) |
252+
(next_lc_state_5bit << 15) |
253+
(next_lc_state_5bit << 10) |
254+
(next_lc_state_5bit << 5) |
255+
next_lc_state_5bit;
256+
257+
sw_transition_req(targeted_state_5, 0x0, 0x0, 0x0, 0x0, 1); //DEV, tokenmsb, tokenlsb, conditional
258+
reg_value = lsu_read_32(LC_CTRL_HW_REVISION0_OFFSET); // Reset the lcc and its bfm
259+
VPRINTF(LOW, "LC_CTRL: CALIPTRA_SS_LC_CTRL is under reset!\n");
260+
for (uint8_t ii = 0; ii < 160; ii++) {
261+
__asm__ volatile ("nop"); // Sleep loop as "nop"
262+
}
263+
VPRINTF(LOW, "LC_CTRL: CALIPTRA_SS_LC_CTRL is in PROD state!\n");
264+
265+
}
266+
267+
void DEV_to_PROD(){
268+
uint32_t reg_value;
269+
uint32_t status_val;
270+
uint32_t loop_ctrl;
271+
272+
uint32_t next_lc_state = 17; // PROD
273+
uint32_t next_lc_state_5bit = next_lc_state & 0x1F; // Extract 5-bit value (DecLcStateWidth = 5)
274+
uint32_t targeted_state_5 =
275+
(next_lc_state_5bit << 25) |
276+
(next_lc_state_5bit << 20) |
277+
(next_lc_state_5bit << 15) |
278+
(next_lc_state_5bit << 10) |
279+
(next_lc_state_5bit << 5) |
280+
next_lc_state_5bit;
281+
282+
sw_transition_req(targeted_state_5, 0x0, 0x0, 0x0, 0x0, 1); //DEV, tokenmsb, tokenlsb, conditional
283+
reg_value = lsu_read_32(LC_CTRL_HW_REVISION0_OFFSET); // Reset the lcc and its bfm
284+
VPRINTF(LOW, "LC_CTRL: CALIPTRA_SS_LC_CTRL is under reset!\n");
285+
for (uint8_t ii = 0; ii < 160; ii++) {
286+
__asm__ volatile ("nop"); // Sleep loop as "nop"
287+
}
288+
VPRINTF(LOW, "LC_CTRL: CALIPTRA_SS_LC_CTRL is in PROD state!\n");
289+
290+
}
291+
242292
void DEV_to_RMA(){
243293
uint32_t reg_value;
244294
uint32_t status_val;
@@ -337,8 +387,12 @@ void main (void) {
337387

338388
RAW_to_TESTUNLOCK0();
339389

390+
// TESTUNLOCK0_to_PROD();
391+
340392
TESTUNLOCK0_to_DEV();
341393

394+
DEV_to_PROD();
395+
342396
DEV_to_RMA_without_STRAP();
343397

344398
DEV_to_RMA();

‎src/integration/testbench/caliptra_ss_lc_ctrl_bfm.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ module caliptra_ss_lc_ctrl_bfm
2727
input axi_struct_pkg::axi_rd_req_t caliptra_ss_lc_axi_rd_req,
2828
input axi_struct_pkg::axi_rd_rsp_t caliptra_ss_lc_axi_rd_rsp,
2929
output logic fake_reset,
30-
output logic RMA_strap,
30+
output logic Allow_RMA_on_PPD,
3131
output logic [7:0] from_bfm_caliptra_ss_lc_flash_rma_ack,
3232
input [3:0] to_bfm_caliptra_ss_lc_flash_rma_req_o,
3333

@@ -108,9 +108,9 @@ module caliptra_ss_lc_ctrl_bfm
108108
//-------------------------------------------------------------------
109109
always@(posedge clk or negedge reset_n) begin
110110
if (!reset_n)
111-
RMA_strap <= 0;
111+
Allow_RMA_on_PPD <= 0;
112112
else if (caliptra_ss_lc_axi_rd_req.arvalid && caliptra_ss_lc_axi_rd_rsp.arready && caliptra_ss_lc_axi_rd_req.araddr == 32'h7000_0048 && !power_and_reset_indication)
113-
RMA_strap <= ~RMA_strap;
113+
Allow_RMA_on_PPD <= ~Allow_RMA_on_PPD;
114114
end
115115
//-------------------------------------------------------------------
116116

‎src/integration/testbench/caliptra_ss_top.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2014,7 +2014,7 @@ module caliptra_ss_top
20142014
logic [7:0] from_bfm_caliptra_ss_lc_flash_rma_ack;
20152015
assign caliptra_ss_lc_flash_rma_ack_tb = from_bfm_caliptra_ss_lc_flash_rma_ack;
20162016

2017-
logic RMA_strap;
2017+
logic Allow_RMA_on_PPD;
20182018
logic fake_reset;
20192019

20202020
logic [3:0] to_bfm_caliptra_ss_lc_flash_rma_req_o;
@@ -2030,7 +2030,7 @@ module caliptra_ss_top
20302030
.caliptra_ss_lc_axi_rd_req(caliptra_ss_lc_axi_rd_req),
20312031
.caliptra_ss_lc_axi_rd_rsp(caliptra_ss_lc_axi_rd_rsp),
20322032
.fake_reset(fake_reset),
2033-
.RMA_strap(RMA_strap),
2033+
.Allow_RMA_on_PPD(Allow_RMA_on_PPD),
20342034
.from_bfm_caliptra_ss_lc_flash_rma_ack(from_bfm_caliptra_ss_lc_flash_rma_ack),
20352035
.to_bfm_caliptra_ss_lc_flash_rma_req_o(to_bfm_caliptra_ss_lc_flash_rma_req_o),
20362036

@@ -2087,7 +2087,7 @@ module caliptra_ss_top
20872087
) */ u_caliptra_ss_lc_ctrl (
20882088
.clk_i(core_clk),
20892089
.rst_ni(rst_l & fake_reset),
2090-
.RMA_strap(RMA_strap),
2090+
.Allow_RMA_on_PPD(Allow_RMA_on_PPD),
20912091
.axi_wr_req(caliptra_ss_lc_axi_wr_req),
20922092
.axi_wr_rsp(caliptra_ss_lc_axi_wr_rsp),
20932093
.axi_rd_req(caliptra_ss_lc_axi_rd_req),

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