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[RTL][VAL] Add SOC BFM, MCU SRAM Exec Test, and AXI USER RO registers to MCI (#263)
* Add SOC BFM, Add AXI USER RO registers in MCI, Add MCU SRAM Exec Test SOC BFM can generate AXI transactions, assert reset, randomize the AXI users. Use this BFM to create UVM like sequences. AXI USER registers are for MCU to read and use to configure its mailbox and other parts of the design. MCU SRAM execution region test are added to the L0 and L1 regressions. These utilize the new AXI BFM. * Fix build issue * Add missing file cptra_smoke_test_mcu_sram_byte_write.c * Fix regression failures * Dynamically assign MBOX user to MCU LSU * Fix failing regression * Fix syntax error * Add Vfile changes * Add Warm and Cold reset controls to TB services * Fix failing regression * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-soc-bfm' with updated timestamp and hash after successful run * Fix L1 regressions caliptra_ss_mcu_sram_to_sha randomizes the amount of data sent to MCU SRAM, so expanding the execution region size is required to pass all seeds. caliptra_ss_lcc_escalation never passed regressions. Removing test until passing. * Removed Makefile '-p' from smoke_test_mcu_mbox1_zeroize yaml * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-soc-bfm' with updated timestamp and hash after successful run
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‎.github/workflow_metadata/pr_hash‎

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‎.github/workflow_metadata/pr_timestamp‎

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‎src/integration/config/caliptra_ss_top_tb.vf‎

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+incdir+${CALIPTRA_SS_ROOT}/src/integration/coverage
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+incdir+${CALIPTRA_SS_ROOT}/src/integration/testbench
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+incdir+${CALIPTRA_SS_ROOT}/src/integration/testbench/sv_tests/ai3c
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+incdir+${CALIPTRA_SS_ROOT}/src/integration/testbench/sv_tests/mci
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+incdir+${CALIPTRA_SS_ROOT}/src/integration/testbench/sv_tests/common
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${CALIPTRA_SS_ROOT}/third_party/caliptra-rtl/src/integration/rtl/config_defines.svh
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${CALIPTRA_SS_ROOT}/third_party/caliptra-rtl/src/libs/rtl/caliptra_sva.svh
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${CALIPTRA_SS_ROOT}/third_party/caliptra-rtl/src/libs/rtl/caliptra_macros.svh
@@ -921,4 +923,6 @@ ${CALIPTRA_SS_ROOT}/src/integration/testbench/caliptra_ss_tb_cmd_list.svh
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${CALIPTRA_SS_ROOT}/src/integration/testbench/caliptra_ss_veer_sram_export.sv
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${CALIPTRA_SS_ROOT}/src/integration/testbench/fc_lcc_tb_services.sv
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${CALIPTRA_SS_ROOT}/src/integration/testbench/caliptra_ss_top_tb_services.sv
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${CALIPTRA_SS_ROOT}/src/integration/testbench/caliptra_ss_top_tb.sv
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${CALIPTRA_SS_ROOT}/src/integration/testbench/caliptra_ss_bfm_services_if.sv
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${CALIPTRA_SS_ROOT}/src/integration/testbench/caliptra_ss_top_tb.sv
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${CALIPTRA_SS_ROOT}/src/integration/testbench/caliptra_ss_top_tb_soc_bfm.sv

‎src/integration/config/compile.yml‎

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- $COMPILE_ROOT/vip
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- $COMPILE_ROOT/testbench
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- $COMPILE_ROOT/testbench/sv_tests/ai3c
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- $COMPILE_ROOT/testbench/sv_tests/mci
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- $COMPILE_ROOT/testbench/sv_tests/common
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files:
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# - $COMPILE_ROOT/../../../../chipsalliance/caliptra-rtl/src/axi/rtl/caliptra_axi_sram.sv
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- $COMPILE_ROOT/testbench/tb_top_pkg.sv
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- $COMPILE_ROOT/testbench/caliptra_ss_veer_sram_export.sv
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- $COMPILE_ROOT/testbench/fc_lcc_tb_services.sv
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- $COMPILE_ROOT/testbench/caliptra_ss_top_tb_services.sv
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- $COMPILE_ROOT/testbench/caliptra_ss_bfm_services_if.sv
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- $COMPILE_ROOT/testbench/caliptra_ss_top_tb.sv
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- $COMPILE_ROOT/testbench/caliptra_ss_top_tb_soc_bfm.sv
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tops: [caliptra_ss_top_tb, ai3c_tests_bench]
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sim:
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pre_exec: 'echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/src/ecc/tb/ecc_secp384r1.exe .

‎src/integration/rtl/soc_address_map.h‎

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‎src/integration/rtl/soc_address_map_defines.svh‎

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`define SOC_MCI_TOP_MCI_REG_FW_REV_ID_1 (32'h21000014)
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`define SOC_MCI_TOP_MCI_REG_HW_CONFIG0 (32'h21000018)
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`define SOC_MCI_TOP_MCI_REG_HW_CONFIG1 (32'h2100001c)
419-
`define SOC_MCI_TOP_MCI_REG_FW_FLOW_STATUS (32'h21000020)
420-
`define SOC_MCI_TOP_MCI_REG_HW_FLOW_STATUS (32'h21000024)
421-
`define SOC_MCI_TOP_MCI_REG_RESET_REASON (32'h21000028)
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`define SOC_MCI_TOP_MCI_REG_RESET_STATUS (32'h2100002c)
423-
`define SOC_MCI_TOP_MCI_REG_SECURITY_STATE (32'h21000030)
424-
`define SOC_MCI_TOP_MCI_REG_HW_ERROR_FATAL (32'h21000040)
425-
`define SOC_MCI_TOP_MCI_REG_AGG_ERROR_FATAL (32'h21000044)
426-
`define SOC_MCI_TOP_MCI_REG_HW_ERROR_NON_FATAL (32'h21000048)
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`define SOC_MCI_TOP_MCI_REG_AGG_ERROR_NON_FATAL (32'h2100004c)
428-
`define SOC_MCI_TOP_MCI_REG_FW_ERROR_FATAL (32'h21000050)
429-
`define SOC_MCI_TOP_MCI_REG_FW_ERROR_NON_FATAL (32'h21000054)
430-
`define SOC_MCI_TOP_MCI_REG_HW_ERROR_ENC (32'h21000058)
431-
`define SOC_MCI_TOP_MCI_REG_FW_ERROR_ENC (32'h2100005c)
432-
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_0 (32'h21000060)
433-
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_1 (32'h21000064)
434-
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_2 (32'h21000068)
435-
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_3 (32'h2100006c)
436-
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_4 (32'h21000070)
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`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_5 (32'h21000074)
438-
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_6 (32'h21000078)
439-
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_7 (32'h2100007c)
440-
`define SOC_MCI_TOP_MCI_REG_INTERNAL_HW_ERROR_FATAL_MASK (32'h21000080)
441-
`define SOC_MCI_TOP_MCI_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK (32'h21000084)
442-
`define SOC_MCI_TOP_MCI_REG_INTERNAL_AGG_ERROR_FATAL_MASK (32'h21000088)
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`define SOC_MCI_TOP_MCI_REG_INTERNAL_AGG_ERROR_NON_FATAL_MASK (32'h2100008c)
444-
`define SOC_MCI_TOP_MCI_REG_INTERNAL_FW_ERROR_FATAL_MASK (32'h21000090)
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`define SOC_MCI_TOP_MCI_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK (32'h21000094)
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`define SOC_MCI_TOP_MCI_REG_WDT_TIMER1_EN (32'h210000a0)
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`define SOC_MCI_TOP_MCI_REG_WDT_TIMER1_CTRL (32'h210000a4)
448-
`define SOC_MCI_TOP_MCI_REG_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'h210000a8)
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`define SOC_MCI_TOP_MCI_REG_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'h210000ac)
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`define SOC_MCI_TOP_MCI_REG_WDT_TIMER2_EN (32'h210000b0)
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`define SOC_MCI_TOP_MCI_REG_WDT_TIMER2_CTRL (32'h210000b4)
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`define SOC_MCI_TOP_MCI_REG_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'h210000b8)
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`define SOC_MCI_TOP_MCI_REG_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h210000bc)
454-
`define SOC_MCI_TOP_MCI_REG_WDT_STATUS (32'h210000c0)
455-
`define SOC_MCI_TOP_MCI_REG_WDT_CFG_0 (32'h210000d0)
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`define SOC_MCI_TOP_MCI_REG_WDT_CFG_1 (32'h210000d4)
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`define SOC_MCI_TOP_MCI_REG_MCU_IFU_AXI_USER (32'h21000020)
420+
`define SOC_MCI_TOP_MCI_REG_MCU_LSU_AXI_USER (32'h21000024)
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`define SOC_MCI_TOP_MCI_REG_MCU_SRAM_CONFIG_AXI_USER (32'h21000028)
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`define SOC_MCI_TOP_MCI_REG_MCI_SOC_CONFIG_AXI_USER (32'h2100002c)
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`define SOC_MCI_TOP_MCI_REG_FW_FLOW_STATUS (32'h21000030)
424+
`define SOC_MCI_TOP_MCI_REG_HW_FLOW_STATUS (32'h21000034)
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`define SOC_MCI_TOP_MCI_REG_RESET_REASON (32'h21000038)
426+
`define SOC_MCI_TOP_MCI_REG_RESET_STATUS (32'h2100003c)
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`define SOC_MCI_TOP_MCI_REG_SECURITY_STATE (32'h21000040)
428+
`define SOC_MCI_TOP_MCI_REG_HW_ERROR_FATAL (32'h21000050)
429+
`define SOC_MCI_TOP_MCI_REG_AGG_ERROR_FATAL (32'h21000054)
430+
`define SOC_MCI_TOP_MCI_REG_HW_ERROR_NON_FATAL (32'h21000058)
431+
`define SOC_MCI_TOP_MCI_REG_AGG_ERROR_NON_FATAL (32'h2100005c)
432+
`define SOC_MCI_TOP_MCI_REG_FW_ERROR_FATAL (32'h21000060)
433+
`define SOC_MCI_TOP_MCI_REG_FW_ERROR_NON_FATAL (32'h21000064)
434+
`define SOC_MCI_TOP_MCI_REG_HW_ERROR_ENC (32'h21000068)
435+
`define SOC_MCI_TOP_MCI_REG_FW_ERROR_ENC (32'h2100006c)
436+
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_0 (32'h21000070)
437+
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_1 (32'h21000074)
438+
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_2 (32'h21000078)
439+
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_3 (32'h2100007c)
440+
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_4 (32'h21000080)
441+
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_5 (32'h21000084)
442+
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_6 (32'h21000088)
443+
`define SOC_MCI_TOP_MCI_REG_FW_EXTENDED_ERROR_INFO_7 (32'h2100008c)
444+
`define SOC_MCI_TOP_MCI_REG_INTERNAL_HW_ERROR_FATAL_MASK (32'h21000090)
445+
`define SOC_MCI_TOP_MCI_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK (32'h21000094)
446+
`define SOC_MCI_TOP_MCI_REG_INTERNAL_AGG_ERROR_FATAL_MASK (32'h21000098)
447+
`define SOC_MCI_TOP_MCI_REG_INTERNAL_AGG_ERROR_NON_FATAL_MASK (32'h2100009c)
448+
`define SOC_MCI_TOP_MCI_REG_INTERNAL_FW_ERROR_FATAL_MASK (32'h210000a0)
449+
`define SOC_MCI_TOP_MCI_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK (32'h210000a4)
450+
`define SOC_MCI_TOP_MCI_REG_WDT_TIMER1_EN (32'h210000b0)
451+
`define SOC_MCI_TOP_MCI_REG_WDT_TIMER1_CTRL (32'h210000b4)
452+
`define SOC_MCI_TOP_MCI_REG_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'h210000b8)
453+
`define SOC_MCI_TOP_MCI_REG_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'h210000bc)
454+
`define SOC_MCI_TOP_MCI_REG_WDT_TIMER2_EN (32'h210000c0)
455+
`define SOC_MCI_TOP_MCI_REG_WDT_TIMER2_CTRL (32'h210000c4)
456+
`define SOC_MCI_TOP_MCI_REG_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'h210000c8)
457+
`define SOC_MCI_TOP_MCI_REG_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h210000cc)
458+
`define SOC_MCI_TOP_MCI_REG_WDT_STATUS (32'h210000d0)
459+
`define SOC_MCI_TOP_MCI_REG_WDT_CFG_0 (32'h210000d4)
460+
`define SOC_MCI_TOP_MCI_REG_WDT_CFG_1 (32'h210000d8)
457461
`define SOC_MCI_TOP_MCI_REG_MCU_TIMER_CONFIG (32'h210000e0)
458462
`define SOC_MCI_TOP_MCI_REG_MCU_RV_MTIME_L (32'h210000e4)
459463
`define SOC_MCI_TOP_MCI_REG_MCU_RV_MTIME_H (32'h210000e8)

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