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[Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200)
* User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com>
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‎.github/workflow_metadata/pr_hash‎

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‎.github/workflow_metadata/pr_timestamp‎

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‎src/integration/stimulus/L0_Promote_caliptra_ss_top_tb_regression.yml‎

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- ../test_suites/smoke_test_mcu_mbox_zeroize/smoke_test_mcu_mbox_zeroize.yml
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- ../test_suites/mcu_mbox_lock_return_one_during_zeroize/mcu_mbox_lock_return_one_during_zeroize.yml
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- ../test_suites/smoke_test_mbox_csr_zeros_after_release/smoke_test_mbox_csr_zeros_after_release.yml
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- ../test_suites/smoke_test_mcu_mbox_valid_user/smoke_test_mcu_mbox_valid_user.yml
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- ../test_suites/smoke_test_mcu_mbox_write_user_lock/smoke_test_mcu_mbox_write_user_lock.yml

‎src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv‎

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@@ -23,3 +23,5 @@ $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox/smoke_test_mcu
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$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_zeroize/smoke_test_mcu_mbox_zeroize , None , None , L0 , None, caliptra_ss_top_tb, Promote , None , 100
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$CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_mbox_lock_return_one_during_zeroize/mcu_mbox_lock_return_one_during_zeroize, None , None , L0 , None, caliptra_ss_top_tb, Promote , None , 100
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$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mbox_csr_zeros_after_release/smoke_test_mbox_csr_zeros_after_release, None , None , L0 , None, caliptra_ss_top_tb, Promote , None , 100
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$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_valid_user/smoke_test_mcu_mbox_valid_user , None , None , L0 , None, caliptra_ss_top_tb, Promote , None , 100
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$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_write_user_lock/smoke_test_mcu_mbox_write_user_lock , None , None , L0 , None, caliptra_ss_top_tb, Promote , None , 100

‎src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.c‎

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@@ -23,6 +23,7 @@
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#include "stdint.h"
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#include "caliptra_ss_clk_freq.h"
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#include "caliptra_ss_lib.h"
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#include <stdbool.h>
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#ifdef MY_RANDOM_SEED
@@ -164,15 +165,107 @@ void mcu_cptra_user_init() {
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}
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167-
void mcu_mbox_clear_lock_out_of_reset() {
168+
void mcu_mbox_clear_lock_out_of_reset(uint32_t mbox_num) {
168169
// MBOX: Write DLEN (normally would be max SRAM size but using smaller size for test run time)
169-
lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_DLEN, 32);
170+
lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_DLEN + MCU_MBOX_NUM_STRIDE*mbox_num, 32);
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171172
// MBOX: Clear Execute
172-
lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_EXECUTE, 0);
173-
VPRINTF(LOW, "MCU: Mbox0 execute clear\n");
173+
lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_EXECUTE + MCU_MBOX_NUM_STRIDE*mbox_num, 0);
174+
VPRINTF(LOW, "MCU: Mbox%x execute clear\n", mbox_num);
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175-
VPRINTF(LOW, "MCU: MBOX Lock out of reset cleared\n");
176+
VPRINTF(LOW, "MCU: Mbox%x Lock out of reset cleared\n", mbox_num);
177+
}
178+
179+
void mcu_mbox_update_status_complete(uint32_t mbox_num) {
180+
// MBOX: Write CMD
181+
VPRINTF(LOW, "MCU: Writing to MBOX status 0x2\n");
182+
lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_CMD_STATUS + MCU_MBOX_NUM_STRIDE*mbox_num, 0x2 );
183+
}
184+
185+
bool mcu_mbox_wait_for_user_lock(uint32_t mbox_num, uint32_t user_axi, uint32_t attempt_count) {
186+
VPRINTF(LOW, "MCU: Waiting for caliptra to acquire the lock in mbox%x\n", mbox_num);
187+
for(uint32_t ii=0; ii<attempt_count; ii++) {
188+
if(lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_USER + MCU_MBOX_NUM_STRIDE * mbox_num) == user_axi){
189+
VPRINTF(LOW, "MCU: Caliptra acquired Mbox%x lock\n", mbox_num);
190+
return true;
191+
}
192+
}
193+
return false;
194+
}
195+
196+
bool mcu_mbox_wait_for_user_execute(uint32_t mbox_num, uint32_t attempt_count) {
197+
VPRINTF(LOW, "MCU: Waiting for caliptra to set execute in mbox%x\n", mbox_num);
198+
for(uint32_t ii=0; ii<attempt_count; ii++) {
199+
if(lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_EXECUTE + MCU_MBOX_NUM_STRIDE * mbox_num)){
200+
VPRINTF(LOW, "MCU: Caliptra set execute for Mbox%x\n", mbox_num);
201+
202+
// Check that Mailbox cmd available from SOC interrupt has been set
203+
if((lsu_read_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R) &
204+
(MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_CMD_AVAIL_STS_MASK << mbox_num)) == 0) {
205+
VPRINTF(FATAL, "MCU: Mbox%x Mailbox cmd available from SoC interrupt not set\n", mbox_num);
206+
SEND_STDOUT_CTRL(0x1);
207+
while(1);
208+
}
209+
return true;
210+
}
211+
}
212+
return false;
213+
}
214+
215+
void mcu_mbox_clear_mbox_cmd_avail_interrupt(uint32_t mbox_num) {
216+
VPRINTF(LOW, "MCU: RW1C cmd available interrupt Mbox%x\n", mbox_num);
217+
uint32_t internal_intr = lsu_read_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R);
218+
internal_intr |= MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_CMD_AVAIL_STS_MASK << mbox_num;
219+
lsu_write_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R, internal_intr);
220+
221+
// Check that Mailbox cmd available from SOC interrupt has been cleared
222+
if((lsu_read_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R) &
223+
(MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_CMD_AVAIL_STS_MASK << mbox_num)) == 1) {
224+
VPRINTF(FATAL, "MCU: Mbox%x Mailbox cmd available from SoC interrupt not set\n", mbox_num);
225+
SEND_STDOUT_CTRL(0x1);
226+
while(1);
227+
}
228+
}
229+
230+
void mcu_mbox_configure_valid_axi(uint32_t mbox_num, uint32_t *axi_user_id) {
231+
232+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_VALID_AXI_USER_0 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, axi_user_id[0]);
233+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_VALID_AXI_USER_1 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, axi_user_id[1]);
234+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_VALID_AXI_USER_2 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, axi_user_id[2]);
235+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_VALID_AXI_USER_3 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, axi_user_id[3]);
236+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_VALID_AXI_USER_4 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, axi_user_id[4]);
237+
238+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_0 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, MCI_REG_MBOX0_AXI_USER_LOCK_0_LOCK_MASK);
239+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_1 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, MCI_REG_MBOX0_AXI_USER_LOCK_1_LOCK_MASK);
240+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_2 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, MCI_REG_MBOX0_AXI_USER_LOCK_2_LOCK_MASK);
241+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_3 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, MCI_REG_MBOX0_AXI_USER_LOCK_3_LOCK_MASK);
242+
lsu_write_32(SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_4 + MCU_MBOX_AXI_CFG_STRIDE*mbox_num, MCI_REG_MBOX0_AXI_USER_LOCK_4_LOCK_MASK);
243+
244+
VPRINTF(LOW, "MCU: Configured Valid AXI USERs in Mbox%x: 0 - 0x%x; 1 - 0x%x; 2 - 0x%x; 3 - 0x%x; 4 - 0x%x;\n", mbox_num, axi_user_id[0], axi_user_id[1], axi_user_id[2], axi_user_id[3], axi_user_id[4]);
245+
}
246+
247+
bool mcu_mbox_acquire_lock(uint32_t mbox_num, uint32_t attempt_count) {
248+
VPRINTF(LOW, "MCU: Waiting for Mbox%x lock acquired\n", mbox_num);
249+
for(uint32_t ii=0; ii<attempt_count; ii++) {
250+
if(!(lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_LOCK + MCU_MBOX_NUM_STRIDE * mbox_num) & MCU_MBOX0_CSR_MBOX_LOCK_LOCK_MASK)){
251+
VPRINTF(LOW, "MCU: Mbox%x lock acquired\n", mbox_num);
252+
return true;
253+
}
254+
}
255+
return false;
256+
}
257+
258+
bool mcu_mbox_wait_for_user_to_be_mcu(uint32_t mbox_num, uint32_t attempt_count) {
259+
// TODO: update with MCU Root Strap Value
260+
uint32_t mbox_resp_data;
261+
for(uint32_t ii=0; ii<attempt_count; ii++) {
262+
mbox_resp_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_USER + MCU_MBOX_NUM_STRIDE * mbox_num);
263+
if(mbox_resp_data != 0){
264+
VPRINTF(LOW, "MCU: MBOX%x USER = %x\n", mbox_num, mbox_resp_data);
265+
return true;
266+
}
267+
}
268+
return false;
176269
}
177270

178271
void mcu_cptra_poll_mb_ready() {

‎src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.h‎

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@@ -1,5 +1,6 @@
11
// SPDX-License-Identifier: Apache-2.0
22
//
3+
//
34
// Licensed under the Apache License, Version 2.0 (the "License");
45
// you may not use this file except in compliance with the License.
56
// You may obtain a copy of the License at
@@ -12,9 +13,12 @@
1213
// See the License for the specific language governing permissions and
1314
// limitations under the License.
1415
//
16+
1517
#ifndef CALIPTRA_SS_LIB
1618
#define CALIPTRA_SS_LIB
1719

20+
#include "soc_address_map.h"
21+
#include <stdbool.h>
1822

1923
extern uint32_t state;
2024
uint32_t xorshift32(void);
@@ -36,7 +40,14 @@ void boot_i3c_core(void);
3640
void boot_i3c_socmgmt_if(void);
3741
void boot_i3c_standby_ctrl_mode();
3842
void boot_i3c_reg(void);
39-
void mcu_mbox_clear_lock_out_of_reset();
43+
void mcu_mbox_clear_lock_out_of_reset(uint32_t mbox_num);
44+
void mcu_mbox_update_status_complete(uint32_t mbox_num);
45+
bool mcu_mbox_wait_for_user_lock(uint32_t mbox_num, uint32_t user_axi, uint32_t attempt_count);
46+
bool mcu_mbox_wait_for_user_execute(uint32_t mbox_num, uint32_t attempt_count);
47+
void mcu_mbox_configure_valid_axi(uint32_t mbox_num, uint32_t *axi_user_id);
48+
bool mcu_mbox_acquire_lock(uint32_t mbox_num, uint32_t attempt_count);
49+
bool mcu_mbox_wait_for_user_to_be_mcu(uint32_t mbox_num, uint32_t attempt_count);
50+
void mcu_mbox_clear_mbox_cmd_avail_interrupt(uint32_t mbox_num);
4051

4152
#define FC_LCC_CMD_OFFSET 0xB0
4253
#define CMD_FC_LCC_RESET FC_LCC_CMD_OFFSET + 0x02
@@ -49,4 +60,7 @@ void mcu_mbox_clear_lock_out_of_reset();
4960
#define CMD_FORCE_LC_TOKENS FC_LCC_CMD_OFFSET + 0x09
5061
#define CMD_LC_FORCE_RMA_SCRAP_PPD FC_LCC_CMD_OFFSET + 10
5162

63+
#define MCU_MBOX_NUM_STRIDE (SOC_MCI_TOP_MCU_MBOX1_CSR_BASE_ADDR - SOC_MCI_TOP_MCU_MBOX0_CSR_BASE_ADDR)
64+
#define MCU_MBOX_AXI_CFG_STRIDE (SOC_MCI_TOP_MCI_REG_MBOX1_AXI_USER_LOCK_0 - SOC_MCI_TOP_MCI_REG_MBOX0_AXI_USER_LOCK_0)
65+
5266
#endif // CALIPTRA_SS_LIB

‎src/integration/test_suites/mcu_mbox_lock_return_one_during_zeroize/mcu_mbox_lock_return_one_during_zeroize.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ void main (void) {
3838
enum boot_fsm_state_e boot_fsm_ps;
3939
const uint32_t mbox_dlen = 10000; // Program to large value to make sure zeroization is still in progress when read of lock arrives
4040

41+
uint32_t mbox_num = 0;
4142
uint32_t mbox_resp_dlen;
4243
uint32_t mbox_resp_data;
4344
uint32_t mci_boot_fsm_go;
@@ -59,7 +60,7 @@ void main (void) {
5960
mcu_cptra_user_init();
6061

6162
// MBOX: clear the lock on MBOX that is there from reset
62-
mcu_mbox_clear_lock_out_of_reset();
63+
mcu_mbox_clear_lock_out_of_reset(mbox_num);
6364

6465
VPRINTF(LOW, "=================\nMCU MBOX SRAM Testing\n=================\n\n")
6566

‎src/integration/test_suites/smoke_test_mcu_mbox/smoke_test_mcu_mbox.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,7 @@ void main (void) {
157157
char *argv[1];
158158
enum boot_fsm_state_e boot_fsm_ps;
159159
const uint32_t mbox_dlen = 16*4;
160+
uint32_t mbox_num = 0;
160161
uint32_t mbox_resp_dlen;
161162
uint32_t mbox_resp_data;
162163
uint32_t mci_boot_fsm_go;
@@ -176,7 +177,7 @@ void main (void) {
176177
mcu_cptra_fuse_init_axi_user(0xFFFFFFFF);
177178

178179

179-
mcu_mbox_clear_lock_out_of_reset();
180+
mcu_mbox_clear_lock_out_of_reset(mbox_num);
180181

181182
////////////////////////////////////
182183
// Mailbox command test

‎src/integration/test_suites/smoke_test_mcu_mbox/smoke_test_mcu_mbox.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,4 +4,4 @@ testname: smoke_test_mcu_mbox
44
pre-exec: |
55
echo "Running pre_exec for [smoke_test_mcu_mbox]"
66
make -f $CALIPTRA_SS_ROOT/tools/scripts/Makefile TESTNAME=smoke_test_mcu_mbox mcu_program.hex
7-
CALIPTRA_ROOT=$CALIPTRA_SS_ROOT/third_party/caliptra-rtl make -f $CALIPTRA_SS_ROOT/third_party/caliptra-rtl/tools/scripts/Makefile CALIPTRA_INTERNAL_TRNG=0 TEST_DIR=$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox TESTNAME=cptra_ss_mcu_mbox_test program.hex
7+
CALIPTRA_ROOT=$CALIPTRA_SS_ROOT/third_party/caliptra-rtl make -f $CALIPTRA_SS_ROOT/third_party/caliptra-rtl/tools/scripts/Makefile AUX_HEADER_FILES=$CALIPTRA_SS_ROOT/src/integration/rtl/soc_address_map.h CALIPTRA_INTERNAL_TRNG=0 TEST_DIR=$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox TESTNAME=cptra_ss_mcu_mbox_test program.hex

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