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| 1 | +//******************************************************************************** |
| 2 | +// SPDX-License-Identifier: Apache-2.0 |
| 3 | +// |
| 4 | +// |
| 5 | +// Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | +// you may not use this file except in compliance with the License. |
| 7 | +// You may obtain a copy of the License at |
| 8 | +// |
| 9 | +// http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | +// |
| 11 | +// Unless required by applicable law or agreed to in writing, software |
| 12 | +// distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | +// See the License for the specific language governing permissions and |
| 15 | +// limitations under the License. |
| 16 | +//******************************************************************************** |
| 17 | +//******************************************************************************** |
| 18 | +// SPDX-License-Identifier: Apache-2.0 |
| 19 | +// |
| 20 | +// |
| 21 | +// Licensed under the Apache License, Version 2.0 (the \"License\"); |
| 22 | +// you may not use this file except in compliance with the License. |
| 23 | +// You may obtain a copy of the License at |
| 24 | +// |
| 25 | +// http://www.apache.org/licenses/LICENSE-2.0 |
| 26 | +// |
| 27 | +// Unless required by applicable law or agreed to in writing, software |
| 28 | +// distributed under the License is distributed on an \"AS IS\" BASIS, |
| 29 | +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 30 | +// See the License for the specific language governing permissions and |
| 31 | +// limitations under the License. |
| 32 | +//********************************************************************************" |
| 33 | + |
| 34 | +#include "soc_address_map.h" |
| 35 | +#include "printf.h" |
| 36 | +#include "riscv_hw_if.h" |
| 37 | +#include "soc_ifc.h" |
| 38 | +#include "caliptra_ss_lib.h" |
| 39 | +#include "string.h" |
| 40 | +#include "stdint.h" |
| 41 | +#include "veer-csr.h" |
| 42 | + |
| 43 | +volatile char* stdout = (char *)SOC_MCI_TOP_MCI_REG_DEBUG_OUT; |
| 44 | +// volatile char* stdout = (char *)0xd0580000; |
| 45 | + |
| 46 | +#ifdef CPT_VERBOSITY |
| 47 | + enum printf_verbosity verbosity_g = CPT_VERBOSITY; |
| 48 | +#else |
| 49 | + enum printf_verbosity verbosity_g = LOW; |
| 50 | +#endif |
| 51 | + |
| 52 | + |
| 53 | +void main (void) { |
| 54 | + |
| 55 | + int argc=0; |
| 56 | + char *argv[1]; |
| 57 | + uint32_t i3c_reg_data; |
| 58 | + int err_count = 0; |
| 59 | + |
| 60 | + // Initialize the printf library |
| 61 | + VPRINTF(LOW, "=== MCU boot.. started == \n"); |
| 62 | + |
| 63 | + //-- Boot MCU |
| 64 | + VPRINTF(LOW, "MCU: Booting...\n"); |
| 65 | + boot_mcu(); |
| 66 | + boot_i3c_core(); |
| 67 | + trigger_caliptra_go(); |
| 68 | + mcu_cptra_user_init(); |
| 69 | + wait_for_cptra_ready_for_mb_processing(); |
| 70 | + |
| 71 | + //-- setting bypass mode for I3C |
| 72 | + i3c_reg_data = 0x00000000 | I3CCSR_I3C_EC_SOCMGMTIF_REC_INTF_CFG_REC_INTF_BYPASS_MASK; |
| 73 | + lsu_write_32(SOC_I3CCSR_I3C_EC_SOCMGMTIF_REC_INTF_CFG, i3c_reg_data); |
| 74 | + VPRINTF(LOW,"I3C BYPASS mode set"); |
| 75 | + |
| 76 | + VPRINTF(LOW, "=== MCU boot.. completed == \n"); |
| 77 | + |
| 78 | + // Check if the I3C core is in the correct state |
| 79 | + i3c_reg_data = lsu_read_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_PROT_CAP_0); |
| 80 | + if (i3c_reg_data != 0x2050434f) { |
| 81 | + VPRINTF(LOW, "Error : I3C core not in the correct state\n"); |
| 82 | + err_count++; |
| 83 | + } |
| 84 | + |
| 85 | + i3c_reg_data = lsu_read_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_PROT_CAP_1); |
| 86 | + if (i3c_reg_data != 0x56434552) { |
| 87 | + VPRINTF(LOW, "I3C core not in the correct state\n"); |
| 88 | + err_count++; |
| 89 | + } |
| 90 | + |
| 91 | + // Read DEVICE_ID |
| 92 | + i3c_reg_data = lsu_read_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_DEVICE_ID_0); |
| 93 | + // TODO : add data checking |
| 94 | + |
| 95 | + // Read HW_STATUS |
| 96 | + i3c_reg_data = lsu_read_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_HW_STATUS); |
| 97 | + // TODO : add data checking |
| 98 | + |
| 99 | + // Read DEVICE_STATUS_0 |
| 100 | + i3c_reg_data = lsu_read_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_DEVICE_STATUS_0); |
| 101 | + // TODO : add data checking |
| 102 | + |
| 103 | + |
| 104 | + // waiting for recovery start |
| 105 | + while (1) { |
| 106 | + |
| 107 | + i3c_reg_data = lsu_read_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_DEVICE_STATUS_0); |
| 108 | + // i3c_reg_data == 0x00000003 |
| 109 | + i3c_reg_data = i3c_reg_data & 0x00000003; |
| 110 | + VPRINTF(LOW, "I3C core device status is 0x%x\n", i3c_reg_data); |
| 111 | + if (i3c_reg_data == 0x00000003) { |
| 112 | + VPRINTF(LOW, "I3C core in recovery mode\n"); |
| 113 | + break; |
| 114 | + } |
| 115 | + // Wait for the I3C core to finish the test |
| 116 | + VPRINTF(LOW, "Waiting for recovery start\n"); |
| 117 | + mcu_sleep(1000); |
| 118 | + |
| 119 | + } |
| 120 | + |
| 121 | + //-- Read Recovery Status register for 0x00000001 |
| 122 | + i3c_reg_data = lsu_read_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_RECOVERY_STATUS); |
| 123 | + if (i3c_reg_data != 0x00000001) { |
| 124 | + VPRINTF(LOW, "I3C core recovery status is not set to 0x1\n"); |
| 125 | + err_count++; |
| 126 | + } |
| 127 | + |
| 128 | + //-- writing RECOVERY_CTRL register |
| 129 | + i3c_reg_data = 0x00000000; |
| 130 | + lsu_write_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_RECOVERY_CTRL, i3c_reg_data); |
| 131 | + VPRINTF(LOW, "I3C core recovery control register is set to 0x0\n"); |
| 132 | + |
| 133 | + //-- writing INDIRECT_FIFO_CTRL Register |
| 134 | + i3c_reg_data = 0x00000100; |
| 135 | + lsu_write_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_INDIRECT_FIFO_CTRL_0, i3c_reg_data); |
| 136 | + VPRINTF(LOW, "I3C core indirect FIFO control register is set to 0x0100\n"); |
| 137 | + |
| 138 | + //-- writing INDIRECT_FIFO_CTRL Register 1 |
| 139 | + i3c_reg_data = 0x00000004; |
| 140 | + lsu_write_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_INDIRECT_FIFO_CTRL_1, i3c_reg_data); |
| 141 | + VPRINTF(LOW, "I3C core indirect FIFO control register 1 is set to 0x00000001\n"); |
| 142 | + |
| 143 | + //-- writing INDIRECT_FIFO_DATA Register |
| 144 | + i3c_reg_data = 0x12345678; |
| 145 | + lsu_write_32(SOC_I3CCSR_I3C_EC_TTI_TX_DATA_PORT, i3c_reg_data); |
| 146 | + VPRINTF(LOW, "I3C core indirect FIFO data register is set to 0x12345678\n"); |
| 147 | + |
| 148 | + i3c_reg_data = 0xABCDCAFE; |
| 149 | + lsu_write_32(SOC_I3CCSR_I3C_EC_TTI_TX_DATA_PORT, i3c_reg_data); |
| 150 | + VPRINTF(LOW, "I3C core indirect FIFO data register is set to 0xABCDCAFE\n"); |
| 151 | + |
| 152 | + i3c_reg_data = 0x23456789; |
| 153 | + lsu_write_32(SOC_I3CCSR_I3C_EC_TTI_TX_DATA_PORT, i3c_reg_data); |
| 154 | + VPRINTF(LOW, "I3C core indirect FIFO data register is set to 0x23456789\n"); |
| 155 | + |
| 156 | + i3c_reg_data = 0xFEEDCAFE; |
| 157 | + lsu_write_32(SOC_I3CCSR_I3C_EC_TTI_TX_DATA_PORT, i3c_reg_data); |
| 158 | + VPRINTF(LOW, "I3C core indirect FIFO data register is set to 0xFEEDCAFE\n"); |
| 159 | + |
| 160 | + //-- writing RECOVERY_CTRL Register |
| 161 | + i3c_reg_data = 0x00000F00; |
| 162 | + lsu_write_32(SOC_I3CCSR_I3C_EC_SOCMGMTIF_REC_INTF_REG_W1C_ACCESS, i3c_reg_data); |
| 163 | + VPRINTF(LOW, "I3C core recovery control register set to IMAGE ACTIVATION\n"); |
| 164 | + |
| 165 | + // -- Read Recovery Status register to indicate RECOVERY SUCCESS by reading value 0x00000003 |
| 166 | + while(1){ |
| 167 | + i3c_reg_data = lsu_read_32(SOC_I3CCSR_I3C_EC_SECFWRECOVERYIF_RECOVERY_STATUS); |
| 168 | + if( i3c_reg_data != 0x00000002 || i3c_reg_data != 0x00000003 || i3c_reg_data != 0x00000004) { |
| 169 | + VPRINTF(LOW, "I3C core recovery status is not set to expected value\n"); |
| 170 | + err_count++; |
| 171 | + } |
| 172 | + if (i3c_reg_data == 0x00000003) { |
| 173 | + VPRINTF(LOW, "I3C core recovery status is set to 0x3\n"); |
| 174 | + break; |
| 175 | + } |
| 176 | + // Wait for the I3C core to finish the test |
| 177 | + VPRINTF(LOW, "Waiting for recovery status update\n"); |
| 178 | + mcu_sleep(1000); |
| 179 | + } |
| 180 | + |
| 181 | + |
| 182 | + //Halt the core to wait for Caliptra to finish the test |
| 183 | + csr_write_mpmc_halt(); |
| 184 | +} |
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