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[fuse_ctrl, test] caliptra_ss_fuse_ctrl_init_fail (#265)
* [fuse_ctrl, test] caliptra_ss_fuse_ctrl_init_fail Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'caliptra_ss_fuse_ctrl_init_fail' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org>
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‎.github/workflow_metadata/pr_hash‎

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cffe193254f81be9b6907d79acf2c1129a0017e1762731a2d200c1de3accb97561e2bc78e3602d9867e46f390e77bb79

‎.github/workflow_metadata/pr_timestamp‎

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‎src/integration/stimulus/L1_Nightly_Random_caliptra_ss_top_tb_regression.yml‎

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$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_sram_execution_region/smoke_test_mcu_sram_execution_region_max_size: { weight: 100 }
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$CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_mcu_sram_to_sha/caliptra_ss_mcu_sram_to_sha: { weight: 100 }
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$CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_external_clock/caliptra_ss_fuse_ctrl_external_clock: { weight: 100 }
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$CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_lcc_escalation/caliptra_ss_lcc_escalation: { weight: 100 }
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$CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_integrity_check/caliptra_ss_fuse_ctrl_init_fail: { weight: 100 }

‎src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv‎

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@@ -57,3 +57,4 @@ $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_bus_ecc_erro
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$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_wdt/smoke_test_wdt , None , None , L0 , None, caliptra_ss_top_tb, Promote , None , 100
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$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_wdt_rst/smoke_test_wdt_rst , Directed , Nightly , None, L1 , caliptra_ss_top_tb, None , None , 100
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$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_st_trans/smoke_test_lcc_st_trans , Directed , Nightly , L0 , L1 , caliptra_ss_top_tb, Promote , None , 100
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$CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_integrity_check/caliptra_ss_fuse_ctrl_init_fail , Random , Nightly , None, L1 , caliptra_ss_top_tb, None , None , 100

‎src/integration/test_suites/caliptra_ss_fuse_ctrl_init_fail/caliptra_ss_fuse_ctrl_init_fail.c‎

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#include <string.h>
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#include <stdint.h>
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#include <time.h>
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#include <stdlib.h>
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#include "soc_address_map.h"
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#include "printf.h"
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#include "riscv_hw_if.h"
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#include "soc_ifc.h"
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#include "caliptra_ss_lc_ctrl_address_map.h"
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#include "caliptra_ss_lib.h"
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#include "fuse_ctrl.h"
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#include "lc_ctrl.h"
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volatile char* stdout = (char *)SOC_MCI_TOP_MCI_REG_DEBUG_OUT;
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#ifdef CPT_VERBOSITY
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enum printf_verbosity verbosity_g = CPT_VERBOSITY;
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#else
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enum printf_verbosity verbosity_g = LOW;
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#endif
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typedef struct {
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uint32_t address;
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uint32_t digest_address;
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uint32_t index;
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} partition_t;
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// XXX: Fuse addresses, eventually these should be generated automatically.
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// Buffered partitions.
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static partition_t partitions[8] = {
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// SECRET_TEST_UNLOCK_PARTITION
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{ .address = 0x000, .digest_address = 0x040, .index = 0 },
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// SECRET_MANUF_PARTITION
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{ .address = 0x048, .digest_address = 0x088, .index = 1 },
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// SECRET_PROD_PARTITION_0
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{ .address = 0x090, .digest_address = 0x098, .index = 2 },
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// SECRET_PROD_PARTITION_1
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{ .address = 0x0A0, .digest_address = 0x0A8, .index = 3 },
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// SECRET_PROD_PARTITION_2
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{ .address = 0x0B0, .digest_address = 0x0B8, .index = 4 },
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// SECRET_PROD_PARTITION_3
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{ .address = 0x0C0, .digest_address = 0x0C8, .index = 5 },
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// SECRET_LC_TRANSITION_PARTITION
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{ .address = 0x4C0, .digest_address = 0x570, .index = 7 },
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// VENDOR_SECRET_PROD_PARTITION
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{ .address = 0x9A8, .digest_address = 0xBA8, .index = 13 }
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};
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void init_fail() {
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const uint32_t faults[2] = {
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CMD_FC_LCC_CORRECTABLE_FAULT,
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CMD_FC_LCC_UNCORRECTABLE_FAULT
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};
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partition_t partition = partitions[xorshift32() % 8];
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uint32_t fault = faults[xorshift32() % 2];
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if (partition.address < 0x090) {
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grant_caliptra_core_for_fc_writes();
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} else {
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grant_mcu_for_fc_writes();
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}
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// Write one word in the selected partition and lock it afterwards.
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dai_wr(partition.address, 0x1, 0x2, 64, 0);
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calculate_digest(partition.address);
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// Inject either a correctable or uncorrectable error into the written partition.
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lsu_write_32(SOC_MCI_TOP_MCI_REG_DEBUG_OUT, fault);
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wait_dai_op_idle(0);
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reset_fc_lcc_rtl();
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wait_dai_op_idle(
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fault == CMD_FC_LCC_CORRECTABLE_FAULT ? 1 << partition.index : 0x3FFFF
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);
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uint32_t err_reg = lsu_read_32(SOC_OTP_CTRL_ERR_CODE_RF_ERR_CODE_0 + 0x4*partition.index);
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uint32_t status_reg = lsu_read_32(SOC_OTP_CTRL_STATUS);
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80+
if (fault == CMD_FC_LCC_CORRECTABLE_FAULT) {
81+
if (err_reg != 0x2) {
82+
VPRINTF(LOW, "ERROR: err code register does not show correctable error: %08X\n", err_reg);
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return;
84+
}
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} else {
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if (err_reg != 0x3) {
87+
VPRINTF(LOW, "ERROR: err code register does not show uncorrectable error: %08X\n", err_reg);
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return;
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}
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}
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}
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void main (void) {
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VPRINTF(LOW, "=================\nMCU Caliptra Boot Go\n=================\n\n")
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mcu_cptra_init_d();
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wait_dai_op_idle(0);
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lcc_initialization();
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grant_mcu_for_fc_writes();
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transition_state(TEST_UNLOCKED0, raw_unlock_token[0], raw_unlock_token[1], raw_unlock_token[2], raw_unlock_token[3], 1);
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wait_dai_op_idle(0);
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initialize_otp_controller();
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init_fail();
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for (uint8_t ii = 0; ii < 160; ii++) {
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__asm__ volatile ("nop"); // Sleep loop as "nop"
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}
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SEND_STDOUT_CTRL(0xff);
114+
}

‎src/integration/test_suites/caliptra_ss_fuse_ctrl_init_fail/caliptra_ss_fuse_ctrl_init_fail.yml‎

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---
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seed: ${PLAYBOOK_RANDOM_SEED}
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testname: caliptra_ss_fuse_ctrl_init_fail
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pre-exec: |
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echo "Running pre_exec for [caliptra_ss_fuse_ctrl_init_fail]"
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CALIPTRA_ROOT=$CALIPTRA_SS_ROOT/third_party/caliptra-rtl make -f $CALIPTRA_SS_ROOT/third_party/caliptra-rtl/tools/scripts/Makefile CALIPTRA_INTERNAL_TRNG=0 TESTNAME=smoke_test_mbox program.hex
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make -f $CALIPTRA_SS_ROOT/tools/scripts/Makefile TESTNAME=caliptra_ss_fuse_ctrl_init_fail mcu_program.hex

‎src/integration/test_suites/caliptra_ss_fuse_ctrl_integrity_check/caliptra_ss_fuse_ctrl_integrity_check.c‎

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@@ -37,7 +37,7 @@ void main (void) {
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initialize_otp_controller();
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40-
wait_dai_op_idle(0x1BFFFF);
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wait_dai_op_idle(0x3FFFF);
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for (uint8_t ii = 0; ii < 160; ii++) {
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__asm__ volatile ("nop"); // Sleep loop as "nop"

‎src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.h‎

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#define CMD_LC_TRIGGER_ESCALATION1 FC_LCC_CMD_OFFSET + 0x13
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#define CMD_LC_DISABLE_SVA FC_LCC_CMD_OFFSET + 0x14
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#define CMD_LC_ENABLE_SVA FC_LCC_CMD_OFFSET + 0x15
48+
#define CMD_FC_LCC_CORRECTABLE_FAULT FC_LCC_CMD_OFFSET + 0x16
49+
#define CMD_FC_LCC_UNCORRECTABLE_FAULT FC_LCC_CMD_OFFSET + 0x17
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5052
#define TB_CMD_DISABLE_MCU_SRAM_PROT_ASSERTS 0xC0
@@ -224,6 +226,28 @@ static inline void mcu_mbox_write_cmd_status(uint32_t mbox_num, enum mcu_mbox_cm
224226
lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_CMD_STATUS + MCU_MBOX_NUM_STRIDE * mbox_num, (cmd_status & MCU_MBOX0_CSR_MBOX_CMD_STATUS_STATUS_MASK));
225227
}
226228

229+
#define FC_LCC_CMD_OFFSET 0x90
230+
#define CMD_FC_LCC_RESET FC_LCC_CMD_OFFSET + 0x02
231+
#define CMD_FORCE_FC_AWUSER_CPTR_CORE FC_LCC_CMD_OFFSET + 0x03
232+
#define CMD_FORCE_FC_AWUSER_MCU FC_LCC_CMD_OFFSET + 0x04
233+
#define CMD_RELEASE_AWUSER FC_LCC_CMD_OFFSET + 0x05
234+
#define CMD_FC_FORCE_ZEROIZATION FC_LCC_CMD_OFFSET + 0x06
235+
#define CMD_FC_FORCE_ZEROIZATION_RESET FC_LCC_CMD_OFFSET + 0x07
236+
#define CMD_RELEASE_ZEROIZATION FC_LCC_CMD_OFFSET + 0x08
237+
#define CMD_FORCE_LC_TOKENS FC_LCC_CMD_OFFSET + 0x09
238+
#define CMD_LC_FORCE_RMA_SCRAP_PPD FC_LCC_CMD_OFFSET + 0x0a
239+
#define CMD_FC_TRIGGER_ESCALATION FC_LCC_CMD_OFFSET + 0x0b
240+
#define CMD_FC_LCC_EXT_CLK_500MHZ FC_LCC_CMD_OFFSET + 0x0c
241+
#define CMD_FC_LCC_EXT_CLK_160MHZ FC_LCC_CMD_OFFSET + 0x0d
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#define CMD_FC_LCC_EXT_CLK_400MHZ FC_LCC_CMD_OFFSET + 0x0e
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#define CMD_FC_LCC_EXT_CLK_1000MHZ FC_LCC_CMD_OFFSET + 0x0f
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#define CMD_FC_LCC_FAULT_DIGEST FC_LCC_CMD_OFFSET + 0x10
245+
#define CMD_FC_LCC_FAULT_BUS_ECC FC_LCC_CMD_OFFSET + 0x11
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#define CMD_LC_TRIGGER_ESCALATION0 FC_LCC_CMD_OFFSET + 0x12
247+
#define CMD_LC_TRIGGER_ESCALATION1 FC_LCC_CMD_OFFSET + 0x13
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#define CMD_FC_LCC_CORRECTABLE_FAULT FC_LCC_CMD_OFFSET + 0x14
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#define CMD_FC_LCC_UNCORRECTABLE_FAULT FC_LCC_CMD_OFFSET + 0x15
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227251
static inline uint32_t mcu_mbox_read_cmd_status(uint32_t mbox_num) {
228252
uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_CMD_STATUS + MCU_MBOX_NUM_STRIDE * mbox_num);
229253
VPRINTF(LOW, "MCU: Mbox%x Reading CMD_STATUS: 0x%x\n", mbox_num, rd_data);

‎src/integration/test_suites/libs/fuse_ctrl/fuse_ctrl.c‎

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@@ -49,13 +49,12 @@ void wait_dai_op_idle(uint32_t status_mask) {
4949
status = lsu_read_32(SOC_OTP_CTRL_STATUS);
5050
dai_idle = (status >> OTP_CTRL_STATUS_DAI_IDLE_LOW) & 0x1;
5151
check_pending = (status >> OTP_CTRL_STATUS_CHECK_PENDING_LOW) & 0x1;
52-
} while ((!dai_idle || check_pending) && (status != 0x1BFFFF));
52+
} while ((!dai_idle || check_pending) && ((status & 0x3FFFF) != 0x3FFFF));
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5454
// Clear the IDLE bit from the status value
5555
status &= ((((uint32_t)1) << (OTP_CTRL_STATUS_DAI_IDLE_LOW - 1)) - 1);
5656
if (status != status_mask) {
5757
VPRINTF(LOW, "ERROR: unexpected status: expected: %08X actual: %08X\n", status_mask, status);
58-
exit(1);
5958
}
6059
VPRINTF(LOW, "DEBUG: DAI is now idle.\n");
6160
return;

‎src/integration/testbench/caliptra_ss_tb_cmd_list.svh‎

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@@ -83,6 +83,9 @@ localparam CMD_LC_TRIGGER_ESCALATION0 = FC_LCC_CMD_OFFSET + 8'h12;
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localparam CMD_LC_TRIGGER_ESCALATION1 = FC_LCC_CMD_OFFSET + 8'h13;
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localparam CMD_LC_DISABLE_SVA = FC_LCC_CMD_OFFSET + 8'h14;
8585
localparam CMD_LC_ENABLE_SVA = FC_LCC_CMD_OFFSET + 8'h15;
86+
localparam CMD_FC_LCC_CORRECTABLE_FAULT = FC_LCC_CMD_OFFSET + 8'h16;
87+
localparam CMD_FC_LCC_UNCORRECTABLE_FAULT = FC_LCC_CMD_OFFSET + 8'h17;
88+
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8790
localparam TB_DISABLE_MCU_SRAM_PROT_ASSERTS = 8'hc0;
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