[Intel] Gaussian & Neural Accelerator - GNA technology

* Renamed Gemini Lake structures

Author: cyring

x86_64/corefreq-api.h

@@ -814,8 +814,8 @@ typedef struct
 			ADL_SA_PERF_STATUS	ADL_SA_Pll;
 		};
 		struct {
-			GKL_CAPID_A		GKL_Cap_A;
-			GKL_CAPID_B		GKL_Cap_B;
+			GLK_CAPID_A		GLK_Cap_A;
+			GLK_CAPID_B		GLK_Cap_B;
 		};
 		struct {
 			MTL_CAPID_A		MTL_Cap_A;

x86_64/corefreq-cli-json.c

@@ -1531,6 +1531,9 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L2_UpDown_Pf);
 			json_key(&s, "LLC_Streamer");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.LLC_Streamer);
+			json_key(&s, "GNA");
+			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.GNA);
+
 
 			json_end_object(&s);
 		}

x86_64/corefreq-cli-rsc-en.h

@@ -1241,6 +1241,7 @@
 #define RSC_TECHNOLOGIES_R2H_CODE_EN	"Race To Halt Optimization"
 #define RSC_TECHNOLOGIES_HYPERV_CODE_EN "Hypervisor"
 #define RSC_TECHNOLOGIES_WDT_CODE_EN	"Watchdog Timer"
+#define RSC_TECHNOLOGIES_GNA_CODE_EN	"Gaussian & Neural Accelerator"
 
 #define RSC_TECH_AMD_CPB_COMM_CODE_EN	" Hardware Configuration::CpbDis "
 #define RSC_TECH_INTEL_EEO_COMM_CODE_EN " Skylake::Power Control::EEO_Disable "

x86_64/corefreq-cli-rsc-fr.h

@@ -715,6 +715,8 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_TECHNOLOGIES_R2H_CODE_FR	"Optimisation Race To Halt"
 #define RSC_TECHNOLOGIES_HYPERV_CODE_FR "Hyperviseur"
 #define RSC_TECHNOLOGIES_WDT_CODE_FR	"Compteur Watchdog"
+#define RSC_TECHNOLOGIES_GNA_CODE_FR	\
+				"Acc""\xa9""l""\xa9""rateur Gaussien & Neuronal"
 
 #define RSC_TECH_AMD_CPB_COMM_CODE_FR	RSC_TECH_AMD_CPB_COMM_CODE_EN
 #define RSC_TECH_INTEL_EEO_COMM_CODE_FR RSC_TECH_INTEL_EEO_COMM_CODE_EN

x86_64/corefreq-cli-rsc.c

@@ -1151,6 +1151,7 @@ RESOURCE_ST Resource[] = {
 	LDQ(RSC_TECH_HYPERV_KBOX),
 	LDQ(RSC_TECH_HYPERV_VMWARE),
 	LDQ(RSC_TECH_HYPERV_HYPERV),
+	LDT(RSC_TECHNOLOGIES_GNA),
 	LDT(RSC_PERF_MON_TITLE),
 	LDT(RSC_PERF_CAPS_TITLE),
 	LDT(RSC_VERSION),

x86_64/corefreq-cli-rsc.h

@@ -954,6 +954,7 @@ enum {
 	RSC_TECH_HYPERV_KBOX,
 	RSC_TECH_HYPERV_VMWARE,
 	RSC_TECH_HYPERV_HYPERV,
+	RSC_TECHNOLOGIES_GNA,
 	RSC_PERF_MON_TITLE,
 	RSC_PERF_CAPS_TITLE,
 	RSC_VERSION,

x86_64/corefreq-cli.c

@@ -4389,6 +4389,16 @@ REASON_CODE SysInfoTech(Window *win,
 		: (char*) RSC(NOT_AVAILABLE).CODE(),
 		SCANKEY_NULL,
 		NULL
+	},
+	{
+		(unsigned int[]) { CRC_INTEL, 0 },
+		RO(Shm)->Proc.Technology.GNA == 1,
+		2, "%s%.*sGNA   [%3s]",
+		RSC(TECHNOLOGIES_GNA).CODE(), NULL,
+		width - 14 - RSZ(TECHNOLOGIES_GNA),
+		NULL,
+		SCANKEY_NULL,
+		NULL
 	}
     };
 	size_t idx;

x86_64/corefreq.h

@@ -370,7 +370,8 @@ typedef struct
 				L2_Stream_HW_Pf : 41-40,
 				L2_UpDown_Pf	: 42-41,
 				LLC_Streamer	: 43-42,
-				_pad64		: 64-43;
+				GNA		: 44-43,
+				_pad64		: 64-44;
 	} Technology;
 
 	struct {

x86_64/corefreqd.c

@@ -4970,6 +4970,8 @@ void SKL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 
 	RO(Shm)->Proc.Technology.IOMMU_Ver_Minor = \
 					RO(Proc)->Uncore.Bus.IOMMU_Ver.Minor;
+
+	RO(Shm)->Proc.Technology.GNA = !RO(Proc)->Uncore.Bus.SKL_Cap_B.GMM_DIS;
 }
 
 void RKL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
@@ -5286,6 +5288,8 @@ void RKL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 
 	RO(Shm)->Proc.Technology.IOMMU_Ver_Minor = \
 					RO(Proc)->Uncore.Bus.IOMMU_Ver.Minor;
+
+	RO(Shm)->Proc.Technology.GNA = !RO(Proc)->Uncore.Bus.RKL_Cap_B.GNA_DIS;
 }
 
 void TGL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
@@ -5838,6 +5842,8 @@ void ADL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 
 	RO(Shm)->Proc.Technology.IOMMU_Ver_Minor = \
 					RO(Proc)->Uncore.Bus.IOMMU_Ver.Minor;
+
+	RO(Shm)->Proc.Technology.GNA = !RO(Proc)->Uncore.Bus.ADL_Cap_B.GNA_DIS;
 }
 
 void GLK_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
@@ -5851,13 +5857,15 @@ void GLK_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 	RO(Shm)->Uncore.Unit.BusSpeed = MC_NIL;
 	RO(Shm)->Uncore.Unit.DDRSpeed = MC_NIL;
 
-	RO(Shm)->Proc.Technology.IOMMU = !RO(Proc)->Uncore.Bus.RKL_Cap_A.VT_d;
+	RO(Shm)->Proc.Technology.IOMMU = !RO(Proc)->Uncore.Bus.GLK_Cap_A.VT_d;
 
 	RO(Shm)->Proc.Technology.IOMMU_Ver_Major = \
 					RO(Proc)->Uncore.Bus.IOMMU_Ver.Major;
 
 	RO(Shm)->Proc.Technology.IOMMU_Ver_Minor = \
 					RO(Proc)->Uncore.Bus.IOMMU_Ver.Minor;
+
+	RO(Shm)->Proc.Technology.GNA = !RO(Proc)->Uncore.Bus.GLK_Cap_B.GMM_DIS;
 }
 
 void GLK_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
@@ -5982,6 +5990,8 @@ void MTL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 
 	RO(Shm)->Proc.Technology.IOMMU_Ver_Minor = \
 					RO(Proc)->Uncore.Bus.IOMMU_Ver.Minor;
+
+	RO(Shm)->Proc.Technology.GNA = !RO(Proc)->Uncore.Bus.MTL_Cap_B.GNA_DIS;
 }
 
 void MTL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))

x86_64/corefreqk.c

@@ -6514,10 +6514,10 @@ static PCI_CALLBACK GLK_IMC(struct pci_dev *dev)
 	PUBLIC(RO(Proc))->Uncore.CtrlCount = 1;
 
 	pci_read_config_dword(dev, 0xe4,
-				&PUBLIC(RO(Proc))->Uncore.Bus.GKL_Cap_A.value);
+				&PUBLIC(RO(Proc))->Uncore.Bus.GLK_Cap_A.value);
 
 	pci_read_config_dword(dev, 0xe8,
-				&PUBLIC(RO(Proc))->Uncore.Bus.GKL_Cap_B.value);
+				&PUBLIC(RO(Proc))->Uncore.Bus.GLK_Cap_B.value);
 
 	SoC_SKL_VTD();