Introducing a framework to collect thermal points, per Core, per Package.

For capable processors, thresholds and limits within registers:
* Intel: MSR_IA32_THERM_INTERRUPT; MSR_IA32_PACKAGE_THERM_INTERRUPT
* AMD: SMU_AMD_THM_TCTL_REGISTER_F17H at offsets 0x4 and 0x8

Author: cyring

corefreq-api.h

@@ -361,6 +361,7 @@ typedef struct
 	} Delta __attribute__ ((aligned (8)));
 
 	POWER_THERMAL			PowerThermal;
+	THERMAL_POINT			ThermalPoint;
 
 	struct
 	{
@@ -877,6 +878,8 @@ typedef struct
 	  };
 	} PowerThermal;
 
+	THERMAL_POINT		ThermalPoint;
+
 	struct {
 		struct {
 			size_t	Size;

corefreq-cli-rsc-en.h

@@ -997,6 +997,9 @@
 #define RSC_POWER_THERMAL_TPL_CODE_EN	"Power Limit"
 #define RSC_POWER_THERMAL_EDC_CODE_EN	"Electrical Design Current"
 #define RSC_POWER_THERMAL_TDC_CODE_EN	"Thermal Design Current"
+#define RSC_POWER_THERMAL_POINT_CODE_EN "Thermal Point"
+#define RSC_THERMAL_POINT_THRESHOLD_CODE_EN "Threshold"
+#define RSC_THERMAL_POINT_LIMIT_CODE_EN "Limit"
 
 #define RSC_KERNEL_TITLE_CODE_EN	" Kernel "
 #define RSC_KERNEL_TOTAL_RAM_CODE_EN	"Total RAM"

corefreq-cli-rsc-fr.h

@@ -645,6 +645,9 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_POWER_THERMAL_TPL_CODE_FR	"Limite de puissance"
 #define RSC_POWER_THERMAL_EDC_CODE_FR	"Limite de courant sup""\xa9""rieure"
 #define RSC_POWER_THERMAL_TDC_CODE_FR	"Limite de courant sup""\xa9""rieure"
+#define RSC_POWER_THERMAL_POINT_CODE_FR "Seuil thermique"
+#define RSC_THERMAL_POINT_THRESHOLD_CODE_FR "Threshold"
+#define RSC_THERMAL_POINT_LIMIT_CODE_FR "Limite"
 
 #define RSC_KERNEL_TITLE_CODE_FR	" Noyau "
 #define RSC_KERNEL_TOTAL_RAM_CODE_FR	"RAM totale"

corefreq-cli-rsc.c

@@ -997,6 +997,9 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_POWER_THERMAL_TPL),
 	LDT(RSC_POWER_THERMAL_EDC),
 	LDT(RSC_POWER_THERMAL_TDC),
+	LDT(RSC_POWER_THERMAL_POINT),
+	LDT(RSC_THERMAL_POINT_THRESHOLD),
+	LDT(RSC_THERMAL_POINT_LIMIT),
 	LDQ(RSC_POWER_LABEL_ODCM),
 	LDQ(RSC_POWER_LABEL_PWM),
 	LDQ(RSC_POWER_LABEL_BIAS),

corefreq-cli-rsc.h

@@ -811,6 +811,9 @@ enum {
 	RSC_POWER_THERMAL_TPL,
 	RSC_POWER_THERMAL_EDC,
 	RSC_POWER_THERMAL_TDC,
+	RSC_POWER_THERMAL_POINT,
+	RSC_THERMAL_POINT_THRESHOLD,
+	RSC_THERMAL_POINT_LIMIT,
 	RSC_POWER_LABEL_ODCM,
 	RSC_POWER_LABEL_PWM,
 	RSC_POWER_LABEL_BIAS,

corefreq-cli.c

@@ -4020,7 +4020,6 @@ REASON_CODE SysInfoPwrThermal(Window *win, CUINT width, CELL_FUNC OutFunc)
 		 - RSZ(POWER_THERMAL_MAX), hSpace,
 		RSC(POWER_LABEL_MAX).CODE(), POWERED(0) );
     }
-    {
 	struct {
 		const ASCII *code;
 		const int size;
@@ -4113,7 +4112,6 @@ REASON_CODE SysInfoPwrThermal(Window *win, CUINT width, CELL_FUNC OutFunc)
 			PL2_Update, pw );
 	  }
 	}
-    }
     if((Shm->Proc.Features.Info.Vendor.CRC == CRC_AMD)
 	 || (Shm->Proc.Features.Info.Vendor.CRC == CRC_HYGON))
     {
@@ -4158,6 +4156,60 @@ REASON_CODE SysInfoPwrThermal(Window *win, CUINT width, CELL_FUNC OutFunc)
 		width - 18 - RSZ(POWER_THERMAL_TDC), hSpace,
 		RSC(POWER_LABEL_TDC).CODE(), POWERED(0) );
     }
+
+	PUT(	SCANKEY_NULL, attrib[0], width, 2, "%s %s",
+		RSC(POWER_LABEL_CORE).CODE(), RSC(POWER_THERMAL_POINT).CODE() );
+
+	enum THM_POINTS tp;
+    for (tp = THM_THRESHOLD_1; tp < THM_POINTS_DIM; tp++)
+    {
+	if (BITVAL(Shm->Cpu[Shm->Proc.Service.Core].ThermalPoint.Mask, tp)
+	  & BITVAL(Shm->Cpu[Shm->Proc.Service.Core].ThermalPoint.State, tp))
+	{
+	ASCII *code;
+	int size;
+	if (BITVAL(Shm->Cpu[Shm->Proc.Service.Core].ThermalPoint.Kind, tp)) {
+		code = RSC(THERMAL_POINT_LIMIT).CODE();
+		size = RSZ(THERMAL_POINT_LIMIT);
+	} else {
+		code = RSC(THERMAL_POINT_THRESHOLD).CODE();
+		size = RSZ(THERMAL_POINT_THRESHOLD);
+	}
+	PUT(	SCANKEY_NULL, attrib[5], width, 3,
+		"%s%.*s%s   [%5u %c]",
+		RSC(POWER_THERMAL_POINT).CODE(),
+		width - (OutFunc == NULL ? 18 : 16)
+		- RSZ(POWER_THERMAL_POINT) - size, hSpace, code,
+		Shm->Cpu[Shm->Proc.Service.Core].ThermalPoint.Value[tp], 'C');
+	}
+    }
+
+	PUT(	SCANKEY_NULL, attrib[0], width, 2, "%s %s",
+		RSC(POWER_LABEL_PKG).CODE(), RSC(POWER_THERMAL_POINT).CODE() );
+
+    for (tp = THM_THRESHOLD_1; tp < THM_POINTS_DIM; tp++)
+    {
+	if (BITVAL(Shm->Proc.ThermalPoint.Mask, tp)
+	  & BITVAL(Shm->Proc.ThermalPoint.State, tp))
+	{
+	ASCII *code;
+	int size;
+	if (BITVAL(Shm->Proc.ThermalPoint.Kind, tp)) {
+		code = RSC(THERMAL_POINT_LIMIT).CODE();
+		size = RSZ(THERMAL_POINT_LIMIT);
+	} else {
+		code = RSC(THERMAL_POINT_THRESHOLD).CODE();
+		size = RSZ(THERMAL_POINT_THRESHOLD);
+	}
+	PUT(	SCANKEY_NULL, attrib[5], width, 3,
+		"%s%.*s%s   [%5u %c]",
+		RSC(POWER_THERMAL_POINT).CODE(),
+		width - (OutFunc == NULL ? 18 : 16)
+		- RSZ(POWER_THERMAL_POINT) - size, hSpace, code,
+		Shm->Proc.ThermalPoint.Value[tp], 'C');
+	}
+    }
+
 	PUT(	SCANKEY_NULL, attrib[0], width, 2,
 		(char*) RSC(POWER_THERMAL_UNITS).CODE(), NULL );
 

corefreq.h

@@ -153,6 +153,8 @@ typedef struct
 		} HWP;
 	} PowerThermal;
 
+	THERMAL_POINT			ThermalPoint;
+
 	struct {
 		struct {
 			double		Limit[SENSOR_LIMITS_DIM];
@@ -445,6 +447,8 @@ typedef struct
 		} Feature;
 	} Power;
 
+	THERMAL_POINT			ThermalPoint;
+
 	signed int			ArchID;
 	enum HYPERVISOR 		HypervisorID;
 	char				Architecture[CODENAME_LEN],

corefreqd.c

@@ -1776,6 +1776,9 @@ void Package_Update(SHM_STRUCT *Shm, RO(PROC) *RO(Proc), RW(PROC) *RW(Proc))
 	PowerInterface(Shm, RO(Proc));
 
 	Mitigation_1st_Stage(Shm, RO(Proc), RW(Proc));
+
+	memcpy(&Shm->Proc.ThermalPoint, &RO(Proc)->ThermalPoint,
+		sizeof(THERMAL_POINT));
 }
 
 typedef struct {
@@ -5654,6 +5657,9 @@ void PowerThermal(SHM_STRUCT *Shm, RO(PROC) *RO(Proc), RO(CORE) **RO(Core),
 
 	Shm->Cpu[cpu].PowerThermal.HWP.Request.Energy_Pref = \
 		RO(Core, AT(cpu))->PowerThermal.HWP_Request.Energy_Pref;
+
+	memcpy(&Shm->Cpu[cpu].ThermalPoint, &RO(Core, AT(cpu))->ThermalPoint,
+		sizeof(THERMAL_POINT));
 }
 
 void SystemRegisters(SHM_STRUCT *Shm, RO(CORE) **RO(Core), unsigned int cpu)