AMD/Zen/UMC

[cyring]

DRAM Power Down Mode

[cyring]

Refactoring DRAM Size Calculation

• Based on https://www.systemverilog.io/design/ddr4-basics/#dram-size-calculation

Matisse

./zencli smu 0x50034
[0x00050034] READ(smu) = 0x00150608 (1377800)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0101 0000 0110 0000 1000

• Decoding the AMD_ZEN_UMC_DRAM_ADDR_CFG register

NumBankGroups = 0b10 -> 4 BG
NumRow = 0b0110 = 10 + 6 -> 1 << 16 = 65536 rows
NumCol = 0b0101 = 5 + 5 -> 1 << 10 = 1024 columns
NumBanks = 0b01 -> 16 banks

---

Rows	Column	ColWidth	BankGroups	Banks
65536	1024	8 (64-bits)	4	16

• DIMM Size (MB)
  Size = Rows x Columns x ColWidth * 4 x BankGroups x Ranks

echo $(( (65536*1024*4*4*8*2)/(1024*1024) ))
16384

Or
Size = Rows x Columns x ColWidth x Banks x Ranks

echo $(( (65536*1024*8*16*2)/(1024*1024) ))
16384

---

Ranks = DIMM Size(B) / ( 8 x Banks x Rows x Columns )

echo $(( 17179869184/(8*16*65536*1024) ))
2

2 ranks

[cyring]

What is Rank register ?

• Dual Channel DDR4 G.Skill F4-3600C16-16GTZN
• DIMM_A2\BANK 1
• DIMM_B2\BANK 3

./zencli umc

Data Fabric: scanning UMC @ BAR[0x00050000] : 0 1 2 3 4 5 6 7 for 2 Channels

CHA[0] CHIP[0:0] @ 0x00050000[0x00000000] Disable, Rank=0
CHA[0] MASK[0:0] @ 0x00050020[0x00000000]
CHA[0] CHIP[0:1] @ 0x00050010[0x00000000] Disable, Rank=0
CHA[0] MASK[0:1] @ 0x00050028[0x00000000]
CHA[0] CHIP[1:0] @ 0x00050004[0x00000000] Disable, Rank=0
CHA[0] MASK[1:0] @ 0x00050020[0x00000000]
CHA[0] CHIP[1:1] @ 0x00050014[0x00000000] Disable, Rank=0
CHA[0] MASK[1:1] @ 0x00050028[0x00000000]
CHA[0] CHIP[2:0] @ 0x00050008[0x00000001] Enable, Rank=2
CHA[0] MASK[2:0] @ 0x00050024[0x03fffdfe] ChipSize[8388608]
CHA[0] CHIP[2:1] @ 0x00050018[0x00000000] Disable, Rank=0
CHA[0] MASK[2:1] @ 0x0005002c[0x00000000]
CHA[0] CHIP[3:0] @ 0x0005000c[0x00000201] Enable, Rank=2
CHA[0] MASK[3:0] @ 0x00050024[0x03fffdfe] ChipSize[8388608]
CHA[0] CHIP[3:1] @ 0x00050018[0x00000000] Disable, Rank=0
CHA[0] MASK[3:1] @ 0x0005002c[0x00000000]

DIMM Size[16777216 KB] [16384 MB]

CHA[1] CHIP[0:0] @ 0x00150000[0x00000000] Disable, Rank=0
CHA[1] MASK[0:0] @ 0x00150020[0x00000000]
CHA[1] CHIP[0:1] @ 0x00150010[0x00000000] Disable, Rank=0
CHA[1] MASK[0:1] @ 0x00150028[0x00000000]
CHA[1] CHIP[1:0] @ 0x00150004[0x00000000] Disable, Rank=0
CHA[1] MASK[1:0] @ 0x00150020[0x00000000]
CHA[1] CHIP[1:1] @ 0x00150014[0x00000000] Disable, Rank=0
CHA[1] MASK[1:1] @ 0x00150028[0x00000000]
CHA[1] CHIP[2:0] @ 0x00150008[0x00000001] Enable, Rank=2
CHA[1] MASK[2:0] @ 0x00150024[0x03fffdfe] ChipSize[8388608]
CHA[1] CHIP[2:1] @ 0x00150018[0x00000000] Disable, Rank=0
CHA[1] MASK[2:1] @ 0x0015002c[0x00000000]
CHA[1] CHIP[3:0] @ 0x0015000c[0x00000201] Enable, Rank=2
CHA[1] MASK[3:0] @ 0x00150024[0x03fffdfe] ChipSize[8388608]
CHA[1] CHIP[3:1] @ 0x00150018[0x00000000] Disable, Rank=0
CHA[1] MASK[3:1] @ 0x0015002c[0x00000000]

DIMM Size[16777216 KB] [16384 MB]

./zencli smu 0x50084
[0x00050084] READ(smu) = 0x00000001 (1)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001

./zencli smu 0x150084
[0x00150084] READ(smu) = 0x00000001 (1)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001

./zencli smu 0x50090
[0x00050090] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

[root@RYZEN C]# ./zencli smu 0x50094
[0x00050094] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

./zencli smu 0x50100
[0x00050100] READ(smu) = 0x80000200 (2147484160)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0010 0000 0000

[root@RYZEN C]# ./zencli smu 0x50104
[0x00050104] READ(smu) = 0xb040808b (2957017227)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1011 0000 0100 0000 1000 0000 1000 1011

./zencli smu 0x150100
[0x00150100] READ(smu) = 0x80000200 (2147484160)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0010 0000 0000

[root@RYZEN C]# ./zencli smu 0x150104
[0x00150104] READ(smu) = 0xb040808b (2957017227)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1011 0000 0100 0000 1000 0000 1000 1011

BurstLength = 0b10

[cyring]

From PPR: BaseAddr: Base Address [39:9] Base address for chipselect decoding.
CSEnable is the disabled/enabled bit

Rank count is a function of the sum of enabled chip with a not null base address