[vm] arm64: add tbl

Needed to improve the performance of Int32x4.shuffle and
Float32x4.shuffle.

Also print the offset of 128-bit SIMD&FP loads and stores scaled by 16,
as the disassembler printed it 16 times too small.

Issue: #64170
Issue: #64345
TEST=vm/cc/Assembler_Tbl1

Change-Id: Icd4a3fb04600aaa28e038d04ef12164e292aa117
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/559001
Commit-Queue: Alexander Aprelev <aam@google.com>
Reviewed-by: Slava Egorov <vegorov@google.com>
Auto-Submit: Modestas Valauskas <valauskasmodestas@gmail.com>
Reviewed-by: Alexander Aprelev <aam@google.com>

Author: modulovalue

runtime/vm/compiler/assembler/assembler_arm64.h

@@ -1568,6 +1568,15 @@ class Assembler : public AssemblerBase {
                              (static_cast<int32_t>(vd) << kVdShift);
     Emit(encoding);
   }
+  // TBL Vd.16B, {Vn.16B}, Vm.16B: byte i of Vd is byte Vm[i] of Vn, or zero
+  // when Vm[i] is 16 or more.
+  void vtbl1(VRegister vd, VRegister vn, VRegister vm) {
+    const int32_t encoding = 0x4E000000 |
+                             (static_cast<int32_t>(vm) << kVmShift) |
+                             (static_cast<int32_t>(vn) << kVnShift) |
+                             (static_cast<int32_t>(vd) << kVdShift);
+    Emit(encoding);
+  }
   // UMINV Sd, Vn.4S: unsigned minimum across the four word lanes of Vn into the
   // 32-bit scalar in the low bits of Vd.
   void vuminv_4s(VRegister vd, VRegister vn) {

runtime/vm/compiler/assembler/assembler_arm64_test.cc

@@ -2407,6 +2407,51 @@ ASSEMBLER_TEST_RUN(Uminv4S, test) {
       "ret\n");
 }
 
+ASSEMBLER_TEST_GENERATE(Tbl1, assembler) {
+  __ fldrq(V1, Address(R0, 0));
+  __ fldrq(V2, Address(R0, 16));
+  __ vtbl1(V0, V1, V2);
+  __ fstrq(V0, Address(R0, 32));
+  __ ret();
+}
+
+ASSEMBLER_TEST_RUN(Tbl1, test) {
+  struct {
+    uint8_t table[16];
+    uint8_t indices[16];
+    uint8_t result[16];
+  } buffer = {{0x85, 0x98, 0xAB, 0xBE, 0xD1, 0xE4, 0xF7, 0x8A, 0x9D, 0xB0, 0xC3,
+               0xD6, 0xE9, 0xFC, 0x8F, 0xA2},
+              {0x0F, 0x00, 0x07, 0x08, 0x10, 0x03, 0xFF, 0x0C, 0x01, 0x0E, 0x80,
+               0x05, 0x0A, 0x1F, 0x06, 0x0B},
+              {0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A,
+               0x5A, 0x5A, 0x5A, 0x5A, 0x5A}};
+  typedef void (*Tbl1Code)(void* buffer) DART_UNUSED;
+  reinterpret_cast<Tbl1Code>(test->entry())(&buffer);
+  EXPECT_EQ(0xA2, buffer.result[0]);
+  EXPECT_EQ(0x85, buffer.result[1]);
+  EXPECT_EQ(0x8A, buffer.result[2]);
+  EXPECT_EQ(0x9D, buffer.result[3]);
+  EXPECT_EQ(0x00, buffer.result[4]);
+  EXPECT_EQ(0xBE, buffer.result[5]);
+  EXPECT_EQ(0x00, buffer.result[6]);
+  EXPECT_EQ(0xE9, buffer.result[7]);
+  EXPECT_EQ(0x98, buffer.result[8]);
+  EXPECT_EQ(0x8F, buffer.result[9]);
+  EXPECT_EQ(0x00, buffer.result[10]);
+  EXPECT_EQ(0xE4, buffer.result[11]);
+  EXPECT_EQ(0xC3, buffer.result[12]);
+  EXPECT_EQ(0x00, buffer.result[13]);
+  EXPECT_EQ(0xF7, buffer.result[14]);
+  EXPECT_EQ(0xD6, buffer.result[15]);
+  EXPECT_DISASSEMBLY(
+      "fldrq v1, [r0]\n"
+      "fldrq v2, [r0, #16]\n"
+      "vtbl1 v0, v1, v2\n"
+      "fstrq v0, [r0, #32]\n"
+      "ret\n");
+}
+
 // Comparisons, branching.
 ASSEMBLER_TEST_GENERATE(BranchALForward, assembler) {
   Label l;

runtime/vm/compiler/assembler/disassembler_arm64.cc

@@ -185,7 +185,9 @@ void ARM64Decoder::PrintMemOperand(Instr* instr) {
   const Register rn = instr->RnField();
   if (instr->Bit(24) == 1) {
     // rn + scaled unsigned 12-bit immediate offset.
-    const uint32_t scale = instr->SzField();
+    const bool is_simd128 = (instr->Bit(26) == 1) && (instr->SzField() == 0) &&
+                            (instr->Bit(23) == 1);
+    const uint32_t scale = is_simd128 ? 4 : instr->SzField();
     const uint32_t imm12 = instr->Imm12Field();
     const uint32_t off = imm12 << scale;
     Print("[");
@@ -1596,6 +1598,11 @@ void ARM64Decoder::DecodeDPSimd1(Instr* instr) {
     Format(instr, "vuminv 'vd, 'vn");
     return;
   }
+  // TBL Vd.16B, {Vn.16B}, Vm.16B (Q=1, len=0, op=0 table lookup form).
+  if ((instr->InstructionBits() & 0xFFE0FC00) == 0x4E000000) {
+    Format(instr, "vtbl1 'vd, 'vn, 'vm");
+    return;
+  }
   if (instr->IsSIMDCopyOp()) {
     DecodeSIMDCopy(instr);
   } else if (instr->IsSIMDThreeSameOp()) {

runtime/vm/simulator_arm64.cc

@@ -3762,6 +3762,25 @@ void Simulator::DecodeDPSimd1(Instr* instr) {
     return;
   }
 
+  // TBL Vd.16B, {Vn.16B}, Vm.16B: byte-wise table lookup.
+  if ((instr->InstructionBits() & 0xFFE0FC00) == 0x4E000000) {
+    const VRegister vd = instr->VdField();
+    const VRegister vn = instr->VnField();
+    const VRegister vm = instr->VmField();
+    int64_t table_bits[2] = {get_vregisterd(vn, 0), get_vregisterd(vn, 1)};
+    int64_t index_bits[2] = {get_vregisterd(vm, 0), get_vregisterd(vm, 1)};
+    const uint8_t* table = reinterpret_cast<const uint8_t*>(&table_bits[0]);
+    const uint8_t* index = reinterpret_cast<const uint8_t*>(&index_bits[0]);
+    int64_t result_bits[2];
+    uint8_t* result = reinterpret_cast<uint8_t*>(&result_bits[0]);
+    for (int i = 0; i < 16; i++) {
+      result[i] = index[i] < 16 ? table[index[i]] : 0;
+    }
+    set_vregisterd(vd, 0, result_bits[0]);
+    set_vregisterd(vd, 1, result_bits[1]);
+    return;
+  }
+
   // UMINV Sd, Vn.4S — unsigned minimum across the four word lanes.
   if ((instr->InstructionBits() & 0xFFFFFC00) == 0x6EB1A800) {
     const VRegister vd = instr->VdField();