[vm] arm64: use rev64 for 32x4 shuffles

Adds REV64 on .4S lanes and lowers shuffle mask 0xB1 (yxwz) to it.

Issue: #64170
Issue: #64345
Issue: #64511
TEST=vm/cc/Assembler_Rev64S
TEST=lib/typed_data/simd_shuffle_all_masks_test

Change-Id: Ideb7bfb87ebfb096b99ff9b424950f3bb61e46df
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/562681
Reviewed-by: Alexander Markov <alexmarkov@google.com>
Reviewed-by: Martin Kustermann <kustermann@google.com>
Auto-Submit: Modestas Valauskas <valauskasmodestas@gmail.com>
Commit-Queue: Martin Kustermann <kustermann@google.com>

Author: modulovalue

runtime/vm/compiler/assembler/assembler_arm64.h

@@ -1580,6 +1580,14 @@ class Assembler : public AssemblerBase {
                              (static_cast<int32_t>(vd) << kVdShift);
     Emit(encoding);
   }
+  // REV64 Vd.4S, Vn.4S: swaps the two 32-bit lanes in each 64-bit half, so
+  // the lanes n0, n1, n2, n3 of Vn become n1, n0, n3, n2.
+  void vrev64_4s(VRegister vd, VRegister vn) {
+    const int32_t encoding = 0x4EA00800 |
+                             (static_cast<int32_t>(vn) << kVnShift) |
+                             (static_cast<int32_t>(vd) << kVdShift);
+    Emit(encoding);
+  }
   // UMINV Sd, Vn.4S: unsigned minimum across the four word lanes of Vn into the
   // 32-bit scalar in the low bits of Vd.
   void vuminv_4s(VRegister vd, VRegister vn) {

runtime/vm/compiler/assembler/assembler_arm64_test.cc

@@ -2452,6 +2452,29 @@ ASSEMBLER_TEST_RUN(Tbl1, test) {
       "ret\n");
 }
 
+ASSEMBLER_TEST_GENERATE(Rev64S, assembler) {
+  __ fldrq(V1, Address(R0, 0));
+  __ vrev64_4s(V0, V1);
+  __ fstrq(V0, Address(R0, 16));
+  __ ret();
+}
+
+ASSEMBLER_TEST_RUN(Rev64S, test) {
+  typedef void (*Rev64SCode)(uint32_t* buffer) DART_UNUSED;
+  uint32_t buffer[8] = {0x01234567, 0x89ABCDEF, 0x76543210, 0xFEDCBA98,
+                        0x5A5A5A5A, 0x5A5A5A5A, 0x5A5A5A5A, 0x5A5A5A5A};
+  reinterpret_cast<Rev64SCode>(test->entry())(buffer);
+  EXPECT_EQ(0x89ABCDEFu, buffer[4]);
+  EXPECT_EQ(0x01234567u, buffer[5]);
+  EXPECT_EQ(0xFEDCBA98u, buffer[6]);
+  EXPECT_EQ(0x76543210u, buffer[7]);
+  EXPECT_DISASSEMBLY(
+      "fldrq v1, [r0]\n"
+      "vrev64s v0, v1\n"
+      "fstrq v0, [r0, #16]\n"
+      "ret\n");
+}
+
 // Comparisons, branching.
 ASSEMBLER_TEST_GENERATE(BranchALForward, assembler) {
   Label l;

runtime/vm/compiler/assembler/disassembler_arm64.cc

@@ -1600,6 +1600,11 @@ void ARM64Decoder::DecodeDPSimd1(Instr* instr) {
     Format(instr, "vuminv 'vd, 'vn");
     return;
   }
+  // REV64 Vd.4S, Vn.4S.
+  if ((instr->InstructionBits() & 0xFFFFFC00) == 0x4EA00800) {
+    Format(instr, "vrev64s 'vd, 'vn");
+    return;
+  }
   // TBL Vd.16B, {Vn.16B}, Vm.16B (Q=1, len=0, op=0 table lookup form).
   if ((instr->InstructionBits() & 0xFFE0FC00) == 0x4E000000) {
     Format(instr, "vtbl1 'vd, 'vn, 'vm");

runtime/vm/compiler/backend/il_arm64.cc

@@ -4001,6 +4001,9 @@ DEFINE_EMIT(Simd32x4Shuffle, (VRegister result, VRegister value)) {
     case 0xFF:  // wwww
       __ vdups(result, value, 3);
       break;
+    case 0xB1:  // yxwz
+      __ vrev64_4s(result, value);
+      break;
     default:
       __ LoadQImmediate(VTMP, ShuffleTableIndices(mask));
       __ vtbl1(result, value, VTMP);

runtime/vm/simulator_arm64.cc

@@ -3773,6 +3773,18 @@ void Simulator::DecodeDPSimd1(Instr* instr) {
     return;
   }
 
+  // REV64 Vd.4S, Vn.4S: swaps the two 32-bit lanes in each 64-bit half.
+  if ((instr->InstructionBits() & 0xFFFFFC00) == 0x4EA00800) {
+    const VRegister vd = instr->VdField();
+    const VRegister vn = instr->VnField();
+    const int32_t res[4] = {get_vregisters(vn, 1), get_vregisters(vn, 0),
+                            get_vregisters(vn, 3), get_vregisters(vn, 2)};
+    for (int i = 0; i < 4; i++) {
+      set_vregisters(vd, i, res[i]);
+    }
+    return;
+  }
+
   // TBL Vd.16B, {Vn.16B}, Vm.16B: byte-wise table lookup.
   if ((instr->InstructionBits() & 0xFFE0FC00) == 0x4E000000) {
     const VRegister vd = instr->VdField();