[vm] arm64: add ushl in its 4S form

Needed to intrinsify Int32x4 operator >>>.

Issue: #64170
Issue: #64345
Issue: #64511
TEST=vm/cc/Assembler_Vushlw

Change-Id: I613b7a776f873ff52e22e1a75395e24c507769b3
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/560561
Reviewed-by: Slava Egorov <vegorov@google.com>
Reviewed-by: Martin Kustermann <kustermann@google.com>
Auto-Submit: Modestas Valauskas <valauskasmodestas@gmail.com>
Commit-Queue: Slava Egorov <vegorov@google.com>

Author: modulovalue

runtime/vm/compiler/assembler/assembler_arm64.h

@@ -1512,6 +1512,9 @@ class Assembler : public AssemblerBase {
   void vsshlx(VRegister vd, VRegister vn, VRegister vm) {
     EmitSIMDThreeSameOp(VSSHLX, vd, vn, vm);
   }
+  void vushlw(VRegister vd, VRegister vn, VRegister vm) {
+    EmitSIMDThreeSameOp(VUSHLW, vd, vn, vm);
+  }
   void vnot(VRegister vd, VRegister vn) { EmitSIMDTwoRegOp(VNOT, vd, vn); }
   void vabss(VRegister vd, VRegister vn) { EmitSIMDTwoRegOp(VABSS, vd, vn); }
   void vabsd(VRegister vd, VRegister vn) { EmitSIMDTwoRegOp(VABSD, vd, vn); }

runtime/vm/compiler/assembler/assembler_arm64_test.cc

@@ -7174,6 +7174,52 @@ ASSEMBLER_TEST_RUN(VsshlxLargeNegativeCount, test) {
       "ret\n");
 }
 
+ASSEMBLER_TEST_GENERATE(Vushlw, assembler) {
+  __ fldrq(V0, Address(R0, 0));
+  __ fldrq(V1, Address(R0, 16));
+  __ vushlw(V2, V0, V1);
+  __ fstrq(V2, Address(R0, 32));
+  __ ret();
+}
+
+ASSEMBLER_TEST_RUN(Vushlw, test) {
+  typedef void (*VushlwCode)(intptr_t) DART_UNUSED;
+  struct {
+    uint32_t values[4];
+    int32_t shifts[4];
+    uint32_t result[4];
+  } buffer;
+  auto check = [&](const uint32_t (&values)[4], const int32_t (&shifts)[4],
+                   const uint32_t (&expected)[4]) {
+    for (intptr_t i = 0; i < 4; i++) {
+      buffer.values[i] = values[i];
+      buffer.shifts[i] = shifts[i];
+      buffer.result[i] = 0xAAAAAAAA;
+    }
+    EXECUTE_TEST_CODE_INTPTR_INTPTR(VushlwCode, test->entry(),
+                                    reinterpret_cast<intptr_t>(&buffer));
+    for (intptr_t i = 0; i < 4; i++) {
+      EXPECT_EQ(expected[i], buffer.result[i]);
+    }
+  };
+  const uint32_t values[4] = {0xFFFFFFF8, 8, 0x80000000, 0x7FFFFFFF};
+  // A positive count shifts left.
+  check(values, {2, 2, 2, 2}, {0xFFFFFFE0, 32, 0, 0xFFFFFFFC});
+  // A negative count shifts right, filling with zeros.
+  check(values, {-1, -1, -1, -1}, {0x7FFFFFFC, 4, 0x40000000, 0x3FFFFFFF});
+  // A shift of 32 or more in either direction shifts every bit out.
+  check(values, {32, 32, 32, 32}, {0, 0, 0, 0});
+  check(values, {-32, -32, -32, -32}, {0, 0, 0, 0});
+  // Each lane uses its own count.
+  check(values, {2, -1, 32, -32}, {0xFFFFFFE0, 4, 0, 0});
+  EXPECT_DISASSEMBLY(
+      "fldrq v0, [r0]\n"
+      "fldrq v1, [r0, #16]\n"
+      "vushlw v2, v0, v1\n"
+      "fstrq v2, [r0, #32]\n"
+      "ret\n");
+}
+
 ASSEMBLER_TEST_GENERATE(Vsubw, assembler) {
   __ LoadImmediate(R4, 31);
   __ LoadImmediate(R5, 10);

runtime/vm/compiler/assembler/disassembler_arm64.cc

@@ -1471,6 +1471,8 @@ void ARM64Decoder::DecodeSIMDThreeSame(Instr* instr) {
     Format(instr, "vceq'vsz 'vd, 'vn, 'vm");
   } else if ((U == 0) && (opcode == 0x8)) {
     Format(instr, "vsshl'vsz 'vd, 'vn, 'vm");
+  } else if ((U == 1) && (opcode == 0x8)) {
+    Format(instr, "vushl'vsz 'vd, 'vn, 'vm");
   } else if ((U == 0) && (opcode == 0x10)) {
     Format(instr, "vadd'vsz 'vd, 'vn, 'vm");
   } else if ((U == 1) && (opcode == 0x10)) {

runtime/vm/constants_arm64.h

@@ -1062,6 +1062,7 @@ enum SIMDThreeSameOp {
   VRSQRTSS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B13 | B12 | B11,
   VSSHLW = SIMDThreeSameFixed | B30 | B23 | B14,
   VSSHLX = SIMDThreeSameFixed | B30 | B23 | B22 | B14,
+  VUSHLW = SIMDThreeSameFixed | B30 | B29 | B23 | B14,
 };
 
 // C.3.6.17

runtime/vm/simulator_arm64.cc

@@ -3351,6 +3351,17 @@ void Simulator::DecodeSIMDThreeSame(Instr* instr) {
           // a copy of the sign bit in every position.
           res = vn_val >> (-shift >= 32 ? 31 : -shift);
         }
+      } else if ((U == 1) && (opcode == 0x8)) {
+        // Format(instr, "vushl'vsz 'vd, 'vn, 'vm");
+        const int8_t shift = static_cast<int8_t>(vm_val & 0xff);
+        const uint32_t vn_bits = static_cast<uint32_t>(vn_val);
+        // A shift of the element width or more, in either direction, shifts
+        // every bit out.
+        if (shift >= 0) {
+          res = shift >= 32 ? 0 : static_cast<int32_t>(vn_bits << shift);
+        } else {
+          res = -shift >= 32 ? 0 : static_cast<int32_t>(vn_bits >> -shift);
+        }
       } else if ((U == 0) && (opcode == 0x10)) {
         // Format(instr, "vadd'vsz 'vd, 'vn, 'vm");
         res = vn_val + vm_val;