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Verilog: allow typedefs as sequence/property identifiers #5545

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Verilog: allow typedefs as sequence/property identifiers

Verilog: allow typedefs as sequence/property identifiers #5545

Run time

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Job Run time
check-ubuntu-24_04-make-gcc
2m 20s
check-vs-2022-make-build-and-test
2m 3s
CentOS 8
1m 11s
Emscripten build
1m 42s
check-ubuntu-24_04-make-clang
2m 45s
check-macos-15-make-clang
1m 54s
check-ubuntu-24_04-make-clang-KNOWNBUG
36s
ebmc-spot
42s
benchmarking
3m 25s
examples
11s
16m 49s