Merge pull request #1541 from diffblue/instance_vs_typedef1

KNOWNBUG test for re-using a typedef as an instance name

Author: tautschnig

regression/verilog/modules/instance_vs_typedef1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+enum_vs_typedef1.sv
+
+^EXIT=10$
+^SIGNAL=0$
+--
+--
+This fails to parse.

regression/verilog/modules/instance_vs_typedef1.sv

@@ -0,0 +1,12 @@
+typedef int some_name;
+
+module main;
+
+  wire a, b, c;
+
+  // The identifier 'some_name' can be re-used in the module scope.
+  // This works with VCS 2023.03, Questa 2024.3, Xcelium 23.09,
+  // Riviera Pro 2023.04, but fails with Icarus Verilog 12.
+  and some_name(a, b, c);
+
+endmodule