Merge pull request #1547 from diffblue/sequence-vs-typedef1-fix

Verilog: allow typedefs as sequence/property identifiers

Author: tautschnig

regression/verilog/SVA/property_vs_typedef1.desc

@@ -1,8 +1,7 @@
-KNOWNBUG
+CORE
 property_vs_typedef1.sv
 
 ^EXIT=10$
 ^SIGNAL=0$
 --
 --
-This fails to parse.

regression/verilog/SVA/sequence_vs_typedef1.desc

@@ -1,8 +1,7 @@
-KNOWNBUG
+CORE
 sequence_vs_typedef1.sv
 
 ^EXIT=10$
 ^SIGNAL=0$
 --
 --
-This fails to parse.

src/verilog/parser.y

@@ -2514,11 +2514,11 @@ assertion_item_declaration:
 	;
 
 property_declaration:
-          TOK_PROPERTY property_identifier property_port_list_paren_opt ';'
+          TOK_PROPERTY any_identifier property_port_list_paren_opt ';'
           property_spec semicolon_opt
           TOK_ENDPROPERTY property_identifier_opt
 		{ init($$, ID_verilog_property_declaration);
-		  stack_expr($$).set(ID_base_name, stack_expr($2).id());
+		  stack_expr($$).set(ID_base_name, stack_expr($2).get(ID_base_name));
 		  mto($$, $5); }
         ;
 
@@ -2706,11 +2706,11 @@ property_case_item:
 
 sequence_declaration:
 	  "sequence" { init($$, ID_verilog_sequence_declaration); }
-	  sequence_identifier sequence_port_list_opt ';'
+	  any_identifier sequence_port_list_opt ';'
 	  sequence_expr semicolon_opt
 	  "endsequence" sequence_identifier_opt
 		{ $$=$2;
-		  stack_expr($$).set(ID_base_name, stack_expr($3).id());
+		  stack_expr($$).set(ID_base_name, stack_expr($3).get(ID_base_name));
 		  mto($$, $6);
 		}
 	;