Ensure NI_Vector128_AsVector128 (aka Vector128<T> AsVector128(this Vector<T> value)) doesn't have a side-effect in its assert (#76460)

tannergooding · web-flow · commit 144a33a01251 · 2022-10-02T09:42:49.000-07:00
* Ensure NI_Vector128_AsVector128 (aka `Vector128&lt;T&gt; AsVector128(this Vector&lt;T&gt; value)`) doesn't have a side-effect in its assert

* CorInfoType no var_types
diff --git a/src/coreclr/jit/hwintrinsicxarch.cpp b/src/coreclr/jit/hwintrinsicxarch.cpp
@@ -702,8 +702,11 @@ GenTree* Compiler::impBaseIntrinsic(NamedIntrinsic        intrinsic,
         {
             assert(sig->numArgs == 1);
             assert(HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic));
-            assert(simdBaseJitType ==
-                   getBaseJitTypeAndSizeOfSIMDType(info.compCompHnd->getArgClass(sig, sig->args), &simdSize));
+
+            CorInfoType op1SimdBaseJitType =
+                getBaseJitTypeAndSizeOfSIMDType(info.compCompHnd->getArgClass(sig, sig->args), &simdSize);
+
+            assert(simdBaseJitType == op1SimdBaseJitType);
 
             switch (getSIMDTypeForSize(simdSize))
             {

Original file line number	Diff line number	Diff line change
`@@ -702,8 +702,11 @@ GenTree* Compiler::impBaseIntrinsic(NamedIntrinsic intrinsic,`
`702`	`702`	`{`
`703`	`703`	`assert(sig->numArgs == 1);`
`704`	`704`	`assert(HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic));`
`705`		`- assert(simdBaseJitType ==`
`706`		`- getBaseJitTypeAndSizeOfSIMDType(info.compCompHnd->getArgClass(sig, sig->args), &simdSize));`
	`705`	`+`
	`706`	`+ CorInfoType op1SimdBaseJitType =`
	`707`	`+ getBaseJitTypeAndSizeOfSIMDType(info.compCompHnd->getArgClass(sig, sig->args), &simdSize);`
	`708`	`+`
	`709`	`+ assert(simdBaseJitType == op1SimdBaseJitType);`
`707`	`710`
`708`	`711`	`switch (getSIMDTypeForSize(simdSize))`
`709`	`712`	`{`