Skip to content

Commit 40063f8

Browse files
jonathandavies-armkunalspathak
jonathandavies-arm
and
kunalspathak
authored
arm64: Rename SVE Prefetch APIs names to use Bit (#115609)
* arm64: Rename SVE Prefetch APIs names to use Bit - Fixes #114909 * Update src/coreclr/jit/hwintrinsiclistarm64sve.h * Update src/coreclr/jit/hwintrinsiclistarm64sve.h * Reorder constants & functions * Remove CompatibilitySuppressions.xml --------- Co-authored-by: Kunal Pathak <[email protected]>
1 parent 236643c commit 40063f8

File tree

12 files changed

+96
-74
lines changed

12 files changed

+96
-74
lines changed

‎src/coreclr/jit/fgdiagnostic.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3458,10 +3458,10 @@ void Compiler::fgDebugCheckFlags(GenTree* tree, BasicBlock* block)
34583458
case NI_Sve_GatherPrefetch32Bit:
34593459
case NI_Sve_GatherPrefetch64Bit:
34603460
case NI_Sve_GatherPrefetch8Bit:
3461-
case NI_Sve_PrefetchBytes:
3462-
case NI_Sve_PrefetchInt16:
3463-
case NI_Sve_PrefetchInt32:
3464-
case NI_Sve_PrefetchInt64:
3461+
case NI_Sve_Prefetch16Bit:
3462+
case NI_Sve_Prefetch32Bit:
3463+
case NI_Sve_Prefetch64Bit:
3464+
case NI_Sve_Prefetch8Bit:
34653465
case NI_Sve_GetFfrByte:
34663466
case NI_Sve_GetFfrInt16:
34673467
case NI_Sve_GetFfrInt32:

‎src/coreclr/jit/gentree.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -28698,10 +28698,6 @@ bool GenTreeHWIntrinsic::OperRequiresCallFlag() const
2869828698

2869928699
#if defined(TARGET_ARM64)
2870028700
case NI_ArmBase_Yield:
28701-
case NI_Sve_PrefetchBytes:
28702-
case NI_Sve_PrefetchInt16:
28703-
case NI_Sve_PrefetchInt32:
28704-
case NI_Sve_PrefetchInt64:
2870528701
case NI_Sve_GatherPrefetch16Bit:
2870628702
case NI_Sve_GatherPrefetch32Bit:
2870728703
case NI_Sve_GatherPrefetch64Bit:
@@ -28714,6 +28710,10 @@ bool GenTreeHWIntrinsic::OperRequiresCallFlag() const
2871428710
case NI_Sve_GetFfrUInt16:
2871528711
case NI_Sve_GetFfrUInt32:
2871628712
case NI_Sve_GetFfrUInt64:
28713+
case NI_Sve_Prefetch16Bit:
28714+
case NI_Sve_Prefetch32Bit:
28715+
case NI_Sve_Prefetch64Bit:
28716+
case NI_Sve_Prefetch8Bit:
2871728717
case NI_Sve_SetFfr:
2871828718
{
2871928719
return true;
@@ -28916,10 +28916,10 @@ void GenTreeHWIntrinsic::Initialize(NamedIntrinsic intrinsicId)
2891628916
case NI_Sve_GatherPrefetch32Bit:
2891728917
case NI_Sve_GatherPrefetch64Bit:
2891828918
case NI_Sve_GatherPrefetch8Bit:
28919-
case NI_Sve_PrefetchBytes:
28920-
case NI_Sve_PrefetchInt16:
28921-
case NI_Sve_PrefetchInt32:
28922-
case NI_Sve_PrefetchInt64:
28919+
case NI_Sve_Prefetch16Bit:
28920+
case NI_Sve_Prefetch32Bit:
28921+
case NI_Sve_Prefetch64Bit:
28922+
case NI_Sve_Prefetch8Bit:
2892328923
case NI_Sve_GetFfrByte:
2892428924
case NI_Sve_GetFfrInt16:
2892528925
case NI_Sve_GetFfrInt32:

‎src/coreclr/jit/hwintrinsicarm64.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -508,10 +508,10 @@ void HWIntrinsicInfo::lookupImmBounds(
508508
case NI_Sve_GatherPrefetch16Bit:
509509
case NI_Sve_GatherPrefetch32Bit:
510510
case NI_Sve_GatherPrefetch64Bit:
511-
case NI_Sve_PrefetchBytes:
512-
case NI_Sve_PrefetchInt16:
513-
case NI_Sve_PrefetchInt32:
514-
case NI_Sve_PrefetchInt64:
511+
case NI_Sve_Prefetch16Bit:
512+
case NI_Sve_Prefetch32Bit:
513+
case NI_Sve_Prefetch64Bit:
514+
case NI_Sve_Prefetch8Bit:
515515
immLowerBound = (int)SVE_PRFOP_PLDL1KEEP;
516516
immUpperBound = (int)SVE_PRFOP_CONST15;
517517
break;
@@ -3182,10 +3182,10 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
31823182
case NI_Sve_GatherPrefetch16Bit:
31833183
case NI_Sve_GatherPrefetch32Bit:
31843184
case NI_Sve_GatherPrefetch64Bit:
3185-
case NI_Sve_PrefetchBytes:
3186-
case NI_Sve_PrefetchInt16:
3187-
case NI_Sve_PrefetchInt32:
3188-
case NI_Sve_PrefetchInt64:
3185+
case NI_Sve_Prefetch16Bit:
3186+
case NI_Sve_Prefetch32Bit:
3187+
case NI_Sve_Prefetch64Bit:
3188+
case NI_Sve_Prefetch8Bit:
31893189
{
31903190
assert((sig->numArgs == 3) || (sig->numArgs == 4));
31913191
assert(!isScalar);

‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1786,10 +1786,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
17861786
break;
17871787
}
17881788

1789-
case NI_Sve_PrefetchBytes:
1790-
case NI_Sve_PrefetchInt16:
1791-
case NI_Sve_PrefetchInt32:
1792-
case NI_Sve_PrefetchInt64:
1789+
case NI_Sve_Prefetch16Bit:
1790+
case NI_Sve_Prefetch32Bit:
1791+
case NI_Sve_Prefetch64Bit:
1792+
case NI_Sve_Prefetch8Bit:
17931793
{
17941794
assert(hasImmediateOperand);
17951795
HWIntrinsicImmOpHelper helper(this, intrin.op3, node);

‎src/coreclr/jit/hwintrinsiclistarm64sve.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -227,10 +227,10 @@ HARDWARE_INTRINSIC(Sve, Not,
227227
HARDWARE_INTRINSIC(Sve, Or, -1, -1, {INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_HasAllMaskVariant)
228228
HARDWARE_INTRINSIC(Sve, OrAcross, -1, -1, {INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_ReduceOperation)
229229
HARDWARE_INTRINSIC(Sve, PopCount, -1, -1, {INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
230-
HARDWARE_INTRINSIC(Sve, PrefetchBytes, -1, 3, {INS_invalid, INS_sve_prfb, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
231-
HARDWARE_INTRINSIC(Sve, PrefetchInt16, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_sve_prfh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
232-
HARDWARE_INTRINSIC(Sve, PrefetchInt32, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
233-
HARDWARE_INTRINSIC(Sve, PrefetchInt64, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfd, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
230+
HARDWARE_INTRINSIC(Sve, Prefetch16Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_sve_prfh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
231+
HARDWARE_INTRINSIC(Sve, Prefetch32Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
232+
HARDWARE_INTRINSIC(Sve, Prefetch64Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfd, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
233+
HARDWARE_INTRINSIC(Sve, Prefetch8Bit, -1, 3, {INS_invalid, INS_sve_prfb, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
234234
HARDWARE_INTRINSIC(Sve, ReciprocalEstimate, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_frecpe, INS_sve_frecpe}, HW_Category_SIMD, HW_Flag_Scalable)
235235
HARDWARE_INTRINSIC(Sve, ReciprocalExponent, -1, -1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_frecpx, INS_sve_frecpx}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
236236
HARDWARE_INTRINSIC(Sve, ReciprocalSqrtEstimate, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_frsqrte, INS_sve_frsqrte}, HW_Category_SIMD, HW_Flag_Scalable)

‎src/coreclr/jit/lowerarmarch.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3820,10 +3820,10 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
38203820
case NI_AdvSimd_ExtractVector128:
38213821
case NI_AdvSimd_StoreSelectedScalar:
38223822
case NI_AdvSimd_Arm64_StoreSelectedScalar:
3823-
case NI_Sve_PrefetchBytes:
3824-
case NI_Sve_PrefetchInt16:
3825-
case NI_Sve_PrefetchInt32:
3826-
case NI_Sve_PrefetchInt64:
3823+
case NI_Sve_Prefetch16Bit:
3824+
case NI_Sve_Prefetch32Bit:
3825+
case NI_Sve_Prefetch64Bit:
3826+
case NI_Sve_Prefetch8Bit:
38273827
case NI_Sve_ExtractVector:
38283828
case NI_Sve_AddRotateComplex:
38293829
case NI_Sve_TrigonometricMultiplyAddCoefficient:

‎src/coreclr/jit/lsraarm64.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1655,10 +1655,10 @@ void LinearScan::BuildHWIntrinsicImmediate(GenTreeHWIntrinsic* intrinsicTree, co
16551655
case NI_AdvSimd_ExtractVector128:
16561656
case NI_AdvSimd_StoreSelectedScalar:
16571657
case NI_AdvSimd_Arm64_StoreSelectedScalar:
1658-
case NI_Sve_PrefetchBytes:
1659-
case NI_Sve_PrefetchInt16:
1660-
case NI_Sve_PrefetchInt32:
1661-
case NI_Sve_PrefetchInt64:
1658+
case NI_Sve_Prefetch16Bit:
1659+
case NI_Sve_Prefetch32Bit:
1660+
case NI_Sve_Prefetch64Bit:
1661+
case NI_Sve_Prefetch8Bit:
16621662
case NI_Sve_ExtractVector:
16631663
case NI_Sve_TrigonometricMultiplyAddCoefficient:
16641664
needBranchTargetReg = !intrin.op3->isContainedIntOrIImmed();
@@ -2356,14 +2356,14 @@ GenTree* LinearScan::getVectorAddrOperand(GenTreeHWIntrinsic* intrinsicTree)
23562356
// Operands that are not loads or stores but do require an address
23572357
switch (intrinsicTree->GetHWIntrinsicId())
23582358
{
2359-
case NI_Sve_PrefetchBytes:
2360-
case NI_Sve_PrefetchInt16:
2361-
case NI_Sve_PrefetchInt32:
2362-
case NI_Sve_PrefetchInt64:
23632359
case NI_Sve_GatherPrefetch8Bit:
23642360
case NI_Sve_GatherPrefetch16Bit:
23652361
case NI_Sve_GatherPrefetch32Bit:
23662362
case NI_Sve_GatherPrefetch64Bit:
2363+
case NI_Sve_Prefetch16Bit:
2364+
case NI_Sve_Prefetch32Bit:
2365+
case NI_Sve_Prefetch64Bit:
2366+
case NI_Sve_Prefetch8Bit:
23672367
if (!varTypeIsSIMD(intrinsicTree->Op(2)->gtType))
23682368
{
23692369
return intrinsicTree->Op(2);

‎src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -7422,22 +7422,13 @@ internal Arm64() { }
74227422
public static Vector<ulong> PopCount(Vector<ulong> value) { throw new PlatformNotSupportedException(); }
74237423

74247424

7425-
// Prefetch bytes
7426-
7427-
/// <summary>
7428-
/// <para>void svprfb(svbool_t pg, const void *base, enum svprfop op)</para>
7429-
/// <para> PRFB op, Pg, [Xbase, #0, MUL VL]</para>
7430-
/// </summary>
7431-
public static unsafe void PrefetchBytes(Vector<byte> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
7432-
7433-
74347425
// Prefetch halfwords
74357426

74367427
/// <summary>
74377428
/// <para>void svprfh(svbool_t pg, const void *base, enum svprfop op)</para>
74387429
/// <para> PRFH op, Pg, [Xbase, #0, MUL VL]</para>
74397430
/// </summary>
7440-
public static unsafe void PrefetchInt16(Vector<ushort> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
7431+
public static unsafe void Prefetch16Bit(Vector<ushort> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
74417432

74427433

74437434
// Prefetch words
@@ -7446,7 +7437,7 @@ internal Arm64() { }
74467437
/// <para>void svprfw(svbool_t pg, const void *base, enum svprfop op)</para>
74477438
/// <para> PRFW op, Pg, [Xbase, #0, MUL VL]</para>
74487439
/// </summary>
7449-
public static unsafe void PrefetchInt32(Vector<uint> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
7440+
public static unsafe void Prefetch32Bit(Vector<uint> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
74507441

74517442

74527443
// Prefetch doublewords
@@ -7455,7 +7446,16 @@ internal Arm64() { }
74557446
/// <para>void svprfd(svbool_t pg, const void *base, enum svprfop op)</para>
74567447
/// <para> PRFD op, Pg, [Xbase, #0, MUL VL]</para>
74577448
/// </summary>
7458-
public static unsafe void PrefetchInt64(Vector<ulong> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
7449+
public static unsafe void Prefetch64Bit(Vector<ulong> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
7450+
7451+
7452+
// Prefetch bytes
7453+
7454+
/// <summary>
7455+
/// <para>void svprfb(svbool_t pg, const void *base, enum svprfop op)</para>
7456+
/// <para> PRFB op, Pg, [Xbase, #0, MUL VL]</para>
7457+
/// </summary>
7458+
public static unsafe void Prefetch8Bit(Vector<byte> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
74597459

74607460

74617461
// Reciprocal estimate

‎src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -7413,22 +7413,13 @@ internal Arm64() { }
74137413
public static Vector<ulong> PopCount(Vector<ulong> value) => PopCount(value);
74147414

74157415

7416-
// Prefetch bytes
7417-
7418-
/// <summary>
7419-
/// <para>void svprfb(svbool_t pg, const void *base, enum svprfop op)</para>
7420-
/// <para> PRFB op, Pg, [Xbase, #0, MUL VL]</para>
7421-
/// </summary>
7422-
public static unsafe void PrefetchBytes(Vector<byte> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchBytes(mask, address, prefetchType);
7423-
7424-
74257416
// Prefetch halfwords
74267417

74277418
/// <summary>
74287419
/// <para>void svprfh(svbool_t pg, const void *base, enum svprfop op)</para>
74297420
/// <para> PRFH op, Pg, [Xbase, #0, MUL VL]</para>
74307421
/// </summary>
7431-
public static unsafe void PrefetchInt16(Vector<ushort> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchInt16(mask, address, prefetchType);
7422+
public static unsafe void Prefetch16Bit(Vector<ushort> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch16Bit(mask, address, prefetchType);
74327423

74337424

74347425
// Prefetch words
@@ -7437,7 +7428,7 @@ internal Arm64() { }
74377428
/// <para>void svprfw(svbool_t pg, const void *base, enum svprfop op)</para>
74387429
/// <para> PRFW op, Pg, [Xbase, #0, MUL VL]</para>
74397430
/// </summary>
7440-
public static unsafe void PrefetchInt32(Vector<uint> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchInt32(mask, address, prefetchType);
7431+
public static unsafe void Prefetch32Bit(Vector<uint> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch32Bit(mask, address, prefetchType);
74417432

74427433

74437434
// Prefetch doublewords
@@ -7446,7 +7437,16 @@ internal Arm64() { }
74467437
/// <para>void svprfd(svbool_t pg, const void *base, enum svprfop op)</para>
74477438
/// <para> PRFD op, Pg, [Xbase, #0, MUL VL]</para>
74487439
/// </summary>
7449-
public static unsafe void PrefetchInt64(Vector<ulong> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchInt64(mask, address, prefetchType);
7440+
public static unsafe void Prefetch64Bit(Vector<ulong> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch64Bit(mask, address, prefetchType);
7441+
7442+
7443+
// Prefetch bytes
7444+
7445+
/// <summary>
7446+
/// <para>void svprfb(svbool_t pg, const void *base, enum svprfop op)</para>
7447+
/// <para> PRFB op, Pg, [Xbase, #0, MUL VL]</para>
7448+
/// </summary>
7449+
public static unsafe void Prefetch8Bit(Vector<byte> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch8Bit(mask, address, prefetchType);
74507450

74517451

74527452
// Reciprocal estimate

0 commit comments

Comments
 (0)