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jonathandavies-armjonathandavies-arm
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arm64: Implement missing SVE extract methods (#116095)
* arm64: Implement missing SVE extract methods * Fixes #115336 * Remove asserts & align intrinsic definitions * Remove HasRMWSemantics from ExtractAfterLastActiveElementScalar
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‎.gitignore

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@@ -363,3 +363,8 @@ src/coreclr/System.Private.CoreLib/common
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.dotnet-daily/
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run-stress-*
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test:.cs
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# XUnit
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*.tempLog.xml
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*.testResults.xml
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*.testStats.csv

‎src/coreclr/jit/hwintrinsicarm64.cpp

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@@ -3284,6 +3284,32 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
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break;
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}
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case NI_Sve_ExtractAfterLastActiveElementScalar:
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case NI_Sve_ExtractLastActiveElementScalar:
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{
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assert(sig->numArgs == 2);
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#ifdef DEBUG
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isValidScalarIntrinsic = true;
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#endif
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CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
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CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
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var_types argType = TYP_UNKNOWN;
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CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
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argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
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op2 = getArgForHWIntrinsic(argType, argClass);
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CorInfoType op2BaseJitType = getBaseJitTypeOfSIMDType(argClass);
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argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
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op1 = getArgForHWIntrinsic(argType, argClass);
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retNode = gtNewScalarHWIntrinsicNode(retType, op1, op2, intrinsic);
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retNode->AsHWIntrinsic()->SetSimdBaseJitType(simdBaseJitType);
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break;
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}
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case NI_Sve_MultiplyAddRotateComplexBySelectedScalar:
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{
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assert(sig->numArgs == 5);

‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp

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@@ -2577,6 +2577,35 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
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break;
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}
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case NI_Sve_ExtractAfterLastActiveElementScalar:
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case NI_Sve_ExtractLastActiveElementScalar:
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{
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opt = emitter::optGetSveInsOpt(emitTypeSize(node->GetSimdBaseType()));
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if (emitter::isGeneralRegisterOrZR(targetReg))
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{
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assert(varTypeIsIntegralOrI(intrin.baseType));
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emitSize = emitTypeSize(node);
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GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt,
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INS_SCALABLE_OPTS_NONE);
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break;
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}
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// FP scalars are processed by the INS_SCALABLE_OPTS_WITH_SIMD_SCALAR variant of the instructions
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FALLTHROUGH;
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}
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case NI_Sve_ExtractAfterLastActiveElement:
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case NI_Sve_ExtractLastActiveElement:
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{
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assert(emitter::isFloatReg(targetReg));
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assert(varTypeIsFloating(node->gtType) || varTypeIsSIMD(node->gtType));
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GetEmitter()->emitInsSve_R_R_R(ins, EA_SCALABLE, targetReg, op1Reg, op2Reg, opt,
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INS_SCALABLE_OPTS_WITH_SIMD_SCALAR);
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break;
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}
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case NI_Sve_TrigonometricMultiplyAddCoefficient:
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{
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assert(isRMW);

‎src/coreclr/jit/hwintrinsiclistarm64sve.h

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@@ -97,6 +97,10 @@ HARDWARE_INTRINSIC(Sve, Divide,
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HARDWARE_INTRINSIC(Sve, DotProduct, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sdot, INS_sve_udot, INS_sve_sdot, INS_sve_udot, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
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HARDWARE_INTRINSIC(Sve, DotProductBySelectedScalar, -1, 4, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sdot, INS_sve_udot, INS_sve_sdot, INS_sve_udot, INS_invalid, INS_invalid}, HW_Category_SIMDByIndexedElement, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_LowVectorOperation)
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HARDWARE_INTRINSIC(Sve, DuplicateSelectedScalarToVector, -1, 2, {INS_sve_dup, INS_sve_dup, INS_sve_dup, INS_sve_dup, INS_sve_dup, INS_sve_dup, INS_sve_dup, INS_sve_dup, INS_sve_dup, INS_sve_dup}, HW_Category_SIMDByIndexedElement, HW_Flag_Scalable|HW_Flag_HasImmediateOperand)
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HARDWARE_INTRINSIC(Sve, ExtractAfterLastActiveElement, -1, 2, {INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_SpecialCodeGen)
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HARDWARE_INTRINSIC(Sve, ExtractAfterLastActiveElementScalar, 0, 2, {INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_SpecialCodeGen|HW_Flag_SpecialImport)
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HARDWARE_INTRINSIC(Sve, ExtractLastActiveElement, -1, 2, {INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_SpecialCodeGen)
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HARDWARE_INTRINSIC(Sve, ExtractLastActiveElementScalar, 0, 2, {INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_SpecialCodeGen|HW_Flag_SpecialImport)
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HARDWARE_INTRINSIC(Sve, ExtractVector, -1, 3, {INS_sve_ext, INS_sve_ext, INS_sve_ext, INS_sve_ext, INS_sve_ext, INS_sve_ext, INS_sve_ext, INS_sve_ext, INS_sve_ext, INS_sve_ext}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SpecialCodeGen)
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HARDWARE_INTRINSIC(Sve, FloatingPointExponentialAccelerator, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fexpa, INS_invalid, INS_sve_fexpa, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg)
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HARDWARE_INTRINSIC(Sve, FusedMultiplyAdd, -1, -1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fmla, INS_sve_fmla}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_FmaIntrinsic|HW_Flag_SpecialCodeGen)

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