|
26 | 26 | #
|
27 | 27 | # a a0
|
28 | 28 | # c all caller-saved registers
|
| 29 | + |
| 30 | +nop: len:4 |
| 31 | +not_reached: len:0 |
| 32 | +not_null: src1:i len:0 |
| 33 | +dummy_use: src1:i len:0 |
| 34 | +il_seq_point: len:0 |
| 35 | +seq_point: len:0 |
| 36 | + |
| 37 | +check_this: src1:b len:4 |
| 38 | +get_ex_obj: dest:i len:4 |
| 39 | +gc_safe_point: src1:i len:12 clob:c |
| 40 | +start_handler: len:8 clob:c |
| 41 | +call_handler: len:4 clob:c |
| 42 | +endfinally: len:32 |
| 43 | +localloc: dest:i src1:i len:52 |
| 44 | +localloc_imm: dest:i len:28 |
| 45 | +generic_class_init: src1:a len:12 clob:c |
| 46 | + |
| 47 | +throw: src1:i len:4 |
| 48 | +rethrow: src1:i len:4 |
| 49 | + |
| 50 | +br: len:4 |
| 51 | +br_reg: src1:i len:4 |
| 52 | +jump_table: dest:i len:16 |
| 53 | +call: dest:a len:4 clob:c |
| 54 | +call_reg: dest:a src1:i len:4 clob:c |
| 55 | +call_membase: dest:a src1:b len:8 clob:c |
| 56 | +voidcall: len:4 clob:c |
| 57 | +voidcall_reg: src1:i len:4 clob:c |
| 58 | +voidcall_membase: src1:b len:8 clob:c |
| 59 | +vcall2: len:16 clob:c |
| 60 | +vcall2_membase: src1:b len:20 clob:c |
| 61 | +fcall: dest:f len:8 clob:c |
| 62 | + |
| 63 | +# Note: in RV32, it shoule be |
| 64 | +# lcall: dest:l ... |
| 65 | +lcall: dest:a len:16 clob:c |
| 66 | +lcall_membase: dest:a src1:b len:8 clob:c |
| 67 | + |
| 68 | +store_membase_reg: dest:b src1:i len:4 |
| 69 | +storei1_membase_reg: dest:b src1:i len:4 |
| 70 | +storei2_membase_reg: dest:b src1:i len:4 |
| 71 | +storei4_membase_reg: dest:b src1:i len:4 |
| 72 | +storei8_membase_reg: dest:b src1:i len:4 |
| 73 | +storer4_membase_reg: dest:b src1:f len:4 |
| 74 | +storer8_membase_reg: dest:b src1:f len:4 |
| 75 | + |
| 76 | +load_membase: dest:i src1:b len:24 |
| 77 | +loadu1_membase: dest:i src1:b len:16 |
| 78 | +loadi1_membase: dest:i src1:b len:16 |
| 79 | +loadu2_membase: dest:i src1:b len:16 |
| 80 | +loadi2_membase: dest:i src1:b len:16 |
| 81 | +loadu4_membase: dest:i src1:b len:16 |
| 82 | +loadi4_membase: dest:i src1:b len:16 |
| 83 | +loadi8_membase: dest:i src1:b len:16 |
| 84 | +loadr4_membase: dest:f src1:b len:16 |
| 85 | +loadr8_membase: dest:f src1:b len:16 |
| 86 | + |
| 87 | +memory_barrier: len:4 |
| 88 | +atomic_add_i4: dest:i src1:i src2:i len:4 |
| 89 | +atomic_store_u1: dest:b src1:i len:8 |
| 90 | +atomic_store_i4: dest:b src1:i len:8 |
| 91 | +atomic_store_u8: dest:b src1:i len:8 |
| 92 | +atomic_load_i4: dest:b src1:i len:12 |
| 93 | +atomic_load_i8: dest:b src1:i len:12 |
| 94 | +atomic_load_u8: dest:b src1:i len:12 |
| 95 | +atomic_cas_i4: dest:i src1:i src2:i src3:i len:24 |
| 96 | +atomic_cas_i8: dest:i src1:i src2:i src3:i len:24 |
| 97 | +atomic_exchange_i4: dest:i src1:i src2:i len:4 |
| 98 | +atomic_exchange_i8: dest:i src1:i src2:i len:4 |
| 99 | + |
| 100 | +move: dest:i src1:i len:4 |
| 101 | +lmove: dest:i src1:i len:4 |
| 102 | +fmove: dest:f src1:f len:4 |
| 103 | +rmove: dest:f src1:f len:4 |
| 104 | + |
| 105 | +iconst: dest:i len:16 |
| 106 | +i8const: dest:i len:16 |
| 107 | +int_add: dest:i src1:i src2:i len:4 |
| 108 | +long_add: dest:i src1:i src2:i len:4 |
| 109 | +int_sub: dest:i src1:i src2:i len:4 |
| 110 | +long_sub: dest:i src1:i src2:i len:4 |
| 111 | +int_mul: dest:i src1:i src2:i len:4 |
| 112 | +float_mul: dest:f src1:f src2:f len:4 |
| 113 | +long_div: dest:i src1:i src2:i len:32 |
| 114 | +long_div_un: dest:i src1:i src2:i len:32 |
| 115 | +int_rem: dest:i src1:i src2:i len:32 |
| 116 | +long_rem: dest:i src1:i src2:i len:32 |
| 117 | +int_rem_un: dest:i src1:i src2:i len:32 |
| 118 | +long_rem_un: dest:i src1:i src2:i len:32 |
| 119 | + |
| 120 | +r4const: dest:f len:16 |
| 121 | +r8const: dest:f len:16 |
| 122 | +int_conv_to_r4: dest:f src1:i len:4 |
| 123 | +int_conv_to_r8: dest:f src1:i len:4 |
| 124 | +r4_conv_to_r8: dest:f src1:f len:4 |
| 125 | +float_conv_to_i4: dest:i src1:f len:4 |
| 126 | +float_conv_to_r4: dest:f src1:f len:4 |
| 127 | +float_ceq: dest:i src1:f src2:f len:4 |
| 128 | +float_clt: dest:i src1:f src2:f len:4 |
| 129 | +float_clt_un: dest:i src1:f src2:f len:4 |
| 130 | + |
| 131 | +add_imm: dest:i src1:i len:4 |
| 132 | +int_add_imm: dest:i src1:i len:4 |
| 133 | +long_add_imm: dest:i src1:i len:4 |
| 134 | + |
| 135 | +and_imm: dest:i src1:i len:4 |
| 136 | +xor_imm: dest:i src1:i len:4 |
| 137 | +shl_imm: dest:i src1:i len:4 |
| 138 | +shr_imm: dest:i src1:i len:4 |
| 139 | +shr_un_imm: dest:i src1:i len:4 |
| 140 | + |
| 141 | +int_and: dest:i src1:i src2:i len:4 |
| 142 | +int_and_imm: dest:i src1:i len:4 |
| 143 | +int_or: dest:i src1:i src2:i len:4 |
| 144 | +int_or_imm: dest:i src1:i len:4 |
| 145 | +int_xor: dest:i src1:i src2:i len:4 |
| 146 | +int_xor_imm: dest:i src1:i len:4 |
| 147 | +int_shl: dest:i src1:i src2:i len:4 |
| 148 | +int_shl_imm: dest:i src1:i len:4 |
| 149 | +int_shr_un: dest:i src1:i src2:i len:4 |
| 150 | +int_shr_imm: dest:i src1:i len:4 |
| 151 | +int_shr_un_imm: dest:i src1:i len:4 |
| 152 | + |
| 153 | +long_and: dest:i src1:i src2:i len:4 |
| 154 | +long_and_imm: dest:i src1:i len:4 |
| 155 | +long_or: dest:i src1:i src2:i len:4 |
| 156 | +long_xor: dest:i src1:i src2:i len:4 |
| 157 | +long_or_imm: dest:i src1:i len:4 |
| 158 | +long_shl_imm: dest:i src1:i len:4 |
| 159 | +long_shr_un: dest:i src1:i src2:i len:4 |
| 160 | +long_shr_imm: dest:i src1:i len:4 |
| 161 | +long_shr_un_imm: dest:i src1:i len:4 |
| 162 | + |
| 163 | + |
| 164 | +riscv_setfreg_r4: dest:f src1:f len:4 |
| 165 | + |
| 166 | +riscv_beq: src1:i src2:i len:8 |
| 167 | +riscv_bne: src1:i src2:i len:8 |
| 168 | +riscv_bge: src1:i src2:i len:8 |
| 169 | +riscv_bgeu: src1:i src2:i len:8 |
| 170 | +riscv_blt: src1:i src2:i len:8 |
| 171 | +riscv_bltu: src1:i src2:i len:8 |
| 172 | +riscv_exc_beq: src1:i src2:i len:32 |
| 173 | +riscv_exc_bne: src1:i src2:i len:32 |
| 174 | +riscv_exc_bgeu: src1:i src2:i len:32 |
| 175 | +riscv_exc_blt: src1:i src2:i len:32 |
| 176 | +riscv_exc_bltu: src1:i src2:i len:32 |
| 177 | +riscv_slt: dest:i src1:i src2:i len:4 |
| 178 | +riscv_sltu: dest:i src1:i src2:i len:4 |
| 179 | +riscv_slti: dest:i src1:i len:4 |
| 180 | +riscv_sltiu: dest:i src1:i len:4 |
| 181 | +riscv_addiw: dest:i src1:i len:4 |
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