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Xinlong-WuXinlong-Wu
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[RISC-V] Port Mono for RISC-V 64 Arch (3/3) IL Lowering & Outputting (#83716)
* IL lowering & output * add blank line at end of file * format
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-9
lines changed

4 files changed

+2024
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‎src/mono/mono/mini/cpu-riscv64.mdesc

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,3 +26,156 @@
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#
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# a a0
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# c all caller-saved registers
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nop: len:4
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not_reached: len:0
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not_null: src1:i len:0
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dummy_use: src1:i len:0
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il_seq_point: len:0
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seq_point: len:0
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check_this: src1:b len:4
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get_ex_obj: dest:i len:4
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gc_safe_point: src1:i len:12 clob:c
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start_handler: len:8 clob:c
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call_handler: len:4 clob:c
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endfinally: len:32
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localloc: dest:i src1:i len:52
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localloc_imm: dest:i len:28
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generic_class_init: src1:a len:12 clob:c
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throw: src1:i len:4
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rethrow: src1:i len:4
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br: len:4
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br_reg: src1:i len:4
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jump_table: dest:i len:16
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call: dest:a len:4 clob:c
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call_reg: dest:a src1:i len:4 clob:c
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call_membase: dest:a src1:b len:8 clob:c
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voidcall: len:4 clob:c
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voidcall_reg: src1:i len:4 clob:c
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voidcall_membase: src1:b len:8 clob:c
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vcall2: len:16 clob:c
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vcall2_membase: src1:b len:20 clob:c
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fcall: dest:f len:8 clob:c
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# Note: in RV32, it shoule be
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# lcall: dest:l ...
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lcall: dest:a len:16 clob:c
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lcall_membase: dest:a src1:b len:8 clob:c
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store_membase_reg: dest:b src1:i len:4
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storei1_membase_reg: dest:b src1:i len:4
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storei2_membase_reg: dest:b src1:i len:4
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storei4_membase_reg: dest:b src1:i len:4
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storei8_membase_reg: dest:b src1:i len:4
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storer4_membase_reg: dest:b src1:f len:4
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storer8_membase_reg: dest:b src1:f len:4
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load_membase: dest:i src1:b len:24
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loadu1_membase: dest:i src1:b len:16
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loadi1_membase: dest:i src1:b len:16
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loadu2_membase: dest:i src1:b len:16
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loadi2_membase: dest:i src1:b len:16
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loadu4_membase: dest:i src1:b len:16
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loadi4_membase: dest:i src1:b len:16
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loadi8_membase: dest:i src1:b len:16
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loadr4_membase: dest:f src1:b len:16
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loadr8_membase: dest:f src1:b len:16
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memory_barrier: len:4
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atomic_add_i4: dest:i src1:i src2:i len:4
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atomic_store_u1: dest:b src1:i len:8
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atomic_store_i4: dest:b src1:i len:8
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atomic_store_u8: dest:b src1:i len:8
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atomic_load_i4: dest:b src1:i len:12
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atomic_load_i8: dest:b src1:i len:12
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atomic_load_u8: dest:b src1:i len:12
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atomic_cas_i4: dest:i src1:i src2:i src3:i len:24
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atomic_cas_i8: dest:i src1:i src2:i src3:i len:24
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atomic_exchange_i4: dest:i src1:i src2:i len:4
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atomic_exchange_i8: dest:i src1:i src2:i len:4
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move: dest:i src1:i len:4
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lmove: dest:i src1:i len:4
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fmove: dest:f src1:f len:4
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rmove: dest:f src1:f len:4
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iconst: dest:i len:16
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i8const: dest:i len:16
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int_add: dest:i src1:i src2:i len:4
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long_add: dest:i src1:i src2:i len:4
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int_sub: dest:i src1:i src2:i len:4
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long_sub: dest:i src1:i src2:i len:4
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int_mul: dest:i src1:i src2:i len:4
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float_mul: dest:f src1:f src2:f len:4
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long_div: dest:i src1:i src2:i len:32
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long_div_un: dest:i src1:i src2:i len:32
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int_rem: dest:i src1:i src2:i len:32
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long_rem: dest:i src1:i src2:i len:32
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int_rem_un: dest:i src1:i src2:i len:32
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long_rem_un: dest:i src1:i src2:i len:32
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r4const: dest:f len:16
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r8const: dest:f len:16
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int_conv_to_r4: dest:f src1:i len:4
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int_conv_to_r8: dest:f src1:i len:4
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r4_conv_to_r8: dest:f src1:f len:4
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float_conv_to_i4: dest:i src1:f len:4
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float_conv_to_r4: dest:f src1:f len:4
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float_ceq: dest:i src1:f src2:f len:4
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float_clt: dest:i src1:f src2:f len:4
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float_clt_un: dest:i src1:f src2:f len:4
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add_imm: dest:i src1:i len:4
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int_add_imm: dest:i src1:i len:4
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long_add_imm: dest:i src1:i len:4
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and_imm: dest:i src1:i len:4
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xor_imm: dest:i src1:i len:4
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shl_imm: dest:i src1:i len:4
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shr_imm: dest:i src1:i len:4
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shr_un_imm: dest:i src1:i len:4
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int_and: dest:i src1:i src2:i len:4
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int_and_imm: dest:i src1:i len:4
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int_or: dest:i src1:i src2:i len:4
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int_or_imm: dest:i src1:i len:4
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int_xor: dest:i src1:i src2:i len:4
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int_xor_imm: dest:i src1:i len:4
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int_shl: dest:i src1:i src2:i len:4
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int_shl_imm: dest:i src1:i len:4
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int_shr_un: dest:i src1:i src2:i len:4
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int_shr_imm: dest:i src1:i len:4
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int_shr_un_imm: dest:i src1:i len:4
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long_and: dest:i src1:i src2:i len:4
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long_and_imm: dest:i src1:i len:4
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long_or: dest:i src1:i src2:i len:4
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long_xor: dest:i src1:i src2:i len:4
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long_or_imm: dest:i src1:i len:4
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long_shl_imm: dest:i src1:i len:4
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long_shr_un: dest:i src1:i src2:i len:4
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long_shr_imm: dest:i src1:i len:4
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long_shr_un_imm: dest:i src1:i len:4
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riscv_setfreg_r4: dest:f src1:f len:4
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riscv_beq: src1:i src2:i len:8
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riscv_bne: src1:i src2:i len:8
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riscv_bge: src1:i src2:i len:8
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riscv_bgeu: src1:i src2:i len:8
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riscv_blt: src1:i src2:i len:8
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riscv_bltu: src1:i src2:i len:8
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riscv_exc_beq: src1:i src2:i len:32
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riscv_exc_bne: src1:i src2:i len:32
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riscv_exc_bgeu: src1:i src2:i len:32
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riscv_exc_blt: src1:i src2:i len:32
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riscv_exc_bltu: src1:i src2:i len:32
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riscv_slt: dest:i src1:i src2:i len:4
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riscv_sltu: dest:i src1:i src2:i len:4
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riscv_slti: dest:i src1:i len:4
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riscv_sltiu: dest:i src1:i len:4
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riscv_addiw: dest:i src1:i len:4

‎src/mono/mono/mini/mini-codegen.c

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -479,7 +479,8 @@ mono_print_ins_index_strbuf (int i, MonoInst *ins)
479479
if (!ins->inst_false_bb)
480480
g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
481481
else
482-
g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
482+
g_string_append_printf (sbuf, " [T:B%d F:B%d]", ins->inst_true_bb->block_num,
483+
ins->inst_false_bb->block_num);
483484
break;
484485
case OP_PHI:
485486
case OP_VPHI:
@@ -683,10 +684,16 @@ mono_print_ins_index_strbuf (int i, MonoInst *ins)
683684
case OP_LBGE_UN:
684685
case OP_LBLE:
685686
case OP_LBLE_UN:
687+
#if defined(TARGET_RISCV64) || defined(TARGET_RISCV32)
688+
case OP_RISCV_BNE:
689+
case OP_RISCV_BEQ:
690+
case OP_RISCV_BGE:
691+
#endif
686692
if (!ins->inst_false_bb)
687693
g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
688694
else
689-
g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
695+
g_string_append_printf (sbuf, " [T:B%d F:B%d]", ins->inst_true_bb->block_num,
696+
ins->inst_false_bb->block_num);
690697
break;
691698
case OP_LIVERANGE_START:
692699
case OP_LIVERANGE_END:
@@ -1827,7 +1834,7 @@ mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
18271834

18281835
sreg_masks [0] &= ~(regmask (hreg));
18291836

1830-
DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1837+
DEBUG (printf ("\tassigned arg ireg %s to R%d\n", mono_arch_regname (hreg), reg));
18311838

18321839
list = g_slist_next (list);
18331840
}
@@ -1845,7 +1852,7 @@ mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
18451852

18461853
assign_reg (cfg, rs, reg, hreg, 1);
18471854

1848-
DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1855+
DEBUG (printf ("\tassigned arg freg %s to R%d\n", mono_regname_full (hreg, 1), reg));
18491856

18501857
list = g_slist_next (list);
18511858
}

‎src/mono/mono/mini/mini-ops.h

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1807,3 +1807,32 @@ MINI_OP(OP_CVT_SI_FP_SCALAR, "convert_si_to_fp_scalar", XREG, XREG, NONE)
18071807
#if defined(TARGET_ARM64) || defined(TARGET_AMD64) || defined(TARGET_WASM)
18081808
MINI_OP3(OP_BSL, "bitwise_select", XREG, XREG, XREG, XREG)
18091809
#endif // TARGET_ARM64 || TARGET_AMD64 || TARGET_WASM
1810+
1811+
#if defined(TARGET_RISCV64) || defined(TARGET_RISCV32)
1812+
MINI_OP(OP_RISCV_EXC_BEQ, "riscv_exc_beq", NONE, IREG, IREG)
1813+
MINI_OP(OP_RISCV_EXC_BNE, "riscv_exc_bne", NONE, IREG, IREG)
1814+
MINI_OP(OP_RISCV_EXC_BGEU, "riscv_exc_bgeu", NONE, IREG, IREG)
1815+
MINI_OP(OP_RISCV_EXC_BLT, "riscv_exc_blt", NONE, IREG, IREG)
1816+
MINI_OP(OP_RISCV_EXC_BLTU, "riscv_exc_bltu", NONE, IREG, IREG)
1817+
1818+
MINI_OP(OP_RISCV_BEQ, "riscv_beq", NONE, IREG, IREG)
1819+
MINI_OP(OP_RISCV_BNE, "riscv_bne", NONE, IREG, IREG)
1820+
MINI_OP(OP_RISCV_BGE, "riscv_bge", NONE, IREG, IREG)
1821+
MINI_OP(OP_RISCV_BGEU, "riscv_bgeu", NONE, IREG, IREG)
1822+
MINI_OP(OP_RISCV_BLT, "riscv_blt", NONE, IREG, IREG)
1823+
MINI_OP(OP_RISCV_BLTU, "riscv_bltu", NONE, IREG, IREG)
1824+
1825+
MINI_OP(OP_RISCV_ADDIW, "riscv_addiw", IREG, IREG, NONE)
1826+
1827+
MINI_OP(OP_RISCV_SLT, "riscv_slt", IREG, IREG, IREG)
1828+
MINI_OP(OP_RISCV_SLTU, "riscv_sltu", IREG, IREG, IREG)
1829+
MINI_OP(OP_RISCV_SLTI, "riscv_slti", IREG, IREG, NONE)
1830+
MINI_OP(OP_RISCV_SLTIU, "riscv_sltiu", IREG, IREG, NONE)
1831+
1832+
// used for cfg->r4fp == FALSE
1833+
MINI_OP(OP_RISCV_SETFREG_R4,"riscv_setfreg_r4", FREG, FREG, NONE)
1834+
#endif
1835+
1836+
#if defined(TARGET_RISCV64)
1837+
MINI_OP(OP_RISCV_ADDUW, "riscv_adduw", IREG, IREG, IREG)
1838+
#endif

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