Fix issue for getting incorrect register type for op2

SwapnilGaikwad · SwapnilGaikwad · commit 7ce466275383 · 2024-06-26T18:33:05.000+01:00
diff --git a/src/coreclr/jit/lsraarm64.cpp b/src/coreclr/jit/lsraarm64.cpp
@@ -1682,7 +1682,14 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree, int* pDstCou
         {
             assert(!isRMW);
 
-            srcCount += BuildOperandUses(intrin.op2, RBM_ASIMD_INDEXED_H_ELEMENT_ALLOWED_REGS.GetFloatRegSet());
+            if (intrin.id == NI_Sve_DuplicateSelectedScalarToVector)
+            {
+                srcCount += BuildOperandUses(intrin.op2);
+            }
+            else
+            {
+                srcCount += BuildOperandUses(intrin.op2, RBM_ASIMD_INDEXED_H_ELEMENT_ALLOWED_REGS.GetFloatRegSet());
+            }
 
             if (intrin.op3 != nullptr)
             {

Original file line number	Diff line number	Diff line change
`@@ -1682,7 +1682,14 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree, int* pDstCou`
`1682`	`1682`	`{`
`1683`	`1683`	`assert(!isRMW);`
`1684`	`1684`
`1685`		`- srcCount += BuildOperandUses(intrin.op2, RBM_ASIMD_INDEXED_H_ELEMENT_ALLOWED_REGS.GetFloatRegSet());`
	`1685`	`+ if (intrin.id == NI_Sve_DuplicateSelectedScalarToVector)`
	`1686`	`+ {`
	`1687`	`+ srcCount += BuildOperandUses(intrin.op2);`
	`1688`	`+ }`
	`1689`	`+ else`
	`1690`	`+ {`
	`1691`	`+ srcCount += BuildOperandUses(intrin.op2, RBM_ASIMD_INDEXED_H_ELEMENT_ALLOWED_REGS.GetFloatRegSet());`
	`1692`	`+ }`
`1686`	`1693`
`1687`	`1694`	`if (intrin.op3 != nullptr)`
`1688`	`1695`	`{`