From 43c34d4a0fb24fac0eeb3b290a0b65de72b9812a Mon Sep 17 00:00:00 2001
From: Hernawan Fa'iz Abdillah <hernawan.faiz@abdillah.me>
Date: Fri, 10 Apr 2020 08:31:38 +0700
Subject: [PATCH 1/3] add pac, alias of esp8266 crate

---
 src/lib.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/lib.rs b/src/lib.rs
index 689b766..4ce237f 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -4,3 +4,4 @@ pub use embedded_hal as ehal;
 pub mod gpio;
 pub mod timer;
 pub mod uart;
+pub use esp8266 as pac;

From e5104ca5735cbc8dcdbf1589e34245abb2edab3d Mon Sep 17 00:00:00 2001
From: Hernawan Fa'iz Abdillah <hernawan.faiz@abdillah.me>
Date: Fri, 10 Apr 2020 08:31:50 +0700
Subject: [PATCH 2/3] add examples/blinky

---
 Cargo.toml         |  3 +++
 examples/blinky.rs | 66 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+)
 create mode 100644 examples/blinky.rs

diff --git a/Cargo.toml b/Cargo.toml
index fd46f1d..9a92b24 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -12,3 +12,6 @@ void = { version = "1.0.2", default-features = false }
 [dependencies.embedded-hal]
 features = ["unproven"]
 version = "0.2.3"
+
+[dev-dependencies]
+xtensa-lx6-rt = { git = "https://github.com/esp-rs/xtensa-lx6-rt", rev = "89cea20c441d4a1624de99c7278df13af5c211a4" }
diff --git a/examples/blinky.rs b/examples/blinky.rs
new file mode 100644
index 0000000..8d6d705
--- /dev/null
+++ b/examples/blinky.rs
@@ -0,0 +1,66 @@
+#![no_std]
+#![no_main]
+#![feature(asm)]
+
+use xtensa_lx6_rt as _;
+
+use core::panic::PanicInfo;
+use esp8266_hal as hal;
+use esp8266_hal::ehal::digital::v2::OutputPin;
+use esp8266_hal::gpio::GpioExt;
+
+/// The default clock source is the onboard crystal
+/// In most cases 40mhz (but can be as low as 2mhz depending on the board)
+const CORE_HZ: u32 = 40_000_000;
+
+#[no_mangle]
+fn main() -> ! {
+    let dp = unsafe { hal::pac::Peripherals::steal() };
+
+    // (https://github.com/espressif/openocd-esp8266/blob/97ba3a6bb9eaa898d91df923bbedddfeaaaf28c9/src/target/esp8266.c#L431)
+    // openocd disables the wdt's on halt
+    // we will do it manually on startup
+    let mut timg = dp.TIMER;
+    disable_timg_wdts(&mut timg);
+
+    let gpios = dp.GPIO.split();
+    let mut led_pin = gpios.gpio2.into_open_drain_output();
+    loop {
+        led_pin.set_high().unwrap();
+        delay(CORE_HZ);
+        led_pin.set_low().unwrap();
+        delay(CORE_HZ);
+    }
+}
+
+fn disable_timg_wdts(timg: &mut esp8266::TIMER) {
+    timg.frc1_ctrl.write(|w| unsafe { w.bits(0x80) });
+    timg.frc2_ctrl.write(|w| unsafe{ w.bits(0x80) });
+}
+
+/// cycle accurate delay using the cycle counter register
+pub fn delay(clocks: u32) {
+    // NOTE: does not account for rollover
+    let target = get_ccount() + clocks;
+    loop {
+        if get_ccount() > target {
+            break;
+        }
+    }
+}
+
+/// Performs a special register read to read the current cycle count.
+/// In the future, this can be precompiled to a archive (.a) and linked to so we don't
+/// have to require the asm nightly feature - see cortex-m-rt for more details
+pub fn get_ccount() -> u32 {
+    let x: u32;
+    unsafe { asm!("rsr.ccount a2" : "={a2}"(x) ) };
+    x
+}
+
+
+/// Basic panic handler - just loops
+#[panic_handler]
+fn panic(_info: &PanicInfo) -> ! {
+    loop {}
+}

From 1133a31543f19988a37bdb7f0c83cf2857326ddc Mon Sep 17 00:00:00 2001
From: Hernawan Fa'iz Abdillah <hernawan.faiz@abdillah.me>
Date: Fri, 10 Apr 2020 08:57:50 +0700
Subject: [PATCH 3/3] fix release linking process

The "crt1-sim.so and _vectors.so not found" error resolved.
But, the CIF not supported on debug build still appeared.
---
 .cargo/config |  9 +++++++++
 build.rs      | 18 ++++++++++++++++++
 memory.x      | 10 ++++++++++
 3 files changed, 37 insertions(+)
 create mode 100644 .cargo/config
 create mode 100644 build.rs
 create mode 100644 memory.x

diff --git a/.cargo/config b/.cargo/config
new file mode 100644
index 0000000..2fca91f
--- /dev/null
+++ b/.cargo/config
@@ -0,0 +1,9 @@
+[target.xtensa-esp32-none-elf]
+runner = "xtensa-esp32-elf-gdb -q -x xtensa.gdb"
+
+[build]
+rustflags = [
+  "-C", "link-arg=-nostartfiles",
+  "-C", "link-arg=-Wl,-Tlink.x",
+]
+target = "xtensa-esp32-none-elf"
diff --git a/build.rs b/build.rs
new file mode 100644
index 0000000..44b26be
--- /dev/null
+++ b/build.rs
@@ -0,0 +1,18 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // Only re-run the build script when memory.x is changed,
+    // instead of when any part of the source code changes.
+    println!("cargo:rerun-if-changed=memory.x");
+}
\ No newline at end of file
diff --git a/memory.x b/memory.x
new file mode 100644
index 0000000..11edaf2
--- /dev/null
+++ b/memory.x
@@ -0,0 +1,10 @@
+/* Specify main memory areas */
+MEMORY
+{
+  /* Use values from the ESP-IDF 'bootloader' component.
+  /* TODO: Use human-readable lengths */
+  /* TODO: Use the full memory map - this is just a test */
+  /* vectors ( RX )       : ORIGIN = 0x40080000, len = 0x400 */
+  iram_seg ( RX )       : ORIGIN = 0x40080400, len = 0xFC00
+  dram_seg ( RW )       : ORIGIN = 0x3FFF0000, len = 0x1000
+}
\ No newline at end of file