From 4d7aed23fd2d92b573a1c4d7020eda2ff13ed510 Mon Sep 17 00:00:00 2001
From: "Earle F. Philhower, III" <earlephilhower@yahoo.com>
Date: Mon, 15 Mar 2021 02:50:13 -0700
Subject: [PATCH] Clean up ICACHE_RAM_ATTR in VM PR
---
cores/esp8266/core_esp8266_vm.cpp | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/cores/esp8266/core_esp8266_vm.cpp b/cores/esp8266/core_esp8266_vm.cpp
index b19360e87f..2a53e69ae2 100644
--- a/cores/esp8266/core_esp8266_vm.cpp
+++ b/cores/esp8266/core_esp8266_vm.cpp
@@ -181,7 +181,7 @@ static void spi_init(spi_regs *spi1)
// So using the command portion of the cycle will not work. Comcatenate the address
// and command into a single 32-bit chunk "address" which will be sent across both bits.
-inline ICACHE_RAM_ATTR void spi_writetransaction(spi_regs *spi1, int addr, int addr_bits, int dummy_bits, int data_bits, iotype dual)
+inline IRAM_ATTR void spi_writetransaction(spi_regs *spi1, int addr, int addr_bits, int dummy_bits, int data_bits, iotype dual)
{
// Ensure no writes are still ongoing
while (spi1->spi_cmd & SPIBUSY) { /* busywait */ }
@@ -198,7 +198,7 @@ inline ICACHE_RAM_ATTR void spi_writetransaction(spi_regs *spi1, int addr, int a
}
}
-inline ICACHE_RAM_ATTR uint32_t spi_readtransaction(spi_regs *spi1, int addr, int addr_bits, int dummy_bits, int data_bits, iotype dual)
+inline IRAM_ATTR uint32_t spi_readtransaction(spi_regs *spi1, int addr, int addr_bits, int dummy_bits, int data_bits, iotype dual)
{
// Ensure no writes are still ongoing
while (spi1->spi_cmd & SPIBUSY) { /* busywait */ }
@@ -214,7 +214,7 @@ inline ICACHE_RAM_ATTR uint32_t spi_readtransaction(spi_regs *spi1, int addr, in
return spi1->spi_w[0];
}
-static inline ICACHE_RAM_ATTR void cache_flushrefill(spi_regs *spi1, int addr)
+static inline IRAM_ATTR void cache_flushrefill(spi_regs *spi1, int addr)
{
addr &= addrmask;
struct cache_line *way = __vm_cache;
@@ -263,7 +263,7 @@ static inline ICACHE_RAM_ATTR void cache_flushrefill(spi_regs *spi1, int addr)
last->addr = addr;
}
-static inline ICACHE_RAM_ATTR void spi_ramwrite(spi_regs *spi1, int addr, int data_bits, uint32_t val)
+static inline IRAM_ATTR void spi_ramwrite(spi_regs *spi1, int addr, int data_bits, uint32_t val)
{
if (cache_ways == 0) {
spi1->spi_w[0] = val;
@@ -280,7 +280,7 @@ static inline ICACHE_RAM_ATTR void spi_ramwrite(spi_regs *spi1, int addr, int da
}
}
-static inline ICACHE_RAM_ATTR uint32_t spi_ramread(spi_regs *spi1, int addr, int data_bits)
+static inline IRAM_ATTR uint32_t spi_ramread(spi_regs *spi1, int addr, int data_bits)
{
if (cache_ways == 0) {
spi1->spi_w[0] = 0;
@@ -298,7 +298,7 @@ static inline ICACHE_RAM_ATTR uint32_t spi_ramread(spi_regs *spi1, int addr, int
static void (*__old_handler)(struct __exception_frame *ef, int cause);
-static ICACHE_RAM_ATTR void loadstore_exception_handler(struct __exception_frame *ef, int cause)
+static IRAM_ATTR void loadstore_exception_handler(struct __exception_frame *ef, int cause)
{
uint32_t excvaddr;
uint32_t insn;