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ledc: Add basic support for esp32c6
1 parent c645c9b commit 9402ab4

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33 files changed

+811
-133
lines changed

33 files changed

+811
-133
lines changed

components/driver/ledc.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -101,8 +101,8 @@ static bool ledc_slow_clk_calibrate(void)
101101
{
102102
if (periph_rtc_dig_clk8m_enable()) {
103103
s_ledc_slow_clk_8M = periph_rtc_dig_clk8m_get_freq();
104-
#if !SOC_CLK_RC_FAST_D256_SUPPORTED
105-
/* Workaround: CLK8M calibration cannot be performed if there is no d256 div clk, we can only use its theoretic freq */
104+
#if !SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
105+
/* Workaround: CLK8M calibration cannot be performed, we can only use its theoretic freq */
106106
ESP_LOGD(LEDC_TAG, "Calibration cannot be performed, approximate CLK8M_CLK : %"PRIu32" Hz", s_ledc_slow_clk_8M);
107107
#else
108108
ESP_LOGD(LEDC_TAG, "Calibrate CLK8M_CLK : %"PRIu32" Hz", s_ledc_slow_clk_8M);
@@ -253,6 +253,10 @@ int duty_val, ledc_duty_direction_t duty_direction, uint32_t duty_num, uint32_t
253253
ledc_hal_set_duty_num(&(p_ledc_obj[speed_mode]->ledc_hal), channel, duty_num);
254254
ledc_hal_set_duty_cycle(&(p_ledc_obj[speed_mode]->ledc_hal), channel, duty_cycle);
255255
ledc_hal_set_duty_scale(&(p_ledc_obj[speed_mode]->ledc_hal), channel, duty_scale);
256+
#if SOC_LEDC_GAMMA_FADE_RANGE_MAX > 1
257+
ledc_hal_set_duty_range(&(p_ledc_obj[speed_mode]->ledc_hal), channel, 0);
258+
ledc_hal_set_range_number(&(p_ledc_obj[speed_mode]->ledc_hal), channel, 1);
259+
#endif
256260
ledc_ls_channel_update(speed_mode, channel);
257261
return ESP_OK;
258262
}

components/driver/test/test_ledc.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,6 @@
2424
#include "soc/io_mux_reg.h"
2525
#include "esp_system.h"
2626
#include "esp_timer.h"
27-
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)
2827
#include "driver/ledc.h"
2928
#include "hal/ledc_ll.h"
3029
#include "driver/gpio.h"
@@ -473,7 +472,7 @@ static void timer_frequency_test(ledc_channel_t channel, ledc_timer_bit_t timer_
473472
.duty_resolution = timer_bit,
474473
.timer_num = timer,
475474
.freq_hz = 5000,
476-
.clk_cfg = LEDC_USE_APB_CLK,
475+
.clk_cfg = TEST_DEFAULT_CLK_CFG,
477476
};
478477
TEST_ESP_OK(ledc_channel_config(&ledc_ch_config));
479478
TEST_ESP_OK(ledc_timer_config(&ledc_time_config));
@@ -536,8 +535,10 @@ TEST_CASE("LEDC timer select specific clock source", "[ledc]")
536535
TEST_ESP_OK(ledc_channel_config(&ledc_ch_config));
537536

538537
if (test_speed_mode == LEDC_LOW_SPEED_MODE) {
538+
#if !CONFIG_IDF_TARGET_ESP32C6 // Temporary. RC_FAST not able to calibrate currently. Can be removed once IDF-5346 done.
539539
printf("Check LEDC_USE_RTC8M_CLK for a 100Hz signal\n");
540540
timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_RTC8M_CLK, 10, 100);
541+
#endif
541542
#if SOC_LEDC_SUPPORT_XTAL_CLOCK
542543
printf("Check LEDC_USE_XTAL_CLK for a 400Hz signal\n");
543544
timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_XTAL_CLK, 13, 400);
@@ -645,4 +646,3 @@ TEST_CASE_MULTIPLE_STAGES("LEDC continue work after software reset", "[ledc]",
645646
ledc_cpu_reset_test_second_stage);
646647

647648
#endif // SOC_PCNT_SUPPORTED
648-
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)

components/esp_hw_support/clk_ctrl_os.c

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,13 @@
66

77
#include <freertos/FreeRTOS.h>
88
#include "clk_ctrl_os.h"
9+
#include "soc/rtc.h"
910
#include "esp_check.h"
10-
#include "sdkconfig.h"
1111

1212
static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
1313

1414
static uint8_t s_periph_ref_counts = 0;
15-
static uint32_t s_rtc_clk_freq = 0; // Frequency of the 8M/256 clock in Hz
15+
static uint32_t s_rc_fast_freq = 0; // Frequency of the RC_FAST clock in Hz
1616
#if SOC_CLK_APLL_SUPPORTED
1717
static const char *TAG = "clk_ctrl_os";
1818
// Current APLL frequency, in HZ. Zero if APLL is not enabled.
@@ -26,13 +26,19 @@ bool periph_rtc_dig_clk8m_enable(void)
2626
portENTER_CRITICAL(&periph_spinlock);
2727
if (s_periph_ref_counts == 0) {
2828
rtc_dig_clk8m_enable();
29+
#if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
2930
#if SOC_CLK_RC_FAST_D256_SUPPORTED
30-
s_rtc_clk_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, 100));
31-
if (s_rtc_clk_freq == 0) {
31+
// If RC_FAST_D256 clock exists, calibration on a slow freq clock is much faster (less slow clock cycles need to wait)
32+
s_rc_fast_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, 100)) << 8; // f_[rc_fast] = f_[rc_fast_d256] * 256;
33+
#else
34+
// Calibrate directly on the RC_FAST clock requires much more slow clock cycles to get an accurate freq value
35+
s_rc_fast_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_RC_FAST, 10000));
36+
#endif
37+
if (s_rc_fast_freq == 0) {
3238
portEXIT_CRITICAL(&periph_spinlock);
3339
return false;
3440
}
35-
#endif
41+
#endif //SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
3642
}
3743
s_periph_ref_counts++;
3844
portEXIT_CRITICAL(&periph_spinlock);
@@ -41,11 +47,11 @@ bool periph_rtc_dig_clk8m_enable(void)
4147

4248
uint32_t periph_rtc_dig_clk8m_get_freq(void)
4349
{
44-
#if !SOC_CLK_RC_FAST_D256_SUPPORTED
45-
/* Workaround: CLK8M calibration cannot be performed if there is no d256 div clk, we can only return its theoretic value */
50+
#if !SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
51+
/* Workaround: CLK8M calibration cannot be performed, we can only return its theoretic value */
4652
return SOC_CLK_RC_FAST_FREQ_APPROX;
4753
#else
48-
return s_rtc_clk_freq * 256;
54+
return s_rc_fast_freq;
4955
#endif
5056
}
5157

@@ -55,7 +61,7 @@ void periph_rtc_dig_clk8m_disable(void)
5561
assert(s_periph_ref_counts > 0);
5662
s_periph_ref_counts--;
5763
if (s_periph_ref_counts == 0) {
58-
s_rtc_clk_freq = 0;
64+
s_rc_fast_freq = 0;
5965
rtc_dig_clk8m_disable();
6066
}
6167
portEXIT_CRITICAL(&periph_spinlock);

components/esp_hw_support/include/clk_ctrl_os.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
#include "soc/rtc.h"
7+
#include <stdbool.h>
88
#include "soc/soc_caps.h"
99
#include "esp_err.h"
1010

@@ -13,18 +13,18 @@ extern "C" {
1313
#endif
1414

1515
/**
16-
* @brief This function is used to enable the digital 8m rtc clock,
16+
* @brief This function is used to enable the digital RC_FAST clock,
1717
* to support the peripherals.
1818
*
1919
* @note If this function is called a number of times, the `periph_rtc_dig_clk8m_disable`
2020
* function needs to be called same times to disable.
2121
*
22-
* @return true: success for enable the rtc 8M clock, false: rtc 8M clock enable failed
22+
* @return true: success for enable the RC_FAST clock, false: RC_FAST clock enable failed
2323
*/
2424
bool periph_rtc_dig_clk8m_enable(void);
2525

2626
/**
27-
* @brief This function is used to disable the rtc digital clock, which should be called
27+
* @brief This function is used to disable the digital RC_FAST clock, which should be called
2828
* with the `periph_rtc_dig_clk8m_enable` pairedly
2929
*
3030
* @note If this function is called a number of times, the `periph_rtc_dig_clk8m_disable`
@@ -33,9 +33,9 @@ bool periph_rtc_dig_clk8m_enable(void);
3333
void periph_rtc_dig_clk8m_disable(void);
3434

3535
/**
36-
* @brief This function is used to get the real clock frequency value of the rtc clock
36+
* @brief This function is used to get the real clock frequency value of RC_FAST clock
3737
*
38-
* @return The real clock value
38+
* @return The real clock value, in Hz
3939
*/
4040
uint32_t periph_rtc_dig_clk8m_get_freq(void);
4141

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