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Isl2017Isl2017
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Merge branch 'debug/fix_deep_sleep_wake_up_by_ble_v5.2' into 'release/v5.2'
fix(ble): fix BLE immediately wakeup deep sleep (v5.2) See merge request espressif/esp-idf!33096
2 parents 68c10bb + 41502db commit fc4abfa

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6 files changed

+179
-86
lines changed

6 files changed

+179
-86
lines changed

‎components/bt/controller/esp32c2/bt.c

Lines changed: 38 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@
4747
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
4848
#include "esp_private/sleep_modem.h"
4949
#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
50+
#include "esp_private/esp_modem_clock.h"
5051

5152
#include "freertos/FreeRTOS.h"
5253
#include "freertos/task.h"
@@ -73,11 +74,6 @@
7374
#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
7475

7576
#define BT_ASSERT_PRINT ets_printf
76-
typedef enum ble_rtc_slow_clk_src {
77-
BT_SLOW_CLK_SRC_MAIN_XTAL,
78-
BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0,
79-
} ble_rtc_slow_clk_src_t;
80-
8177
/* Types definition
8278
************************************************************************
8379
*/
@@ -440,6 +436,7 @@ static bool s_ble_active = false;
440436
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
441437
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
442438
#endif // CONFIG_PM_ENABLE
439+
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
443440

444441
#define BLE_RTC_DELAY_US (1800)
445442

@@ -554,6 +551,20 @@ void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
554551
}
555552
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
556553

554+
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
555+
{
556+
return s_bt_lpclk_src;
557+
}
558+
559+
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
560+
{
561+
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
562+
return;
563+
}
564+
565+
s_bt_lpclk_src = clk_src;
566+
}
567+
557568
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
558569
{
559570
if (!s_ble_active) {
@@ -580,15 +591,15 @@ IRAM_ATTR void controller_wakeup_cb(void *arg)
580591
s_ble_active = true;
581592
}
582593

583-
esp_err_t controller_sleep_init(ble_rtc_slow_clk_src_t slow_clk_src)
594+
esp_err_t controller_sleep_init(modem_clock_lpclk_src_t slow_clk_src)
584595
{
585596
esp_err_t rc = 0;
586597
#ifdef CONFIG_BT_LE_SLEEP_ENABLE
587598
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "BLE modem sleep is enabled\n");
588599
r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US);
589600

590601
#ifdef CONFIG_PM_ENABLE
591-
if (slow_clk_src == BT_SLOW_CLK_SRC_MAIN_XTAL) {
602+
if (slow_clk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
592603
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
593604
} else {
594605
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO);
@@ -643,11 +654,11 @@ void controller_sleep_deinit(void)
643654
#endif //CONFIG_PM_ENABLE
644655
}
645656

646-
static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
657+
static void esp_bt_rtc_slow_clk_select(modem_clock_lpclk_src_t slow_clk_src)
647658
{
648659
/* Select slow clock source for BT momdule */
649660
switch (slow_clk_src) {
650-
case BT_SLOW_CLK_SRC_MAIN_XTAL:
661+
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
651662
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
652663
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
653664
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
@@ -659,7 +670,7 @@ static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
659670
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
660671
#endif // CONFIG_XTAL_FREQ_26
661672
break;
662-
case BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0:
673+
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
663674
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
664675
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
665676
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
@@ -676,40 +687,39 @@ static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
676687
SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S);
677688
}
678689

679-
static ble_rtc_slow_clk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
690+
static modem_clock_lpclk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
680691
{
681-
ble_rtc_slow_clk_src_t slow_clk_src;
682-
692+
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
683693
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
684-
#ifdef CONFIG_XTAL_FREQ_26
685-
cfg->rtc_freq = 40000;
686-
#else
687-
cfg->rtc_freq = 32000;
688-
#endif // CONFIG_XTAL_FREQ_26
689-
slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
694+
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
690695
#else
691-
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
696+
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
697+
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
698+
} else {
699+
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
700+
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
701+
}
702+
#endif // CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
703+
}
704+
705+
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
692706
cfg->rtc_freq = 32768;
693-
slow_clk_src = BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0;
694-
} else {
695-
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
707+
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
696708
#ifdef CONFIG_XTAL_FREQ_26
697709
cfg->rtc_freq = 40000;
698710
#else
699711
cfg->rtc_freq = 32000;
700712
#endif // CONFIG_XTAL_FREQ_26
701-
slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
702713
}
703-
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
704-
esp_bt_rtc_slow_clk_select(slow_clk_src);
705-
return slow_clk_src;
714+
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
715+
return s_bt_lpclk_src;
706716
}
707717

708718
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
709719
{
710720
esp_err_t ret = ESP_OK;
711721
ble_npl_count_info_t npl_info;
712-
ble_rtc_slow_clk_src_t rtc_clk_src;
722+
modem_clock_lpclk_src_t rtc_clk_src;
713723
uint8_t hci_transport_mode;
714724

715725
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));

‎components/bt/controller/esp32c6/bt.c

Lines changed: 56 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -391,6 +391,7 @@ static bool s_ble_active = false;
391391
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
392392
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
393393
#endif // CONFIG_PM_ENABLE
394+
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
394395

395396
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (2500)
396397
#define BLE_RTC_DELAY_US_MODEM_SLEEP (500)
@@ -534,6 +535,20 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
534535
}
535536
}
536537

538+
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
539+
{
540+
return s_bt_lpclk_src;
541+
}
542+
543+
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
544+
{
545+
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
546+
return;
547+
}
548+
549+
s_bt_lpclk_src = clk_src;
550+
}
551+
537552
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
538553
{
539554
if (!s_ble_active) {
@@ -757,12 +772,51 @@ void ble_controller_scan_duplicate_config(void)
757772
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
758773
}
759774

775+
static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
776+
{
777+
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
778+
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
779+
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
780+
#else
781+
#if CONFIG_RTC_CLK_SRC_INT_RC
782+
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
783+
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
784+
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
785+
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
786+
} else {
787+
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
788+
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
789+
}
790+
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
791+
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K;
792+
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
793+
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
794+
#else
795+
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
796+
assert(0);
797+
#endif
798+
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
799+
}
800+
801+
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
802+
cfg->rtc_freq = 100000;
803+
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) {
804+
cfg->rtc_freq = 32768;
805+
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
806+
cfg->rtc_freq = 30000;
807+
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) {
808+
cfg->rtc_freq = 32000;
809+
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
810+
cfg->rtc_freq = 32000;
811+
}
812+
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
813+
}
814+
760815
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
761816
{
762817
uint8_t mac[6];
763818
esp_err_t ret = ESP_OK;
764819
ble_npl_count_info_t npl_info;
765-
uint32_t slow_clk_freq = 0;
766820
uint8_t hci_transport_mode;
767821

768822
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
@@ -814,33 +868,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
814868
modem_clock_module_enable(PERIPH_BT_MODULE);
815869
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
816870
/* Select slow clock source for BT momdule */
817-
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
818-
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
819-
slow_clk_freq = 100000;
820-
#else
821-
#if CONFIG_RTC_CLK_SRC_INT_RC
822-
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
823-
slow_clk_freq = 30000;
824-
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
825-
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
826-
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K);
827-
slow_clk_freq = 32768;
828-
} else {
829-
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
830-
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
831-
slow_clk_freq = 100000;
832-
}
833-
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
834-
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K);
835-
slow_clk_freq = 32000;
836-
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
837-
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K);
838-
slow_clk_freq = 32000;
839-
#else
840-
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
841-
assert(0);
842-
#endif
843-
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
871+
ble_rtc_clk_init(cfg);
844872
esp_phy_modem_init();
845873

846874
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
@@ -873,7 +901,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
873901
}
874902

875903
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
876-
r_esp_ble_change_rtc_freq(slow_clk_freq);
877904

878905
ble_controller_scan_duplicate_config();
879906

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