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static void esp32_cache_state_update (Esp32CacheState * cs );
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static void esp32_cache_data_sync (Esp32CacheRegionState * crs );
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+ static void esp32_cache_invalidate_all_entries (Esp32CacheRegionState * crs );
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static inline uint32_t get_mmu_entry (Esp32CacheRegionState * crs , hwaddr base , hwaddr addr )
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{
@@ -159,7 +160,9 @@ static void esp32_dport_write(void *opaque, hwaddr addr,
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if (FIELD_EX32 (value , DPORT_PRO_CACHE_CTRL , CACHE_FLUSH_ENA )) {
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value |= R_DPORT_PRO_CACHE_CTRL_CACHE_FLUSH_DONE_MASK ;
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value &= ~R_DPORT_PRO_CACHE_CTRL_CACHE_FLUSH_ENA_MASK ;
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+ esp32_cache_invalidate_all_entries (& s -> cache_state [0 ].drom0 );
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esp32_cache_data_sync (& s -> cache_state [0 ].drom0 );
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+ esp32_cache_invalidate_all_entries (& s -> cache_state [0 ].iram0 );
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esp32_cache_data_sync (& s -> cache_state [0 ].iram0 );
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}
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old_val = s -> cache_state [0 ].cache_ctrl_reg ;
@@ -179,7 +182,9 @@ static void esp32_dport_write(void *opaque, hwaddr addr,
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if (FIELD_EX32 (value , DPORT_APP_CACHE_CTRL , CACHE_FLUSH_ENA )) {
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value |= R_DPORT_APP_CACHE_CTRL_CACHE_FLUSH_DONE_MASK ;
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value &= ~R_DPORT_APP_CACHE_CTRL_CACHE_FLUSH_ENA_MASK ;
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+ esp32_cache_invalidate_all_entries (& s -> cache_state [1 ].drom0 );
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esp32_cache_data_sync (& s -> cache_state [1 ].drom0 );
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+ esp32_cache_invalidate_all_entries (& s -> cache_state [1 ].iram0 );
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esp32_cache_data_sync (& s -> cache_state [1 ].iram0 );
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}
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old_val = s -> cache_state [1 ].cache_ctrl_reg ;
@@ -266,6 +271,13 @@ static void esp32_cache_data_sync(Esp32CacheRegionState* crs)
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memory_region_flush_rom_device (& crs -> mem , 0 , ESP32_CACHE_REGION_SIZE );
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}
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+ static void esp32_cache_invalidate_all_entries (Esp32CacheRegionState * crs )
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+ {
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+ for (int i = 0 ; i < ESP32_CACHE_PAGES_PER_REGION ; ++ i ) {
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+ crs -> mmu_table [i ] |= ESP32_CACHE_MMU_ENTRY_CHANGED ;
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+ }
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+ }
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+
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static void esp32_cache_state_update (Esp32CacheState * cs )
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{
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bool cache_enabled = FIELD_EX32 (cs -> cache_ctrl_reg , DPORT_PRO_CACHE_CTRL , CACHE_ENA ) != 0 ;
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