From 372174cc6fc14a1e84e894900fe9f95f205349c9 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 18:26:31 +0200 Subject: [PATCH 01/16] LOCAL: add CI jobs --- .gitlab-ci.yml | 134 ++++++++++++++++++++----------------------------- 1 file changed, 55 insertions(+), 79 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index be57c6a454a5e..77b4531b80f66 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,83 +1,59 @@ -before_script: - - apt-get update -qq - - apt-get install -y -qq flex bison libglib2.0-dev libpixman-1-dev genisoimage +stages: + - build + - deploy -build-system1: - script: - - apt-get install -y -qq libgtk-3-dev libvte-dev nettle-dev libcacard-dev - libusb-dev libvde-dev libspice-protocol-dev libgl1-mesa-dev libvdeplug-dev - - ./configure --enable-werror --target-list="aarch64-softmmu alpha-softmmu - cris-softmmu hppa-softmmu lm32-softmmu moxie-softmmu microblazeel-softmmu - mips64el-softmmu m68k-softmmu ppc-softmmu riscv64-softmmu sparc-softmmu" - - make -j2 - - make -j2 check +variables: + TARGET_LIST: xtensa-softmmu -build-system2: - script: - - apt-get install -y -qq libsdl2-dev libgcrypt-dev libbrlapi-dev libaio-dev - libfdt-dev liblzo2-dev librdmacm-dev libibverbs-dev libibumad-dev - - ./configure --enable-werror --target-list="tricore-softmmu unicore32-softmmu - microblaze-softmmu mips-softmmu riscv32-softmmu s390x-softmmu sh4-softmmu - sparc64-softmmu x86_64-softmmu xtensa-softmmu nios2-softmmu or1k-softmmu" - - make -j2 - - make -j2 check +.use_ci_tools: &use_ci_tools | + curl -sSL ${CIT_LOADER_URL} -o cit_loader.sh && sh cit_loader.sh + source citools/import_functions -build-disabled: - script: - - ./configure --enable-werror --disable-rdma --disable-slirp --disable-curl - --disable-capstone --disable-live-block-migration --disable-glusterfs - --disable-replication --disable-coroutine-pool --disable-smartcard - --disable-guest-agent --disable-curses --disable-libxml2 --disable-tpm - --disable-qom-cast-debug --disable-spice --disable-vhost-vsock - --disable-vhost-net --disable-vhost-crypto --disable-vhost-user - --target-list="i386-softmmu ppc64-softmmu mips64-softmmu i386-linux-user" - - make -j2 - - make -j2 check-qtest SPEED=slow +build-linux: + stage: build + image: $CI_DOCKER_REGISTRY/qemu-build + tags: + - build + - internet + artifacts: + paths: + - dist/qemu-*.tar.bz2 + - dist/archive_name_* + expire_in: 1 week + script: + - ./configure --prefix=/opt/qemu --target-list=${TARGET_LIST} --enable-debug --disable-strip --disable-user --disable-capstone --disable-vnc --disable-sdl --disable-gtk + - make -j8 + - test -z ${CI_COMMIT_TAG} && echo "Not building artifacts archive" && exit 0 + - make install + - find /opt/qemu/share/qemu -maxdepth 1 -mindepth 1 -not -name 'esp*.bin' -exec rm -rf {} \; + - mkdir -p dist + - export DIST_DIR=${PWD}/dist + - export ARCHIVE_NAME=qemu-${CI_COMMIT_TAG}.tar.bz2 + - cd /opt + - tar cjvf ${DIST_DIR}/${ARCHIVE_NAME} qemu + - echo $ARCHIVE_NAME >${DIST_DIR}/archive_name_${CI_JOB_NAME} -build-tcg-disabled: - script: - - apt-get install -y -qq clang libgtk-3-dev libbluetooth-dev libusb-dev - - ./configure --cc=clang --enable-werror --disable-tcg --audio-drv-list="" - - make -j2 - - make check-unit - - make check-qapi-schema - - cd tests/qemu-iotests/ - - ./check -raw 001 002 003 004 005 008 009 010 011 012 021 025 032 033 048 - 052 063 077 086 101 104 106 113 147 148 150 151 152 157 159 160 - 163 170 171 183 184 192 194 197 205 208 215 221 222 226 227 236 - - ./check -qcow2 028 040 051 056 057 058 065 067 068 082 085 091 095 096 102 - 122 124 127 129 132 139 142 144 145 147 151 152 155 157 165 194 - 196 197 200 202 203 205 208 209 215 216 218 222 227 234 246 247 - 248 250 254 255 256 - -build-user: - script: - - ./configure --enable-werror --disable-system --disable-guest-agent - --disable-capstone --disable-slirp --disable-fdt - - make -j2 - - make run-tcg-tests-i386-linux-user run-tcg-tests-x86_64-linux-user - -build-clang: - script: - - apt-get install -y -qq clang libsdl2-dev libattr1-dev libcap-dev - xfslibs-dev libiscsi-dev libnfs-dev libseccomp-dev gnutls-dev librbd-dev - - ./configure --cc=clang --cxx=clang++ --enable-werror - --target-list="alpha-softmmu arm-softmmu m68k-softmmu mips64-softmmu - ppc-softmmu s390x-softmmu x86_64-softmmu arm-linux-user" - - make -j2 - - make -j2 check - -build-tci: - script: - - TARGETS="aarch64 alpha arm hppa m68k microblaze moxie ppc64 s390x x86_64" - - ./configure --enable-tcg-interpreter - --target-list="$(for tg in $TARGETS; do echo -n ${tg}'-softmmu '; done)" - - make -j2 - - make tests/boot-serial-test tests/cdrom-test tests/pxe-test - - for tg in $TARGETS ; do - export QTEST_QEMU_BINARY="${tg}-softmmu/qemu-system-${tg}" ; - ./tests/boot-serial-test || exit 1 ; - ./tests/cdrom-test || exit 1 ; - done - - QTEST_QEMU_BINARY="x86_64-softmmu/qemu-system-x86_64" ./tests/pxe-test - - QTEST_QEMU_BINARY="s390x-softmmu/qemu-system-s390x" ./tests/pxe-test -m slow +upload_to_http: + image: $CI_DOCKER_REGISTRY/qemu-build + stage: deploy + tags: + - deploy + - shiny + when: manual + allow_failure: true + variables: + GIT_STRATEGY: none + only: + - tags + before_script: + - *use_ci_tools + script: + - cit_add_ssh_key "${HTTP_UPLOAD_KEY}" "$(cit_parse_url_host ${HTTP_UPLOAD_DIR})" + # List of archives in dist/ + - FILES=$(find dist -name archive_name_\* -exec cat {} \+) + - cd dist + - scp ${FILES} ${HTTP_UPLOAD_DIR} + # Show info + - /bin/ls -l ${FILES} + - sha256sum ${FILES} + - echo -e "\nArchives were published there:\n\n$(for n in ${FILES}; do echo "${HTTP_PUBLIC_DIR}/${n}"; done)\n" From 7c6cca52c7eeb1993633a93ab2a0d802695ed6ab Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 6 Aug 2019 20:00:06 +0200 Subject: [PATCH 02/16] WIP: LOCAL: make qemu compatible with standard GDB builds --- target/xtensa/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 376a61f3397c6..326012a6eb251 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -180,7 +180,7 @@ static void xtensa_core_class_init(ObjectClass *oc, void *data) * for that: reset bit 0 in the 'flags' field of the registers definitions * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. */ - cc->gdb_num_core_regs = config->gdb_regmap.num_regs; + cc->gdb_num_core_regs = config->gdb_regmap.num_core_regs; } void xtensa_register_core(XtensaConfigList *node) From 84b4260ab74747bb59052230d5873fc5cb2b0814 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 8 Aug 2019 17:21:51 +0200 Subject: [PATCH 03/16] target/xtensa: add stubs for "DFP Accelerator" instructions --- target/xtensa/translate.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index a99f5296e2f4f..b29e6009a557f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2774,6 +2774,12 @@ static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[], tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80); } +static void translate_xur_f64(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + /* no-op */ +} + static void translate_xor(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -5528,6 +5534,24 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_wur_fsr, .par = (const uint32_t[]){FSR}, .coprocessor = 0x1, + }, { + .name = "wur.f64r_lo", + .translate = translate_xur_f64, + }, { + .name = "wur.f64r_hi", + .translate = translate_xur_f64, + }, { + .name = "wur.f64s", + .translate = translate_xur_f64, + }, { + .name = "rur.f64r_lo", + .translate = translate_xur_f64, + }, { + .name = "rur.f64r_hi", + .translate = translate_xur_f64, + }, { + .name = "rur.f64s", + .translate = translate_xur_f64, }, { .name = "wur.threadptr", .translate = translate_wur, From 0bbdd874c27f68b77e7be141d760199dad4bdaac Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:34:12 +0200 Subject: [PATCH 04/16] target/xtensa: add esp32 core configuration --- target/xtensa/Makefile.objs | 1 + target/xtensa/core-esp32.c | 33 + target/xtensa/core-esp32/core-isa.h | 655 + target/xtensa/core-esp32/gdb-config.inc.c | 290 + target/xtensa/core-esp32/xtensa-modules.inc.c | 19196 ++++++++++++++++ 5 files changed, 20175 insertions(+) create mode 100644 target/xtensa/core-esp32.c create mode 100644 target/xtensa/core-esp32/core-isa.h create mode 100644 target/xtensa/core-esp32/gdb-config.inc.c create mode 100644 target/xtensa/core-esp32/xtensa-modules.inc.c diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index c7e7fe6063844..382f936ceaf5c 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -14,3 +14,4 @@ obj-y += fpu_helper.o obj-y += gdbstub.o obj-$(CONFIG_SOFTMMU) += mmu_helper.o obj-y += win_helper.o +obj-$(CONFIG_ESP32) += core-esp32.o diff --git a/target/xtensa/core-esp32.c b/target/xtensa/core-esp32.c new file mode 100644 index 0000000000000..c3b7a9ae3b763 --- /dev/null +++ b/target/xtensa/core-esp32.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/gdbstub.h" +#include "qemu-common.h" +#include "qemu/host-utils.h" + +#include "core-esp32/core-isa.h" +#include "overlay_tool.h" + +#define xtensa_modules xtensa_modules_esp32 +#include "core-esp32/xtensa-modules.inc.c" + +static XtensaConfig xtensa_core_esp32 __attribute__((unused)) = { + .name = "esp32", + .gdb_regmap = { + .reg = { +#include "core-esp32/gdb-config.inc.c" + } + }, + .isa_internal = &xtensa_modules, + .clock_freq_khz = 40000, + DEFAULT_SECTIONS +}; + +REGISTER_CORE(xtensa_core_esp32) diff --git a/target/xtensa/core-esp32/core-isa.h b/target/xtensa/core-esp32/core-isa.h new file mode 100644 index 0000000000000..f3f4e45f001f8 --- /dev/null +++ b/target/xtensa/core-esp32/core-isa.h @@ -0,0 +1,655 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Copyright (c) 1999-2016 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1100003 /* sw version of this header */ + +#define XCHAL_CORE_ID "esp32_v3_49_prod" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x0005FE96 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC2BCFFFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1CC5FE96 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 260003 /* major*100+minor */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_3 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ +#define XCHAL_HAVE_AXI 0 /* AXI bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 1 +#define XCHAL_DCACHE_WAYS 1 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 1 +#define XCHAL_DCACHE_ACCESS_SIZE 1 + +#define XCHAL_DCACHE_BANKS 0 /* number of banks */ + +/* Number of encoded cache attr bits (see for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ + +/* Instruction ROM 0: */ +#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */ +#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */ +#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 1: */ +#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */ +#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */ +#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Data ROM 0: */ +#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */ +#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */ +#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATAROM0_BANKS 1 /* number of banks */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ + +/* XLMI Port 0: */ +#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */ +#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */ +#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */ +#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x000637FF +#define XCHAL_INTLEVEL2_MASK 0x00380000 +#define XCHAL_INTLEVEL3_MASK 0x28C08800 +#define XCHAL_INTLEVEL4_MASK 0x53000000 +#define XCHAL_INTLEVEL5_MASK 0x84010000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 1 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 1 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_INT13_LEVEL 1 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 3 +#define XCHAL_INT16_LEVEL 5 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 2 +#define XCHAL_INT20_LEVEL 2 +#define XCHAL_INT21_LEVEL 2 +#define XCHAL_INT22_LEVEL 3 +#define XCHAL_INT23_LEVEL 3 +#define XCHAL_INT24_LEVEL 4 +#define XCHAL_INT25_LEVEL 4 +#define XCHAL_INT26_LEVEL 5 +#define XCHAL_INT27_LEVEL 3 +#define XCHAL_INT28_LEVEL 4 +#define XCHAL_INT29_LEVEL 3 +#define XCHAL_INT30_LEVEL 4 +#define XCHAL_INT31_LEVEL 5 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F +#define XCHAL_INTTYPE_MASK_TIMER 0x00018040 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ +#define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL7_NUM 14 +/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ +#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ +#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ +#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ +#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ +#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ +#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ +#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ +#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ +#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ +#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ +#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ +#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ +#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ +#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ +#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ +#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ +#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ +#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ +#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ +#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ +#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ +#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x40000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x50000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000400 +#define XCHAL_RESET_VECTOR_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR_PADDR 0x40000400 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0x40000340 +#define XCHAL_USER_VECTOR_PADDR 0x40000340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0x400002C0 +#define XCHAL_NMI_VECTOR_PADDR 0x400002C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/target/xtensa/core-esp32/gdb-config.inc.c b/target/xtensa/core-esp32/gdb-config.inc.c new file mode 100644 index 0000000000000..cf4d7c94cb025 --- /dev/null +++ b/target/xtensa/core-esp32/gdb-config.inc.c @@ -0,0 +1,290 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2016 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, 0,0,0,0,0,0) + XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, 0,0,0,0,0,0) + XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, 0,0,0,0,0,0) + XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, 0,0,0,0,0,0) + XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, 0,0,0,0,0,0) + XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, 0,0,0,0,0,0) + XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, 0,0,0,0,0,0) + XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, 0,0,0,0,0,0) + XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, 0,0,0,0,0,0) + XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, 0,0,0,0,0,0) + XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, 0,0,0,0,0,0) + XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, 0,0,0,0,0,0) + XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, 0,0,0,0,0,0) + XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, 0,0,0,0,0,0) + XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, 0,0,0,0,0,0) + XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, 0,0,0,0,0,0) + XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, 0,0,0,0,0,0) + XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, 0,0,0,0,0,0) + XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, 0,0,0,0,0,0) + XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, 0,0,0,0,0,0) + XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, 0,0,0,0,0,0) + XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, 0,0,0,0,0,0) + XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, 0,0,0,0,0,0) + XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, 0,0,0,0,0,0) + XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, 0,0,0,0,0,0) + XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, 0,0,0,0,0,0) + XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, 0,0,0,0,0,0) + XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 69,276, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 70,280,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 71,284,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 72,288,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 73,292,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 74,296,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) + XTREG( 75,300,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 76,304,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) + XTREG( 77,308,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0) + XTREG( 78,312, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0) + XTREG( 79,316,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0) + XTREG( 80,320,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0) + XTREG( 81,324,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0) + XTREG( 82,328,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0) + XTREG( 83,332,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) + XTREG( 84,336,32, 4, 4,0x03ea,0x0006,-1, 3,0x0100,f64r_lo, 0,0,0,0,0,0) + XTREG( 85,340,32, 4, 4,0x03eb,0x0006,-1, 3,0x0100,f64r_hi, 0,0,0,0,0,0) + XTREG( 86,344,32, 4, 4,0x03ec,0x0006,-1, 3,0x0110,f64s, 0,0,0,0,0,0) + XTREG( 87,348,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0, + "03:03:44:00","03:03:04:00",0,0,0,0) + XTREG( 88,352,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1, + "03:13:44:00","03:13:04:00",0,0,0,0) + XTREG( 89,356,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2, + "03:23:44:00","03:23:04:00",0,0,0,0) + XTREG( 90,360,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3, + "03:33:44:00","03:33:04:00",0,0,0,0) + XTREG( 91,364,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4, + "03:43:44:00","03:43:04:00",0,0,0,0) + XTREG( 92,368,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5, + "03:53:44:00","03:53:04:00",0,0,0,0) + XTREG( 93,372,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6, + "03:63:44:00","03:63:04:00",0,0,0,0) + XTREG( 94,376,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7, + "03:73:44:00","03:73:04:00",0,0,0,0) + XTREG( 95,380,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8, + "03:83:44:00","03:83:04:00",0,0,0,0) + XTREG( 96,384,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9, + "03:93:44:00","03:93:04:00",0,0,0,0) + XTREG( 97,388,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10, + "03:a3:44:00","03:a3:04:00",0,0,0,0) + XTREG( 98,392,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11, + "03:b3:44:00","03:b3:04:00",0,0,0,0) + XTREG( 99,396,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12, + "03:c3:44:00","03:c3:04:00",0,0,0,0) + XTREG(100,400,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13, + "03:d3:44:00","03:d3:04:00",0,0,0,0) + XTREG(101,404,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14, + "03:e3:44:00","03:e3:04:00",0,0,0,0) + XTREG(102,408,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15, + "03:f3:44:00","03:f3:04:00",0,0,0,0) + XTREG(103,412,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0) + XTREG(104,416,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0) + XTREG(105,420,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG(106,424, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG(107,428, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0) + XTREG(108,432, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG(109,436,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG(110,440,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG(111,444,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG(112,448,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG(113,452,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG(114,456,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG(115,460,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG(116,464,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG(117,468,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG(118,472,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG(119,476,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG(120,480,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG(121,484,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) + XTREG(122,488,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) + XTREG(123,492,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG(124,496,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG(125,500,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG(126,504,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG(127,508,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG(128,512,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) + XTREG(129,516,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) + XTREG(130,520,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG(131,524,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG(132,528,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG(133,532,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG(134,536,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG(135,540,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) + XTREG(136,544,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) + XTREG(137,548, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG(138,552,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG(139,556,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG(140,560,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG(141,564,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG(142,568,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG(143,572, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG(144,576,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG(145,580,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG(146,584,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG(147,588,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG(148,592, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG(149,596,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG(150,600,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG(151,604,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG(152,608,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) + XTREG(153,612,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG(154,616,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG(155,620,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2, 0,0,0,0,0,0) + XTREG(156,624,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3, 0,0,0,0,0,0) + XTREG(157,628,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) + XTREG(158,632,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) + XTREG(159,636,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) + XTREG(160,640,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) + XTREG(161,644,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) + XTREG(162,648,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) + XTREG(163,652,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) + XTREG(164,656,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) + XTREG(165,660,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) + XTREG(166,664,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) + XTREG(167,668,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) + XTREG(168,672,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) + XTREG(169,676,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) + XTREG(170,680,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) + XTREG(171,684,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) + XTREG(172,688,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) + XTREG(173,692, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(174,693, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(175,694, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(176,695, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(177,696, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(178,697, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(179,698, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(180,699, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(181,700, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(182,701, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(183,702, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(184,703, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(185,704, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(186,705, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(187,706, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(188,707, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(189,708, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask16,0,0,0) + XTREG(190,712, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask17,0,0,0) + XTREG(191,716, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask18,0,0,0) + XTREG(192,720, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask19,0,0,0) + XTREG(193,724, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask20,0,0,0) + XTREG(194,728, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask21,0,0,0) + XTREG(195,732,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc, + 0,0,&xtensa_mask22,0,0,0) + XTREG(196,740, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask23,0,0,0) + XTREG(197,744,64, 8, 4,0x2015,0x0006,-2, 5,0x1010,f64r, + 0,0,&xtensa_mask24,0,0,0) + XTREG(198,752, 2, 4, 4,0x2016,0x0006, 0, 5,0x1010,roundmode, + 0,0,&xtensa_mask25,0,0,0) + XTREG(199,756, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,invalidenable, + 0,0,&xtensa_mask26,0,0,0) + XTREG(200,760, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,divzeroenable, + 0,0,&xtensa_mask27,0,0,0) + XTREG(201,764, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,overflowenable, + 0,0,&xtensa_mask28,0,0,0) + XTREG(202,768, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,underflowenable, + 0,0,&xtensa_mask29,0,0,0) + XTREG(203,772, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,inexactenable, + 0,0,&xtensa_mask30,0,0,0) + XTREG(204,776, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,invalidflag, + 0,0,&xtensa_mask31,0,0,0) + XTREG(205,780, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,divzeroflag, + 0,0,&xtensa_mask32,0,0,0) + XTREG(206,784, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,overflowflag, + 0,0,&xtensa_mask33,0,0,0) + XTREG(207,788, 1, 4, 4,0x201f,0x0006, 0, 5,0x1010,underflowflag, + 0,0,&xtensa_mask34,0,0,0) + XTREG(208,792, 1, 4, 4,0x2020,0x0006, 0, 5,0x1010,inexactflag, + 0,0,&xtensa_mask35,0,0,0) + XTREG(209,796,20, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved20, + 0,0,&xtensa_mask36,0,0,0) + XTREG(210,800,20, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved20a, + 0,0,&xtensa_mask37,0,0,0) + XTREG(211,804, 5, 4, 4,0x2023,0x0006, 0, 5,0x1010,fpreserved5, + 0,0,&xtensa_mask38,0,0,0) + XTREG_END diff --git a/target/xtensa/core-esp32/xtensa-modules.inc.c b/target/xtensa/core-esp32/xtensa-modules.inc.c new file mode 100644 index 0000000000000..09121cb132f1e --- /dev/null +++ b/target/xtensa/core-esp32/xtensa-modules.inc.c @@ -0,0 +1,19196 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2016 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "MEMCTL", 97, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "MISC2", 246, 0 }, + { "MISC3", 247, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "F64R_LO", 234, 1 }, + { "F64R_HI", 235, 1 }, + { "F64S", 236, 1 }, + { "FCR", 232, 1 }, + { "FSR", 233, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 75 +#define MAX_SPECIAL_REG 247 +#define MAX_USER_REG 236 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 32, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EXCSAVE7", 32, 0 }, + { "EPS2", 13, 0 }, + { "EPS3", 13, 0 }, + { "EPS4", 13, 0 }, + { "EPS5", 13, 0 }, + { "EPS6", 13, 0 }, + { "EPS7", 13, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 4, 0 }, + { "WindowStart", 16, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "MEMCTL", 1, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "MISC2", 32, 0 }, + { "MISC3", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 32, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "CPENABLE", 8, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "F64R", 64, 0 }, + { "F64S", 32, 0 }, + { "RoundMode", 2, 0 }, + { "InvalidEnable", 1, 0 }, + { "DivZeroEnable", 1, 0 }, + { "OverflowEnable", 1, 0 }, + { "UnderflowEnable", 1, 0 }, + { "InexactEnable", 1, 0 }, + { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "FPreserved20", 20, 0 }, + { "FPreserved20a", 20, 0 }, + { "FPreserved5", 5, 0 }, + { "FPreserved7", 7, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 86 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EPC7, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EXCSAVE7, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EPS7, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_MEMCTL, + STATE_SAR, + STATE_THREADPTR, + STATE_MISC0, + STATE_MISC1, + STATE_MISC2, + STATE_MISC3, + STATE_ACC, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_CPENABLE, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_F64R, + STATE_F64S, + STATE_RoundMode, + STATE_InvalidEnable, + STATE_DivZeroEnable, + STATE_OverflowEnable, + STATE_UnderflowEnable, + STATE_InexactEnable, + STATE_InvalidFlag, + STATE_DivZeroFlag, + STATE_OverflowFlag, + STATE_UnderflowFlag, + STATE_InexactFlag, + STATE_FPreserved20, + STATE_FPreserved20a, + STATE_FPreserved5, + STATE_FPreserved7, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dfp_fld_op2_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_op2_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dfp_fld_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_dfp_fld_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dfp_fld_op2_3_2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_op2_3_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dfp_fld_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dfp_fld_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_dfp_fld_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dfp_fld_op2_3_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_op2_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_dfp_fld_r_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dfp_fld_r_0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dfp_fld_r_0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_3_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dfp_fld_r_3_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_s_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_s_0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_s_0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_op2_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_op2_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dfp_fld_op2_1_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_op2_1_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_dfp_fld_op2_2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_op2_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_r3, + FIELD_rbit2, + FIELD_rhi, + FIELD_t3, + FIELD_tbit2, + FIELD_tlo, + FIELD_w, + FIELD_y, + FIELD_x, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_s8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_dfp_fld_op1, + FIELD_dfp_fld_op2, + FIELD_dfp_fld_r_0, + FIELD_dfp_fld_r_2_1, + FIELD_dfp_fld_r_3, + FIELD_dfp_fld_r_3_1, + FIELD_dfp_fld_s_0, + FIELD_dfp_fld_s_3_1, + FIELD_dfp_fld_op2_0, + FIELD_dfp_fld_op2_1_0, + FIELD_dfp_fld_op2_2, + FIELD_dfp_fld_op2_3, + FIELD_dfp_fld_op2_3_2, + FIELD_dfp_fld_op2_3_1, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__mr0, + FIELD__mr1, + FIELD__mr2, + FIELD__mr3, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +#define funcUnits 0 + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_MR, + REGFILE_BR, + REGFILE_FR, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 64 }, + { "MR", "m", REGFILE_MR, 32, 4 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "FR", "f", REGFILE_FR, 32, 16 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "ERI_RD_Out", 14, 0, 0, 'o' }, + { "ERI_RD_In", 32, 0, 1, 'i' }, + { "ERI_RD_Rdy", 1, 0, 0, 'i' }, + { "ERI_WR_Out", 46, 0, 2, 'o' }, + { "ERI_WR_In", 1, 0, 3, 'i' }, + { "IMPWIRE", 32, 0, 4, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In, + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table RECIP_Data8 */ +static const unsigned CONST_TBL_RECIP_Data8_0[] = { + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf5 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf0 & 0xff, + 0xee & 0xff, + 0xed & 0xff, + 0xeb & 0xff, + 0xe9 & 0xff, + 0xe8 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xde & 0xff, + 0xdd & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd1 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb1 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xad & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa4 & 0xff, + 0xa3 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0 +}; + +/* constant table RSQRT_Data8 */ +static const unsigned CONST_TBL_RSQRT_Data8_0[] = { + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x80 & 0xff, + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf6 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf1 & 0xff, + 0xef & 0xff, + 0xed & 0xff, + 0xec & 0xff, + 0xea & 0xff, + 0xe9 & 0xff, + 0xe7 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xdf & 0xff, + 0xdd & 0xff, + 0xdc & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd6 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd2 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xce & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc9 & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc3 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0 +}; + +/* constant table RECIP_Data10_2 */ +static const unsigned CONST_TBL_RECIP_Data10_2_0[] = { + 0x3fc & 0x3ff, + 0x3f4 & 0x3ff, + 0x3ec & 0x3ff, + 0x3e5 & 0x3ff, + 0x3dd & 0x3ff, + 0x3d6 & 0x3ff, + 0x3cf & 0x3ff, + 0x3c7 & 0x3ff, + 0x3c0 & 0x3ff, + 0x3b9 & 0x3ff, + 0x3b2 & 0x3ff, + 0x3ac & 0x3ff, + 0x3a5 & 0x3ff, + 0x39e & 0x3ff, + 0x398 & 0x3ff, + 0x391 & 0x3ff, + 0x38b & 0x3ff, + 0x385 & 0x3ff, + 0x37f & 0x3ff, + 0x378 & 0x3ff, + 0x373 & 0x3ff, + 0x36c & 0x3ff, + 0x367 & 0x3ff, + 0x361 & 0x3ff, + 0x35c & 0x3ff, + 0x356 & 0x3ff, + 0x350 & 0x3ff, + 0x34b & 0x3ff, + 0x345 & 0x3ff, + 0x340 & 0x3ff, + 0x33b & 0x3ff, + 0x335 & 0x3ff, + 0x330 & 0x3ff, + 0x32c & 0x3ff, + 0x327 & 0x3ff, + 0x322 & 0x3ff, + 0x31c & 0x3ff, + 0x318 & 0x3ff, + 0x314 & 0x3ff, + 0x30e & 0x3ff, + 0x30a & 0x3ff, + 0x306 & 0x3ff, + 0x300 & 0x3ff, + 0x2fc & 0x3ff, + 0x2f8 & 0x3ff, + 0x2f4 & 0x3ff, + 0x2f0 & 0x3ff, + 0x2ea & 0x3ff, + 0x2e6 & 0x3ff, + 0x2e2 & 0x3ff, + 0x2de & 0x3ff, + 0x2da & 0x3ff, + 0x2d6 & 0x3ff, + 0x2d2 & 0x3ff, + 0x2ce & 0x3ff, + 0x2ca & 0x3ff, + 0x2c6 & 0x3ff, + 0x2c2 & 0x3ff, + 0x2be & 0x3ff, + 0x2ba & 0x3ff, + 0x2b8 & 0x3ff, + 0x2b4 & 0x3ff, + 0x2b0 & 0x3ff, + 0x2ac & 0x3ff, + 0x2a8 & 0x3ff, + 0x2a6 & 0x3ff, + 0x2a2 & 0x3ff, + 0x29e & 0x3ff, + 0x29c & 0x3ff, + 0x298 & 0x3ff, + 0x294 & 0x3ff, + 0x290 & 0x3ff, + 0x28e & 0x3ff, + 0x28a & 0x3ff, + 0x288 & 0x3ff, + 0x284 & 0x3ff, + 0x280 & 0x3ff, + 0x27e & 0x3ff, + 0x27a & 0x3ff, + 0x278 & 0x3ff, + 0x274 & 0x3ff, + 0x272 & 0x3ff, + 0x26e & 0x3ff, + 0x26c & 0x3ff, + 0x268 & 0x3ff, + 0x266 & 0x3ff, + 0x264 & 0x3ff, + 0x260 & 0x3ff, + 0x25e & 0x3ff, + 0x25a & 0x3ff, + 0x258 & 0x3ff, + 0x254 & 0x3ff, + 0x252 & 0x3ff, + 0x250 & 0x3ff, + 0x24c & 0x3ff, + 0x24a & 0x3ff, + 0x248 & 0x3ff, + 0x246 & 0x3ff, + 0x242 & 0x3ff, + 0x240 & 0x3ff, + 0x23e & 0x3ff, + 0x23c & 0x3ff, + 0x238 & 0x3ff, + 0x236 & 0x3ff, + 0x234 & 0x3ff, + 0x232 & 0x3ff, + 0x230 & 0x3ff, + 0x22c & 0x3ff, + 0x22a & 0x3ff, + 0x228 & 0x3ff, + 0x226 & 0x3ff, + 0x224 & 0x3ff, + 0x220 & 0x3ff, + 0x21e & 0x3ff, + 0x21c & 0x3ff, + 0x21a & 0x3ff, + 0x218 & 0x3ff, + 0x216 & 0x3ff, + 0x214 & 0x3ff, + 0x212 & 0x3ff, + 0x210 & 0x3ff, + 0x20e & 0x3ff, + 0x20c & 0x3ff, + 0x208 & 0x3ff, + 0x208 & 0x3ff, + 0x204 & 0x3ff, + 0x204 & 0x3ff, + 0x201 & 0x3ff, + 0 +}; + +/* constant table RSQRT_10b_256 */ +static const unsigned CONST_TBL_RSQRT_10b_256_0[] = { + 0x1a5 & 0x3ff, + 0x1a0 & 0x3ff, + 0x19a & 0x3ff, + 0x195 & 0x3ff, + 0x18f & 0x3ff, + 0x18a & 0x3ff, + 0x185 & 0x3ff, + 0x180 & 0x3ff, + 0x17a & 0x3ff, + 0x175 & 0x3ff, + 0x170 & 0x3ff, + 0x16b & 0x3ff, + 0x166 & 0x3ff, + 0x161 & 0x3ff, + 0x15d & 0x3ff, + 0x158 & 0x3ff, + 0x153 & 0x3ff, + 0x14e & 0x3ff, + 0x14a & 0x3ff, + 0x145 & 0x3ff, + 0x140 & 0x3ff, + 0x13c & 0x3ff, + 0x138 & 0x3ff, + 0x133 & 0x3ff, + 0x12f & 0x3ff, + 0x12a & 0x3ff, + 0x126 & 0x3ff, + 0x122 & 0x3ff, + 0x11e & 0x3ff, + 0x11a & 0x3ff, + 0x115 & 0x3ff, + 0x111 & 0x3ff, + 0x10d & 0x3ff, + 0x109 & 0x3ff, + 0x105 & 0x3ff, + 0x101 & 0x3ff, + 0xfd & 0x3ff, + 0xfa & 0x3ff, + 0xf6 & 0x3ff, + 0xf2 & 0x3ff, + 0xee & 0x3ff, + 0xea & 0x3ff, + 0xe7 & 0x3ff, + 0xe3 & 0x3ff, + 0xdf & 0x3ff, + 0xdc & 0x3ff, + 0xd8 & 0x3ff, + 0xd5 & 0x3ff, + 0xd1 & 0x3ff, + 0xce & 0x3ff, + 0xca & 0x3ff, + 0xc7 & 0x3ff, + 0xc3 & 0x3ff, + 0xc0 & 0x3ff, + 0xbd & 0x3ff, + 0xb9 & 0x3ff, + 0xb6 & 0x3ff, + 0xb3 & 0x3ff, + 0xb0 & 0x3ff, + 0xad & 0x3ff, + 0xa9 & 0x3ff, + 0xa6 & 0x3ff, + 0xa3 & 0x3ff, + 0xa0 & 0x3ff, + 0x9d & 0x3ff, + 0x9a & 0x3ff, + 0x97 & 0x3ff, + 0x94 & 0x3ff, + 0x91 & 0x3ff, + 0x8e & 0x3ff, + 0x8b & 0x3ff, + 0x88 & 0x3ff, + 0x85 & 0x3ff, + 0x82 & 0x3ff, + 0x7f & 0x3ff, + 0x7d & 0x3ff, + 0x7a & 0x3ff, + 0x77 & 0x3ff, + 0x74 & 0x3ff, + 0x71 & 0x3ff, + 0x6f & 0x3ff, + 0x6c & 0x3ff, + 0x69 & 0x3ff, + 0x67 & 0x3ff, + 0x64 & 0x3ff, + 0x61 & 0x3ff, + 0x5f & 0x3ff, + 0x5c & 0x3ff, + 0x5a & 0x3ff, + 0x57 & 0x3ff, + 0x54 & 0x3ff, + 0x52 & 0x3ff, + 0x4f & 0x3ff, + 0x4d & 0x3ff, + 0x4a & 0x3ff, + 0x48 & 0x3ff, + 0x45 & 0x3ff, + 0x43 & 0x3ff, + 0x41 & 0x3ff, + 0x3e & 0x3ff, + 0x3c & 0x3ff, + 0x3a & 0x3ff, + 0x37 & 0x3ff, + 0x35 & 0x3ff, + 0x33 & 0x3ff, + 0x30 & 0x3ff, + 0x2e & 0x3ff, + 0x2c & 0x3ff, + 0x29 & 0x3ff, + 0x27 & 0x3ff, + 0x25 & 0x3ff, + 0x23 & 0x3ff, + 0x20 & 0x3ff, + 0x1e & 0x3ff, + 0x1c & 0x3ff, + 0x1a & 0x3ff, + 0x18 & 0x3ff, + 0x16 & 0x3ff, + 0x14 & 0x3ff, + 0x11 & 0x3ff, + 0xf & 0x3ff, + 0xd & 0x3ff, + 0xb & 0x3ff, + 0x9 & 0x3ff, + 0x7 & 0x3ff, + 0x5 & 0x3ff, + 0x3 & 0x3ff, + 0x1 & 0x3ff, + 0x3fc & 0x3ff, + 0x3f4 & 0x3ff, + 0x3ec & 0x3ff, + 0x3e5 & 0x3ff, + 0x3dd & 0x3ff, + 0x3d5 & 0x3ff, + 0x3ce & 0x3ff, + 0x3c7 & 0x3ff, + 0x3bf & 0x3ff, + 0x3b8 & 0x3ff, + 0x3b1 & 0x3ff, + 0x3aa & 0x3ff, + 0x3a3 & 0x3ff, + 0x39c & 0x3ff, + 0x395 & 0x3ff, + 0x38e & 0x3ff, + 0x388 & 0x3ff, + 0x381 & 0x3ff, + 0x37a & 0x3ff, + 0x374 & 0x3ff, + 0x36d & 0x3ff, + 0x367 & 0x3ff, + 0x361 & 0x3ff, + 0x35a & 0x3ff, + 0x354 & 0x3ff, + 0x34e & 0x3ff, + 0x348 & 0x3ff, + 0x342 & 0x3ff, + 0x33c & 0x3ff, + 0x336 & 0x3ff, + 0x330 & 0x3ff, + 0x32b & 0x3ff, + 0x325 & 0x3ff, + 0x31f & 0x3ff, + 0x31a & 0x3ff, + 0x314 & 0x3ff, + 0x30f & 0x3ff, + 0x309 & 0x3ff, + 0x304 & 0x3ff, + 0x2fe & 0x3ff, + 0x2f9 & 0x3ff, + 0x2f4 & 0x3ff, + 0x2ee & 0x3ff, + 0x2e9 & 0x3ff, + 0x2e4 & 0x3ff, + 0x2df & 0x3ff, + 0x2da & 0x3ff, + 0x2d5 & 0x3ff, + 0x2d0 & 0x3ff, + 0x2cb & 0x3ff, + 0x2c6 & 0x3ff, + 0x2c1 & 0x3ff, + 0x2bd & 0x3ff, + 0x2b8 & 0x3ff, + 0x2b3 & 0x3ff, + 0x2ae & 0x3ff, + 0x2aa & 0x3ff, + 0x2a5 & 0x3ff, + 0x2a1 & 0x3ff, + 0x29c & 0x3ff, + 0x298 & 0x3ff, + 0x293 & 0x3ff, + 0x28f & 0x3ff, + 0x28a & 0x3ff, + 0x286 & 0x3ff, + 0x282 & 0x3ff, + 0x27d & 0x3ff, + 0x279 & 0x3ff, + 0x275 & 0x3ff, + 0x271 & 0x3ff, + 0x26d & 0x3ff, + 0x268 & 0x3ff, + 0x264 & 0x3ff, + 0x260 & 0x3ff, + 0x25c & 0x3ff, + 0x258 & 0x3ff, + 0x254 & 0x3ff, + 0x250 & 0x3ff, + 0x24c & 0x3ff, + 0x249 & 0x3ff, + 0x245 & 0x3ff, + 0x241 & 0x3ff, + 0x23d & 0x3ff, + 0x239 & 0x3ff, + 0x235 & 0x3ff, + 0x232 & 0x3ff, + 0x22e & 0x3ff, + 0x22a & 0x3ff, + 0x227 & 0x3ff, + 0x223 & 0x3ff, + 0x220 & 0x3ff, + 0x21c & 0x3ff, + 0x218 & 0x3ff, + 0x215 & 0x3ff, + 0x211 & 0x3ff, + 0x20e & 0x3ff, + 0x20a & 0x3ff, + 0x207 & 0x3ff, + 0x204 & 0x3ff, + 0x200 & 0x3ff, + 0x1fd & 0x3ff, + 0x1f9 & 0x3ff, + 0x1f6 & 0x3ff, + 0x1f3 & 0x3ff, + 0x1f0 & 0x3ff, + 0x1ec & 0x3ff, + 0x1e9 & 0x3ff, + 0x1e6 & 0x3ff, + 0x1e3 & 0x3ff, + 0x1df & 0x3ff, + 0x1dc & 0x3ff, + 0x1d9 & 0x3ff, + 0x1d6 & 0x3ff, + 0x1d3 & 0x3ff, + 0x1d0 & 0x3ff, + 0x1cd & 0x3ff, + 0x1ca & 0x3ff, + 0x1c7 & 0x3ff, + 0x1c4 & 0x3ff, + 0x1c1 & 0x3ff, + 0x1be & 0x3ff, + 0x1bb & 0x3ff, + 0x1b8 & 0x3ff, + 0x1b5 & 0x3ff, + 0x1b2 & 0x3ff, + 0x1af & 0x3ff, + 0x1ac & 0x3ff, + 0x1aa & 0x3ff, + 0 +}; + +/* constant table RECIP_10b_256 */ +static const unsigned CONST_TBL_RECIP_10b_256_0[] = { + 0x3fc & 0x3ff, + 0x3f4 & 0x3ff, + 0x3ec & 0x3ff, + 0x3e4 & 0x3ff, + 0x3dd & 0x3ff, + 0x3d5 & 0x3ff, + 0x3cd & 0x3ff, + 0x3c6 & 0x3ff, + 0x3be & 0x3ff, + 0x3b7 & 0x3ff, + 0x3af & 0x3ff, + 0x3a8 & 0x3ff, + 0x3a1 & 0x3ff, + 0x399 & 0x3ff, + 0x392 & 0x3ff, + 0x38b & 0x3ff, + 0x384 & 0x3ff, + 0x37d & 0x3ff, + 0x376 & 0x3ff, + 0x36f & 0x3ff, + 0x368 & 0x3ff, + 0x361 & 0x3ff, + 0x35b & 0x3ff, + 0x354 & 0x3ff, + 0x34d & 0x3ff, + 0x346 & 0x3ff, + 0x340 & 0x3ff, + 0x339 & 0x3ff, + 0x333 & 0x3ff, + 0x32c & 0x3ff, + 0x326 & 0x3ff, + 0x320 & 0x3ff, + 0x319 & 0x3ff, + 0x313 & 0x3ff, + 0x30d & 0x3ff, + 0x307 & 0x3ff, + 0x300 & 0x3ff, + 0x2fa & 0x3ff, + 0x2f4 & 0x3ff, + 0x2ee & 0x3ff, + 0x2e8 & 0x3ff, + 0x2e2 & 0x3ff, + 0x2dc & 0x3ff, + 0x2d7 & 0x3ff, + 0x2d1 & 0x3ff, + 0x2cb & 0x3ff, + 0x2c5 & 0x3ff, + 0x2bf & 0x3ff, + 0x2ba & 0x3ff, + 0x2b4 & 0x3ff, + 0x2af & 0x3ff, + 0x2a9 & 0x3ff, + 0x2a3 & 0x3ff, + 0x29e & 0x3ff, + 0x299 & 0x3ff, + 0x293 & 0x3ff, + 0x28e & 0x3ff, + 0x288 & 0x3ff, + 0x283 & 0x3ff, + 0x27e & 0x3ff, + 0x279 & 0x3ff, + 0x273 & 0x3ff, + 0x26e & 0x3ff, + 0x269 & 0x3ff, + 0x264 & 0x3ff, + 0x25f & 0x3ff, + 0x25a & 0x3ff, + 0x255 & 0x3ff, + 0x250 & 0x3ff, + 0x24b & 0x3ff, + 0x246 & 0x3ff, + 0x241 & 0x3ff, + 0x23c & 0x3ff, + 0x237 & 0x3ff, + 0x232 & 0x3ff, + 0x22e & 0x3ff, + 0x229 & 0x3ff, + 0x224 & 0x3ff, + 0x21f & 0x3ff, + 0x21b & 0x3ff, + 0x216 & 0x3ff, + 0x211 & 0x3ff, + 0x20d & 0x3ff, + 0x208 & 0x3ff, + 0x204 & 0x3ff, + 0x1ff & 0x3ff, + 0x1fb & 0x3ff, + 0x1f6 & 0x3ff, + 0x1f2 & 0x3ff, + 0x1ed & 0x3ff, + 0x1e9 & 0x3ff, + 0x1e5 & 0x3ff, + 0x1e0 & 0x3ff, + 0x1dc & 0x3ff, + 0x1d8 & 0x3ff, + 0x1d4 & 0x3ff, + 0x1cf & 0x3ff, + 0x1cb & 0x3ff, + 0x1c7 & 0x3ff, + 0x1c3 & 0x3ff, + 0x1bf & 0x3ff, + 0x1bb & 0x3ff, + 0x1b6 & 0x3ff, + 0x1b2 & 0x3ff, + 0x1ae & 0x3ff, + 0x1aa & 0x3ff, + 0x1a6 & 0x3ff, + 0x1a2 & 0x3ff, + 0x19e & 0x3ff, + 0x19a & 0x3ff, + 0x197 & 0x3ff, + 0x193 & 0x3ff, + 0x18f & 0x3ff, + 0x18b & 0x3ff, + 0x187 & 0x3ff, + 0x183 & 0x3ff, + 0x17f & 0x3ff, + 0x17c & 0x3ff, + 0x178 & 0x3ff, + 0x174 & 0x3ff, + 0x171 & 0x3ff, + 0x16d & 0x3ff, + 0x169 & 0x3ff, + 0x166 & 0x3ff, + 0x162 & 0x3ff, + 0x15e & 0x3ff, + 0x15b & 0x3ff, + 0x157 & 0x3ff, + 0x154 & 0x3ff, + 0x150 & 0x3ff, + 0x14d & 0x3ff, + 0x149 & 0x3ff, + 0x146 & 0x3ff, + 0x142 & 0x3ff, + 0x13f & 0x3ff, + 0x13b & 0x3ff, + 0x138 & 0x3ff, + 0x134 & 0x3ff, + 0x131 & 0x3ff, + 0x12e & 0x3ff, + 0x12a & 0x3ff, + 0x127 & 0x3ff, + 0x124 & 0x3ff, + 0x120 & 0x3ff, + 0x11d & 0x3ff, + 0x11a & 0x3ff, + 0x117 & 0x3ff, + 0x113 & 0x3ff, + 0x110 & 0x3ff, + 0x10d & 0x3ff, + 0x10a & 0x3ff, + 0x107 & 0x3ff, + 0x103 & 0x3ff, + 0x100 & 0x3ff, + 0xfd & 0x3ff, + 0xfa & 0x3ff, + 0xf7 & 0x3ff, + 0xf4 & 0x3ff, + 0xf1 & 0x3ff, + 0xee & 0x3ff, + 0xeb & 0x3ff, + 0xe8 & 0x3ff, + 0xe5 & 0x3ff, + 0xe2 & 0x3ff, + 0xdf & 0x3ff, + 0xdc & 0x3ff, + 0xd9 & 0x3ff, + 0xd6 & 0x3ff, + 0xd3 & 0x3ff, + 0xd0 & 0x3ff, + 0xcd & 0x3ff, + 0xca & 0x3ff, + 0xc8 & 0x3ff, + 0xc5 & 0x3ff, + 0xc2 & 0x3ff, + 0xbf & 0x3ff, + 0xbc & 0x3ff, + 0xb9 & 0x3ff, + 0xb7 & 0x3ff, + 0xb4 & 0x3ff, + 0xb1 & 0x3ff, + 0xae & 0x3ff, + 0xac & 0x3ff, + 0xa9 & 0x3ff, + 0xa6 & 0x3ff, + 0xa4 & 0x3ff, + 0xa1 & 0x3ff, + 0x9e & 0x3ff, + 0x9c & 0x3ff, + 0x99 & 0x3ff, + 0x96 & 0x3ff, + 0x94 & 0x3ff, + 0x91 & 0x3ff, + 0x8e & 0x3ff, + 0x8c & 0x3ff, + 0x89 & 0x3ff, + 0x87 & 0x3ff, + 0x84 & 0x3ff, + 0x82 & 0x3ff, + 0x7f & 0x3ff, + 0x7c & 0x3ff, + 0x7a & 0x3ff, + 0x77 & 0x3ff, + 0x75 & 0x3ff, + 0x73 & 0x3ff, + 0x70 & 0x3ff, + 0x6e & 0x3ff, + 0x6b & 0x3ff, + 0x69 & 0x3ff, + 0x66 & 0x3ff, + 0x64 & 0x3ff, + 0x61 & 0x3ff, + 0x5f & 0x3ff, + 0x5d & 0x3ff, + 0x5a & 0x3ff, + 0x58 & 0x3ff, + 0x56 & 0x3ff, + 0x53 & 0x3ff, + 0x51 & 0x3ff, + 0x4f & 0x3ff, + 0x4c & 0x3ff, + 0x4a & 0x3ff, + 0x48 & 0x3ff, + 0x45 & 0x3ff, + 0x43 & 0x3ff, + 0x41 & 0x3ff, + 0x3f & 0x3ff, + 0x3c & 0x3ff, + 0x3a & 0x3ff, + 0x38 & 0x3ff, + 0x36 & 0x3ff, + 0x33 & 0x3ff, + 0x31 & 0x3ff, + 0x2f & 0x3ff, + 0x2d & 0x3ff, + 0x2b & 0x3ff, + 0x29 & 0x3ff, + 0x26 & 0x3ff, + 0x24 & 0x3ff, + 0x22 & 0x3ff, + 0x20 & 0x3ff, + 0x1e & 0x3ff, + 0x1c & 0x3ff, + 0x1a & 0x3ff, + 0x18 & 0x3ff, + 0x15 & 0x3ff, + 0x13 & 0x3ff, + 0x11 & 0x3ff, + 0xf & 0x3ff, + 0xd & 0x3ff, + 0xb & 0x3ff, + 0x9 & 0x3ff, + 0x7 & 0x3ff, + 0x5 & 0x3ff, + 0x3 & 0x3ff, + 0x1 & 0x3ff, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_MR_0_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +OperandSem_opnd_sem_MR_0_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_1_encode (uint32 *valp) +{ + int error; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_3_encode (uint32 *valp) +{ + int error; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = uimm4x16_in_0 << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_1_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_3_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_5_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_2_decode (uint32 *valp) +{ + unsigned dfp_fld_op2_2_out_0; + unsigned dfp_fld_op2_2_in_0; + dfp_fld_op2_2_in_0 = *valp & 0x1; + dfp_fld_op2_2_out_0 = (0 << 1) | dfp_fld_op2_2_in_0; + *valp = dfp_fld_op2_2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_2_encode (uint32 *valp) +{ + unsigned dfp_fld_op2_2_in_0; + unsigned dfp_fld_op2_2_out_0; + dfp_fld_op2_2_out_0 = *valp; + dfp_fld_op2_2_in_0 = (((dfp_fld_op2_2_out_0 >> 0) & 1)) & 0x1; + *valp = dfp_fld_op2_2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_1_0_decode (uint32 *valp) +{ + unsigned dfp_fld_op2_1_0_out_0; + unsigned dfp_fld_op2_1_0_in_0; + dfp_fld_op2_1_0_in_0 = *valp & 0x3; + dfp_fld_op2_1_0_out_0 = (0 << 2) | dfp_fld_op2_1_0_in_0; + *valp = dfp_fld_op2_1_0_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_1_0_encode (uint32 *valp) +{ + unsigned dfp_fld_op2_1_0_in_0; + unsigned dfp_fld_op2_1_0_out_0; + dfp_fld_op2_1_0_out_0 = *valp; + dfp_fld_op2_1_0_in_0 = (dfp_fld_op2_1_0_out_0 & 0x3); + *valp = dfp_fld_op2_1_0_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_FR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_FR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_imm8x4_decode (uint32 *valp) +{ + unsigned imm8x4_out_0; + unsigned imm8x4_in_0; + imm8x4_in_0 = *valp & 0xff; + imm8x4_out_0 = (0 << 10) | (imm8x4_in_0 << 2) | 0; + *valp = imm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm8x4_encode (uint32 *valp) +{ + unsigned imm8x4_in_0; + unsigned imm8x4_out_0; + imm8x4_out_0 = *valp; + imm8x4_in_0 = ((imm8x4_out_0 >> 2) & 0xff); + *valp = imm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm8x8_decode (uint32 *valp) +{ + unsigned imm8x8_out_0; + unsigned imm8x8_in_0; + imm8x8_in_0 = *valp & 0xff; + imm8x8_out_0 = (0 << 11) | (imm8x8_in_0 << 3) | 0; + *valp = imm8x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm8x8_encode (uint32 *valp) +{ + unsigned imm8x8_in_0; + unsigned imm8x8_out_0; + imm8x8_out_0 = *valp; + imm8x8_in_0 = ((imm8x8_out_0 >> 3) & 0xff); + *valp = imm8x8_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "mx", FIELD_x, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, + 0, 0 }, + { "my", FIELD_y, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, + 0, 0 }, + { "mw", FIELD_w, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, + 0, 0 }, + { "mr0", FIELD__mr0, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, + 0, 0 }, + { "mr1", FIELD__mr1, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, + 0, 0 }, + { "mr2", FIELD__mr2, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, + 0, 0 }, + { "mr3", FIELD__mr3, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "dfp_fld_op2_2", FIELD_dfp_fld_op2_2, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0 }, + { "dfp_fld_op2_1_0", FIELD_dfp_fld_op2_1_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_1_0_encode, OperandSem_opnd_sem_dfp_fld_op2_1_0_decode, + 0, 0 }, + { "dfp_fld_r_0", FIELD_dfp_fld_r_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0 }, + { "dfp_fld_r_2_1", FIELD_dfp_fld_r_2_1, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_1_0_encode, OperandSem_opnd_sem_dfp_fld_op2_1_0_decode, + 0, 0 }, + { "dfp_fld_op2", FIELD_dfp_fld_op2, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "dfp_fld_op2_0", FIELD_dfp_fld_op2_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0 }, + { "dfp_fld_s_0", FIELD_dfp_fld_s_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0 }, + { "frr", FIELD_r, REGFILE_FR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode, + 0, 0 }, + { "frs", FIELD_s, REGFILE_FR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode, + 0, 0 }, + { "frt", FIELD_t, REGFILE_FR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode, + 0, 0 }, + { "imm_t", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "imm_s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "imm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_imm8x4_encode, OperandSem_opnd_sem_imm8x4_decode, + 0, 0 }, + { "imm8x8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_imm8x8_encode, OperandSem_opnd_sem_imm8x8_decode, + 0, 0 }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, + { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, + { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, + { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op1", FIELD_dfp_fld_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_r_3", FIELD_dfp_fld_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_r_3_1", FIELD_dfp_fld_r_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_s_3_1", FIELD_dfp_fld_s_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op2_3", FIELD_dfp_fld_op2_3, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op2_3_2", FIELD_dfp_fld_op2_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op2_3_1", FIELD_dfp_fld_op2_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_mx, + OPERAND_my, + OPERAND_mw, + OPERAND_mr0, + OPERAND_mr1, + OPERAND_mr2, + OPERAND_mr3, + OPERAND_immt, + OPERAND_imms, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_dfp_fld_op2_2, + OPERAND_dfp_fld_op2_1_0, + OPERAND_dfp_fld_r_0, + OPERAND_dfp_fld_r_2_1, + OPERAND_dfp_fld_op2, + OPERAND_dfp_fld_op2_0, + OPERAND_dfp_fld_s_0, + OPERAND_frr, + OPERAND_frs, + OPERAND_frt, + OPERAND_imm_t, + OPERAND_imm_s, + OPERAND_imm8x4, + OPERAND_imm8x8, + OPERAND_bitindex, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_r3, + OPERAND_rbit2, + OPERAND_rhi, + OPERAND_t3, + OPERAND_tbit2, + OPERAND_tlo, + OPERAND_w, + OPERAND_y, + OPERAND_x, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_s8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_dfp_fld_op1, + OPERAND_dfp_fld_r_3, + OPERAND_dfp_fld_r_3_1, + OPERAND_dfp_fld_s_3_1, + OPERAND_dfp_fld_op2_3, + OPERAND_dfp_fld_op2_3_2, + OPERAND_dfp_fld_op2_3_1, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_LSI_args[] = { + { { OPERAND_frt }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSIP_args[] = { + { { OPERAND_frt }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_imm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSX_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSX_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSXP_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSXP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSI_args[] = { + { { OPERAND_frt }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSIP_args[] = { + { { OPERAND_frt }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_imm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSX_args[] = { + { { OPERAND_frr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSX_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSXP_args[] = { + { { OPERAND_frr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSXP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOV_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOV_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ROUND_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_ROUND_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CEIL_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_CEIL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOOR_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOOR_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_imm_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSEXCM }, 'o' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { + { { STATE_EPC7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { + { { STATE_EPC7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { + { { STATE_EPC7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { + { { STATE_EXCSAVE7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { + { { STATE_EXCSAVE7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { + { { STATE_EXCSAVE7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { + { { STATE_EPS7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { + { { STATE_EPS7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { + { { STATE_EPS7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = { + { { STATE_MISC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = { + { { STATE_MISC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = { + { { STATE_MISC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = { + { { STATE_MISC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = { + { { STATE_MISC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = { + { { STATE_MISC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32h_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPC7 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_EPS7 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERI_RAW_INTERLOCK }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERI_RAW_INTERLOCK }, 'o' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_iclass_F64ITER_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2_1_0 }, 'i' }, + { { OPERAND_dfp_fld_op2_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ITER_stateArgs[] = { + { { STATE_F64R }, 'm' }, + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64RND_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2_1_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64RND_stateArgs[] = { + { { STATE_F64R }, 'm' }, + { { STATE_F64S }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ADDC_F64SUBC_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dfp_fld_r_2_1 }, 'i' }, + { { OPERAND_dfp_fld_r_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ADDC_F64SUBC_stateArgs[] = { + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64SIG_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPL_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPL_stateArgs[] = { + { { STATE_F64S }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPH_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPH_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_F64R }, 'o' }, + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64NORM_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64NORM_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64SEXP_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RF64R_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_dfp_fld_s_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RF64R_stateArgs[] = { + { { STATE_F64R }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WF64R_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_r_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WF64R_stateArgs[] = { + { { STATE_F64R }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_lo_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_lo_stateArgs[] = { + { { STATE_F64R }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_lo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_lo_stateArgs[] = { + { { STATE_F64R }, 'm' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_hi_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_hi_stateArgs[] = { + { { STATE_F64R }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_hi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_hi_stateArgs[] = { + { { STATE_F64R }, 'm' } +}; + +static xtensa_arg_internal Iclass_rur_f64s_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64s_stateArgs[] = { + { { STATE_F64S }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64s_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64s_stateArgs[] = { + { { STATE_F64S }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InvalidEnable }, 'i' }, + { { STATE_DivZeroEnable }, 'i' }, + { { STATE_OverflowEnable }, 'i' }, + { { STATE_UnderflowEnable }, 'i' }, + { { STATE_InexactEnable }, 'i' }, + { { STATE_FPreserved20 }, 'i' }, + { { STATE_FPreserved5 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_InvalidEnable }, 'o' }, + { { STATE_DivZeroEnable }, 'o' }, + { { STATE_OverflowEnable }, 'o' }, + { { STATE_UnderflowEnable }, 'o' }, + { { STATE_InexactEnable }, 'o' }, + { { STATE_FPreserved20 }, 'o' }, + { { STATE_FPreserved5 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_FPreserved20a }, 'i' }, + { { STATE_FPreserved7 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_FPreserved20a }, 'o' }, + { { STATE_FPreserved7 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 3, Iclass_LSI_args, + 1, Iclass_LSI_stateArgs, 0, 0 }, + { 3, Iclass_LSIP_args, + 1, Iclass_LSIP_stateArgs, 0, 0 }, + { 3, Iclass_LSX_args, + 1, Iclass_LSX_stateArgs, 0, 0 }, + { 3, Iclass_LSXP_args, + 1, Iclass_LSXP_stateArgs, 0, 0 }, + { 3, Iclass_SSI_args, + 1, Iclass_SSI_stateArgs, 0, 0 }, + { 3, Iclass_SSIP_args, + 1, Iclass_SSIP_stateArgs, 0, 0 }, + { 3, Iclass_SSX_args, + 1, Iclass_SSX_stateArgs, 0, 0 }, + { 3, Iclass_SSXP_args, + 1, Iclass_SSXP_stateArgs, 0, 0 }, + { 2, Iclass_ABS_S_args, + 1, Iclass_ABS_S_stateArgs, 0, 0 }, + { 2, Iclass_NEG_S_args, + 1, Iclass_NEG_S_stateArgs, 0, 0 }, + { 2, Iclass_MOV_S_args, + 1, Iclass_MOV_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVEQZ_S_args, + 1, Iclass_MOVEQZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVNEZ_S_args, + 1, Iclass_MOVNEZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVLTZ_S_args, + 1, Iclass_MOVLTZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVGEZ_S_args, + 1, Iclass_MOVGEZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVF_S_args, + 1, Iclass_MOVF_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVT_S_args, + 1, Iclass_MOVT_S_stateArgs, 0, 0 }, + { 2, Iclass_WFR_args, + 1, Iclass_WFR_stateArgs, 0, 0 }, + { 2, Iclass_RFR_args, + 1, Iclass_RFR_stateArgs, 0, 0 }, + { 3, Iclass_ROUND_S_args, + 3, Iclass_ROUND_S_stateArgs, 0, 0 }, + { 3, Iclass_CEIL_S_args, + 3, Iclass_CEIL_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOOR_S_args, + 3, Iclass_FLOOR_S_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC_S_args, + 3, Iclass_TRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC_S_args, + 3, Iclass_UTRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_S_args, + 3, Iclass_FLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_S_args, + 3, Iclass_UFLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_UN_S_args, + 2, Iclass_UN_S_stateArgs, 0, 0 }, + { 3, Iclass_ULT_S_args, + 2, Iclass_ULT_S_stateArgs, 0, 0 }, + { 3, Iclass_ULE_S_args, + 2, Iclass_ULE_S_stateArgs, 0, 0 }, + { 3, Iclass_UEQ_S_args, + 2, Iclass_UEQ_S_stateArgs, 0, 0 }, + { 3, Iclass_OLT_S_args, + 2, Iclass_OLT_S_stateArgs, 0, 0 }, + { 3, Iclass_OLE_S_args, + 2, Iclass_OLE_S_stateArgs, 0, 0 }, + { 3, Iclass_OEQ_S_args, + 2, Iclass_OEQ_S_stateArgs, 0, 0 }, + { 3, Iclass_ADD_S_args, + 6, Iclass_ADD_S_stateArgs, 0, 0 }, + { 3, Iclass_SUB_S_args, + 6, Iclass_SUB_S_stateArgs, 0, 0 }, + { 3, Iclass_MUL_S_args, + 6, Iclass_MUL_S_stateArgs, 0, 0 }, + { 3, Iclass_MADD_S_args, + 6, Iclass_MADD_S_stateArgs, 0, 0 }, + { 3, Iclass_MSUB_S_args, + 6, Iclass_MSUB_S_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_S_args, + 1, Iclass_SQRT0_S_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_S_args, + 1, Iclass_DIV0_S_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_S_args, + 3, Iclass_RECIP0_S_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_S_args, + 3, Iclass_RSQRT0_S_stateArgs, 0, 0 }, + { 3, Iclass_MADDN_S_args, + 1, Iclass_MADDN_S_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_S_args, + 5, Iclass_DIVN_S_stateArgs, 0, 0 }, + { 2, Iclass_CONST_S_args, + 1, Iclass_CONST_S_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_S_args, + 1, Iclass_NEXP01_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXP_S_args, + 1, Iclass_ADDEXP_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXPM_S_args, + 1, Iclass_ADDEXPM_S_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_S_args, + 3, Iclass_MKDADJ_S_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_S_args, + 2, Iclass_MKSADJ_S_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 1, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 1, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 1, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc7_args, + 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc7_args, + 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc7_args, + 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave7_args, + 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave7_args, + 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave7_args, + 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps7_args, + 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps7_args, + 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps7_args, + 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc2_args, + 1, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc2_args, + 1, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc2_args, + 1, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc3_args, + 1, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc3_args, + 1, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc3_args, + 1, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32h_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 5, Iclass_iclass_F64ITER_args, + 2, Iclass_iclass_F64ITER_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64RND_args, + 2, Iclass_iclass_F64RND_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64ADDC_F64SUBC_args, + 1, Iclass_iclass_F64ADDC_F64SUBC_stateArgs, 0, 0 }, + { 2, Iclass_iclass_F64SIG_args, + 0, 0, 0, 0 }, + { 3, Iclass_iclass_F64CMPL_args, + 1, Iclass_iclass_F64CMPL_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64CMPH_args, + 3, Iclass_iclass_F64CMPH_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64NORM_args, + 2, Iclass_iclass_F64NORM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_F64SEXP_args, + 0, 0, 0, 0 }, + { 2, Iclass_iclass_RF64R_args, + 1, Iclass_iclass_RF64R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_WF64R_args, + 1, Iclass_iclass_WF64R_stateArgs, 0, 0 }, + { 1, Iclass_rur_f64r_lo_args, + 1, Iclass_rur_f64r_lo_stateArgs, 0, 0 }, + { 1, Iclass_wur_f64r_lo_args, + 1, Iclass_wur_f64r_lo_stateArgs, 0, 0 }, + { 1, Iclass_rur_f64r_hi_args, + 1, Iclass_rur_f64r_hi_stateArgs, 0, 0 }, + { 1, Iclass_wur_f64r_hi_args, + 1, Iclass_wur_f64r_hi_stateArgs, 0, 0 }, + { 1, Iclass_rur_f64s_args, + 1, Iclass_rur_f64s_stateArgs, 0, 0 }, + { 1, Iclass_wur_f64s_args, + 1, Iclass_wur_f64s_stateArgs, 0, 0 }, + { 1, Iclass_rur_fcr_args, + 9, Iclass_rur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fcr_args, + 9, Iclass_wur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_rur_fsr_args, + 8, Iclass_rur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fsr_args, + 8, Iclass_wur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 1, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 1, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_LSI, + ICLASS_LSIP, + ICLASS_LSX, + ICLASS_LSXP, + ICLASS_SSI, + ICLASS_SSIP, + ICLASS_SSX, + ICLASS_SSXP, + ICLASS_ABS_S, + ICLASS_NEG_S, + ICLASS_MOV_S, + ICLASS_MOVEQZ_S, + ICLASS_MOVNEZ_S, + ICLASS_MOVLTZ_S, + ICLASS_MOVGEZ_S, + ICLASS_MOVF_S, + ICLASS_MOVT_S, + ICLASS_WFR, + ICLASS_RFR, + ICLASS_ROUND_S, + ICLASS_CEIL_S, + ICLASS_FLOOR_S, + ICLASS_TRUNC_S, + ICLASS_UTRUNC_S, + ICLASS_FLOAT_S, + ICLASS_UFLOAT_S, + ICLASS_UN_S, + ICLASS_ULT_S, + ICLASS_ULE_S, + ICLASS_UEQ_S, + ICLASS_OLT_S, + ICLASS_OLE_S, + ICLASS_OEQ_S, + ICLASS_ADD_S, + ICLASS_SUB_S, + ICLASS_MUL_S, + ICLASS_MADD_S, + ICLASS_MSUB_S, + ICLASS_SQRT0_S, + ICLASS_DIV0_S, + ICLASS_RECIP0_S, + ICLASS_RSQRT0_S, + ICLASS_MADDN_S, + ICLASS_DIVN_S, + ICLASS_CONST_S, + ICLASS_NEXP01_S, + ICLASS_ADDEXP_S, + ICLASS_ADDEXPM_S, + ICLASS_MKDADJ_S, + ICLASS_MKSADJ_S, + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_epc7, + ICLASS_xt_iclass_wsr_epc7, + ICLASS_xt_iclass_xsr_epc7, + ICLASS_xt_iclass_rsr_excsave7, + ICLASS_xt_iclass_wsr_excsave7, + ICLASS_xt_iclass_xsr_excsave7, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_eps7, + ICLASS_xt_iclass_wsr_eps7, + ICLASS_xt_iclass_xsr_eps7, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_misc2, + ICLASS_xt_iclass_wsr_misc2, + ICLASS_xt_iclass_xsr_misc2, + ICLASS_xt_iclass_rsr_misc3, + ICLASS_xt_iclass_wsr_misc3, + ICLASS_xt_iclass_xsr_misc3, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_mul32h, + ICLASS_xt_iclass_mac16_aa, + ICLASS_xt_iclass_mac16_ad, + ICLASS_xt_iclass_mac16_da, + ICLASS_xt_iclass_mac16_dd, + ICLASS_xt_iclass_mac16a_aa, + ICLASS_xt_iclass_mac16a_ad, + ICLASS_xt_iclass_mac16a_da, + ICLASS_xt_iclass_mac16a_dd, + ICLASS_xt_iclass_mac16al_da, + ICLASS_xt_iclass_mac16al_dd, + ICLASS_xt_iclass_mac16_l, + ICLASS_xt_iclass_rsr_m0, + ICLASS_xt_iclass_wsr_m0, + ICLASS_xt_iclass_xsr_m0, + ICLASS_xt_iclass_rsr_m1, + ICLASS_xt_iclass_wsr_m1, + ICLASS_xt_iclass_xsr_m1, + ICLASS_xt_iclass_rsr_m2, + ICLASS_xt_iclass_wsr_m2, + ICLASS_xt_iclass_xsr_m2, + ICLASS_xt_iclass_rsr_m3, + ICLASS_xt_iclass_wsr_m3, + ICLASS_xt_iclass_xsr_m3, + ICLASS_xt_iclass_rsr_acclo, + ICLASS_xt_iclass_wsr_acclo, + ICLASS_xt_iclass_xsr_acclo, + ICLASS_xt_iclass_rsr_acchi, + ICLASS_xt_iclass_wsr_acchi, + ICLASS_xt_iclass_xsr_acchi, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_iclass_F64ITER, + ICLASS_iclass_F64RND, + ICLASS_iclass_F64ADDC_F64SUBC, + ICLASS_iclass_F64SIG, + ICLASS_iclass_F64CMPL, + ICLASS_iclass_F64CMPH, + ICLASS_iclass_F64NORM, + ICLASS_iclass_F64SEXP, + ICLASS_iclass_RF64R, + ICLASS_iclass_WF64R, + ICLASS_rur_f64r_lo, + ICLASS_wur_f64r_lo, + ICLASS_rur_f64r_hi, + ICLASS_wur_f64r_hi, + ICLASS_rur_f64s, + ICLASS_wur_f64s, + ICLASS_rur_fcr, + ICLASS_wur_fcr, + ICLASS_rur_fsr, + ICLASS_wur_fsr, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE +}; + + +/* Opcode encodings. */ + +static void +Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_lsip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003; +} + +static void +Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_lsxp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4003; +} + +static void +Opcode_ssip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc003; +} + +static void +Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ssxp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0010; +} + +static void +Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0060; +} + +static void +Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0000; +} + +static void +Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b0000; +} + +static void +Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b0000; +} + +static void +Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0000; +} + +static void +Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0000; +} + +static void +Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0000; +} + +static void +Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb0000; +} + +static void +Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0050; +} + +static void +Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0040; +} + +static void +Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a0000; +} + +static void +Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0000; +} + +static void +Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa0000; +} + +static void +Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0000; +} + +static void +Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0000; +} + +static void +Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0000; +} + +static void +Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda0000; +} + +static void +Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0000; +} + +static void +Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_sqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0090; +} + +static void +Opcode_div0_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0070; +} + +static void +Opcode_recip0_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0080; +} + +static void +Opcode_rsqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00a0; +} + +static void +Opcode_maddn_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_divn_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_const_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0030; +} + +static void +Opcode_nexp01_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00b0; +} + +static void +Opcode_addexp_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00e0; +} + +static void +Opcode_addexpm_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00f0; +} + +static void +Opcode_mkdadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00d0; +} + +static void +Opcode_mksadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00c0; +} + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b700; +} + +static void +Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b700; +} + +static void +Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b700; +} + +static void +Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d700; +} + +static void +Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d700; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c700; +} + +static void +Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c700; +} + +static void +Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c700; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f600; +} + +static void +Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f600; +} + +static void +Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f600; +} + +static void +Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f700; +} + +static void +Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f700; +} + +static void +Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f700; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20000; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740004; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750004; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760004; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770004; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710004; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720004; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730004; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340004; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350004; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360004; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370004; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640004; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660004; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670004; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240004; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250004; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270004; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790004; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0004; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0004; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0004; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0004; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0004; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390004; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0004; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0004; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0004; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0004; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0004; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0004; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690004; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0004; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0004; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0004; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0004; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0004; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0004; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290004; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0004; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0004; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0004; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0004; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0004; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0004; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590004; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490004; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0004; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0004; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0004; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0004; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90004; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0004; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0004; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0004; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900004; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800004; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612000; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32100; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132100; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612100; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32200; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132200; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612200; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32300; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132300; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612300; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611000; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31100; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131100; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611100; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_f64iter_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000; +} + +static void +Opcode_f64rnd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_f64addc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb0000; +} + +static void +Opcode_f64subc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb8000; +} + +static void +Opcode_f64sig_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_f64cmpl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0000; +} + +static void +Opcode_f64cmph_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_f64norm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0000; +} + +static void +Opcode_f64sexp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_rf64r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbce00; +} + +static void +Opcode_wf64r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_rur_f64r_lo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30ea0; +} + +static void +Opcode_wur_f64r_lo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3ea00; +} + +static void +Opcode_rur_f64r_hi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30eb0; +} + +static void +Opcode_wur_f64r_hi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3eb00; +} + +static void +Opcode_rur_f64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30ec0; +} + +static void +Opcode_wur_f64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3ec00; +} + +static void +Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e80; +} + +static void +Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e800; +} + +static void +Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e90; +} + +static void +Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e900; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = { + Opcode_lsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsip_encode_fns[] = { + Opcode_lsip_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = { + Opcode_lsx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsxp_encode_fns[] = { + Opcode_lsxp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = { + Opcode_ssi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssip_encode_fns[] = { + Opcode_ssip_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = { + Opcode_ssx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssxp_encode_fns[] = { + Opcode_ssxp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { + Opcode_abs_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { + Opcode_neg_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = { + Opcode_mov_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { + Opcode_moveqz_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { + Opcode_movnez_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { + Opcode_movltz_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { + Opcode_movgez_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { + Opcode_movf_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { + Opcode_movt_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { + Opcode_wfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { + Opcode_rfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = { + Opcode_round_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = { + Opcode_ceil_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = { + Opcode_floor_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { + Opcode_trunc_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { + Opcode_utrunc_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { + Opcode_float_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { + Opcode_ufloat_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { + Opcode_un_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { + Opcode_ult_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { + Opcode_ule_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { + Opcode_ueq_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { + Opcode_olt_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { + Opcode_ole_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { + Opcode_oeq_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { + Opcode_add_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { + Opcode_sub_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { + Opcode_mul_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { + Opcode_madd_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { + Opcode_msub_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = { + Opcode_sqrt0_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = { + Opcode_div0_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = { + Opcode_recip0_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = { + Opcode_rsqrt0_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = { + Opcode_maddn_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = { + Opcode_divn_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = { + Opcode_const_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = { + Opcode_nexp01_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = { + Opcode_addexp_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = { + Opcode_addexpm_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = { + Opcode_mkdadj_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = { + Opcode_mksadj_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { + Opcode_rsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { + Opcode_wsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { + Opcode_xsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { + Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { + Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { + Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { + Opcode_rsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { + Opcode_wsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { + Opcode_xsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = { + Opcode_rsr_misc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = { + Opcode_wsr_misc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = { + Opcode_xsr_misc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = { + Opcode_rsr_misc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = { + Opcode_wsr_misc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = { + Opcode_xsr_misc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { + Opcode_muluh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { + Opcode_mulsh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64iter_encode_fns[] = { + Opcode_f64iter_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64rnd_encode_fns[] = { + Opcode_f64rnd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64addc_encode_fns[] = { + Opcode_f64addc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64subc_encode_fns[] = { + Opcode_f64subc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64sig_encode_fns[] = { + Opcode_f64sig_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64cmpl_encode_fns[] = { + Opcode_f64cmpl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64cmph_encode_fns[] = { + Opcode_f64cmph_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64norm_encode_fns[] = { + Opcode_f64norm_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64sexp_encode_fns[] = { + Opcode_f64sexp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rf64r_encode_fns[] = { + Opcode_rf64r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wf64r_encode_fns[] = { + Opcode_wf64r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_f64r_lo_encode_fns[] = { + Opcode_rur_f64r_lo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_f64r_lo_encode_fns[] = { + Opcode_wur_f64r_lo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_f64r_hi_encode_fns[] = { + Opcode_rur_f64r_hi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_f64r_hi_encode_fns[] = { + Opcode_wur_f64r_hi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_f64s_encode_fns[] = { + Opcode_rur_f64s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_f64s_encode_fns[] = { + Opcode_wur_f64s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { + Opcode_rur_fcr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { + Opcode_wur_fcr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { + Opcode_rur_fsr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { + Opcode_wur_fsr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 +}; + + +uint32 *bypass_entry(__attribute__((unused)) int i); +uint32 *bypass_entry(__attribute__((unused)) int i) { + return 0; +} + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "lsi", ICLASS_LSI, + 0, + Opcode_lsi_encode_fns, 0, 0 }, + { "lsip", ICLASS_LSIP, + 0, + Opcode_lsip_encode_fns, 0, 0 }, + { "lsx", ICLASS_LSX, + 0, + Opcode_lsx_encode_fns, 0, 0 }, + { "lsxp", ICLASS_LSXP, + 0, + Opcode_lsxp_encode_fns, 0, 0 }, + { "ssi", ICLASS_SSI, + 0, + Opcode_ssi_encode_fns, 0, 0 }, + { "ssip", ICLASS_SSIP, + 0, + Opcode_ssip_encode_fns, 0, 0 }, + { "ssx", ICLASS_SSX, + 0, + Opcode_ssx_encode_fns, 0, 0 }, + { "ssxp", ICLASS_SSXP, + 0, + Opcode_ssxp_encode_fns, 0, 0 }, + { "abs.s", ICLASS_ABS_S, + 0, + Opcode_abs_s_encode_fns, 0, 0 }, + { "neg.s", ICLASS_NEG_S, + 0, + Opcode_neg_s_encode_fns, 0, 0 }, + { "mov.s", ICLASS_MOV_S, + 0, + Opcode_mov_s_encode_fns, 0, 0 }, + { "moveqz.s", ICLASS_MOVEQZ_S, + 0, + Opcode_moveqz_s_encode_fns, 0, 0 }, + { "movnez.s", ICLASS_MOVNEZ_S, + 0, + Opcode_movnez_s_encode_fns, 0, 0 }, + { "movltz.s", ICLASS_MOVLTZ_S, + 0, + Opcode_movltz_s_encode_fns, 0, 0 }, + { "movgez.s", ICLASS_MOVGEZ_S, + 0, + Opcode_movgez_s_encode_fns, 0, 0 }, + { "movf.s", ICLASS_MOVF_S, + 0, + Opcode_movf_s_encode_fns, 0, 0 }, + { "movt.s", ICLASS_MOVT_S, + 0, + Opcode_movt_s_encode_fns, 0, 0 }, + { "wfr", ICLASS_WFR, + 0, + Opcode_wfr_encode_fns, 0, 0 }, + { "rfr", ICLASS_RFR, + 0, + Opcode_rfr_encode_fns, 0, 0 }, + { "round.s", ICLASS_ROUND_S, + 0, + Opcode_round_s_encode_fns, 0, 0 }, + { "ceil.s", ICLASS_CEIL_S, + 0, + Opcode_ceil_s_encode_fns, 0, 0 }, + { "floor.s", ICLASS_FLOOR_S, + 0, + Opcode_floor_s_encode_fns, 0, 0 }, + { "trunc.s", ICLASS_TRUNC_S, + 0, + Opcode_trunc_s_encode_fns, 0, 0 }, + { "utrunc.s", ICLASS_UTRUNC_S, + 0, + Opcode_utrunc_s_encode_fns, 0, 0 }, + { "float.s", ICLASS_FLOAT_S, + 0, + Opcode_float_s_encode_fns, 0, 0 }, + { "ufloat.s", ICLASS_UFLOAT_S, + 0, + Opcode_ufloat_s_encode_fns, 0, 0 }, + { "un.s", ICLASS_UN_S, + 0, + Opcode_un_s_encode_fns, 0, 0 }, + { "ult.s", ICLASS_ULT_S, + 0, + Opcode_ult_s_encode_fns, 0, 0 }, + { "ule.s", ICLASS_ULE_S, + 0, + Opcode_ule_s_encode_fns, 0, 0 }, + { "ueq.s", ICLASS_UEQ_S, + 0, + Opcode_ueq_s_encode_fns, 0, 0 }, + { "olt.s", ICLASS_OLT_S, + 0, + Opcode_olt_s_encode_fns, 0, 0 }, + { "ole.s", ICLASS_OLE_S, + 0, + Opcode_ole_s_encode_fns, 0, 0 }, + { "oeq.s", ICLASS_OEQ_S, + 0, + Opcode_oeq_s_encode_fns, 0, 0 }, + { "add.s", ICLASS_ADD_S, + 0, + Opcode_add_s_encode_fns, 0, 0 }, + { "sub.s", ICLASS_SUB_S, + 0, + Opcode_sub_s_encode_fns, 0, 0 }, + { "mul.s", ICLASS_MUL_S, + 0, + Opcode_mul_s_encode_fns, 0, 0 }, + { "madd.s", ICLASS_MADD_S, + 0, + Opcode_madd_s_encode_fns, 0, 0 }, + { "msub.s", ICLASS_MSUB_S, + 0, + Opcode_msub_s_encode_fns, 0, 0 }, + { "sqrt0.s", ICLASS_SQRT0_S, + 0, + Opcode_sqrt0_s_encode_fns, 0, 0 }, + { "div0.s", ICLASS_DIV0_S, + 0, + Opcode_div0_s_encode_fns, 0, 0 }, + { "recip0.s", ICLASS_RECIP0_S, + 0, + Opcode_recip0_s_encode_fns, 0, 0 }, + { "rsqrt0.s", ICLASS_RSQRT0_S, + 0, + Opcode_rsqrt0_s_encode_fns, 0, 0 }, + { "maddn.s", ICLASS_MADDN_S, + 0, + Opcode_maddn_s_encode_fns, 0, 0 }, + { "divn.s", ICLASS_DIVN_S, + 0, + Opcode_divn_s_encode_fns, 0, 0 }, + { "const.s", ICLASS_CONST_S, + 0, + Opcode_const_s_encode_fns, 0, 0 }, + { "nexp01.s", ICLASS_NEXP01_S, + 0, + Opcode_nexp01_s_encode_fns, 0, 0 }, + { "addexp.s", ICLASS_ADDEXP_S, + 0, + Opcode_addexp_s_encode_fns, 0, 0 }, + { "addexpm.s", ICLASS_ADDEXPM_S, + 0, + Opcode_addexpm_s_encode_fns, 0, 0 }, + { "mkdadj.s", ICLASS_MKDADJ_S, + 0, + Opcode_mkdadj_s_encode_fns, 0, 0 }, + { "mksadj.s", ICLASS_MKSADJ_S, + 0, + Opcode_mksadj_s_encode_fns, 0, 0 }, + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, + 0, + Opcode_rsr_epc7_encode_fns, 0, 0 }, + { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, + 0, + Opcode_wsr_epc7_encode_fns, 0, 0 }, + { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, + 0, + Opcode_xsr_epc7_encode_fns, 0, 0 }, + { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, + 0, + Opcode_rsr_excsave7_encode_fns, 0, 0 }, + { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, + 0, + Opcode_wsr_excsave7_encode_fns, 0, 0 }, + { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, + 0, + Opcode_xsr_excsave7_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, + 0, + Opcode_rsr_eps7_encode_fns, 0, 0 }, + { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, + 0, + Opcode_wsr_eps7_encode_fns, 0, 0 }, + { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, + 0, + Opcode_xsr_eps7_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.misc2", ICLASS_xt_iclass_rsr_misc2, + 0, + Opcode_rsr_misc2_encode_fns, 0, 0 }, + { "wsr.misc2", ICLASS_xt_iclass_wsr_misc2, + 0, + Opcode_wsr_misc2_encode_fns, 0, 0 }, + { "xsr.misc2", ICLASS_xt_iclass_xsr_misc2, + 0, + Opcode_xsr_misc2_encode_fns, 0, 0 }, + { "rsr.misc3", ICLASS_xt_iclass_rsr_misc3, + 0, + Opcode_rsr_misc3_encode_fns, 0, 0 }, + { "wsr.misc3", ICLASS_xt_iclass_wsr_misc3, + 0, + Opcode_wsr_misc3_encode_fns, 0, 0 }, + { "xsr.misc3", ICLASS_xt_iclass_xsr_misc3, + 0, + Opcode_xsr_misc3_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "muluh", ICLASS_xt_mul32h, + 0, + Opcode_muluh_encode_fns, 0, 0 }, + { "mulsh", ICLASS_xt_mul32h, + 0, + Opcode_mulsh_encode_fns, 0, 0 }, + { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.da.ll", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.da.hl", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.hh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, + { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, + { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, + { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, + { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, + { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, + { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, + { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, + { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, + { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, + { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, + { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, + { "lddec", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_lddec_encode_fns, 0, 0 }, + { "ldinc", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_ldinc_encode_fns, 0, 0 }, + { "rsr.m0", ICLASS_xt_iclass_rsr_m0, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", ICLASS_xt_iclass_wsr_m0, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", ICLASS_xt_iclass_xsr_m0, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", ICLASS_xt_iclass_rsr_m1, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", ICLASS_xt_iclass_wsr_m1, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", ICLASS_xt_iclass_xsr_m1, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", ICLASS_xt_iclass_rsr_m2, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", ICLASS_xt_iclass_wsr_m2, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", ICLASS_xt_iclass_xsr_m2, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", ICLASS_xt_iclass_rsr_m3, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", ICLASS_xt_iclass_wsr_m3, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", ICLASS_xt_iclass_xsr_m3, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 0, 0 }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "f64iter", ICLASS_iclass_F64ITER, + 0, + Opcode_f64iter_encode_fns, 0, 0 }, + { "f64rnd", ICLASS_iclass_F64RND, + 0, + Opcode_f64rnd_encode_fns, 0, 0 }, + { "f64addc", ICLASS_iclass_F64ADDC_F64SUBC, + 0, + Opcode_f64addc_encode_fns, 0, 0 }, + { "f64subc", ICLASS_iclass_F64ADDC_F64SUBC, + 0, + Opcode_f64subc_encode_fns, 0, 0 }, + { "f64sig", ICLASS_iclass_F64SIG, + 0, + Opcode_f64sig_encode_fns, 0, 0 }, + { "f64cmpl", ICLASS_iclass_F64CMPL, + 0, + Opcode_f64cmpl_encode_fns, 0, 0 }, + { "f64cmph", ICLASS_iclass_F64CMPH, + 0, + Opcode_f64cmph_encode_fns, 0, 0 }, + { "f64norm", ICLASS_iclass_F64NORM, + 0, + Opcode_f64norm_encode_fns, 0, 0 }, + { "f64sexp", ICLASS_iclass_F64SEXP, + 0, + Opcode_f64sexp_encode_fns, 0, 0 }, + { "rf64r", ICLASS_iclass_RF64R, + 0, + Opcode_rf64r_encode_fns, 0, 0 }, + { "wf64r", ICLASS_iclass_WF64R, + 0, + Opcode_wf64r_encode_fns, 0, 0 }, + { "rur.f64r_lo", ICLASS_rur_f64r_lo, + 0, + Opcode_rur_f64r_lo_encode_fns, 0, 0 }, + { "wur.f64r_lo", ICLASS_wur_f64r_lo, + 0, + Opcode_wur_f64r_lo_encode_fns, 0, 0 }, + { "rur.f64r_hi", ICLASS_rur_f64r_hi, + 0, + Opcode_rur_f64r_hi_encode_fns, 0, 0 }, + { "wur.f64r_hi", ICLASS_wur_f64r_hi, + 0, + Opcode_wur_f64r_hi_encode_fns, 0, 0 }, + { "rur.f64s", ICLASS_rur_f64s, + 0, + Opcode_rur_f64s_encode_fns, 0, 0 }, + { "wur.f64s", ICLASS_wur_f64s, + 0, + Opcode_wur_f64s_encode_fns, 0, 0 }, + { "rur.fcr", ICLASS_rur_fcr, + 0, + Opcode_rur_fcr_encode_fns, 0, 0 }, + { "wur.fcr", ICLASS_wur_fcr, + 0, + Opcode_wur_fcr_encode_fns, 0, 0 }, + { "rur.fsr", ICLASS_rur_fsr, + 0, + Opcode_rur_fsr_encode_fns, 0, 0 }, + { "wur.fsr", ICLASS_wur_fsr, + 0, + Opcode_wur_fsr_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_LSI, + OPCODE_LSIP, + OPCODE_LSX, + OPCODE_LSXP, + OPCODE_SSI, + OPCODE_SSIP, + OPCODE_SSX, + OPCODE_SSXP, + OPCODE_ABS_S, + OPCODE_NEG_S, + OPCODE_MOV_S, + OPCODE_MOVEQZ_S, + OPCODE_MOVNEZ_S, + OPCODE_MOVLTZ_S, + OPCODE_MOVGEZ_S, + OPCODE_MOVF_S, + OPCODE_MOVT_S, + OPCODE_WFR, + OPCODE_RFR, + OPCODE_ROUND_S, + OPCODE_CEIL_S, + OPCODE_FLOOR_S, + OPCODE_TRUNC_S, + OPCODE_UTRUNC_S, + OPCODE_FLOAT_S, + OPCODE_UFLOAT_S, + OPCODE_UN_S, + OPCODE_ULT_S, + OPCODE_ULE_S, + OPCODE_UEQ_S, + OPCODE_OLT_S, + OPCODE_OLE_S, + OPCODE_OEQ_S, + OPCODE_ADD_S, + OPCODE_SUB_S, + OPCODE_MUL_S, + OPCODE_MADD_S, + OPCODE_MSUB_S, + OPCODE_SQRT0_S, + OPCODE_DIV0_S, + OPCODE_RECIP0_S, + OPCODE_RSQRT0_S, + OPCODE_MADDN_S, + OPCODE_DIVN_S, + OPCODE_CONST_S, + OPCODE_NEXP01_S, + OPCODE_ADDEXP_S, + OPCODE_ADDEXPM_S, + OPCODE_MKDADJ_S, + OPCODE_MKSADJ_S, + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPNEZ, + OPCODE_LOOPGTZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPC7, + OPCODE_WSR_EPC7, + OPCODE_XSR_EPC7, + OPCODE_RSR_EXCSAVE7, + OPCODE_WSR_EXCSAVE7, + OPCODE_XSR_EXCSAVE7, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EPS7, + OPCODE_WSR_EPS7, + OPCODE_XSR_EPS7, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_MISC2, + OPCODE_WSR_MISC2, + OPCODE_XSR_MISC2, + OPCODE_RSR_MISC3, + OPCODE_WSR_MISC3, + OPCODE_XSR_MISC3, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_MULL, + OPCODE_MULUH, + OPCODE_MULSH, + OPCODE_MUL_AA_LL, + OPCODE_MUL_AA_HL, + OPCODE_MUL_AA_LH, + OPCODE_MUL_AA_HH, + OPCODE_UMUL_AA_LL, + OPCODE_UMUL_AA_HL, + OPCODE_UMUL_AA_LH, + OPCODE_UMUL_AA_HH, + OPCODE_MUL_AD_LL, + OPCODE_MUL_AD_HL, + OPCODE_MUL_AD_LH, + OPCODE_MUL_AD_HH, + OPCODE_MUL_DA_LL, + OPCODE_MUL_DA_HL, + OPCODE_MUL_DA_LH, + OPCODE_MUL_DA_HH, + OPCODE_MUL_DD_LL, + OPCODE_MUL_DD_HL, + OPCODE_MUL_DD_LH, + OPCODE_MUL_DD_HH, + OPCODE_MULA_AA_LL, + OPCODE_MULA_AA_HL, + OPCODE_MULA_AA_LH, + OPCODE_MULA_AA_HH, + OPCODE_MULS_AA_LL, + OPCODE_MULS_AA_HL, + OPCODE_MULS_AA_LH, + OPCODE_MULS_AA_HH, + OPCODE_MULA_AD_LL, + OPCODE_MULA_AD_HL, + OPCODE_MULA_AD_LH, + OPCODE_MULA_AD_HH, + OPCODE_MULS_AD_LL, + OPCODE_MULS_AD_HL, + OPCODE_MULS_AD_LH, + OPCODE_MULS_AD_HH, + OPCODE_MULA_DA_LL, + OPCODE_MULA_DA_HL, + OPCODE_MULA_DA_LH, + OPCODE_MULA_DA_HH, + OPCODE_MULS_DA_LL, + OPCODE_MULS_DA_HL, + OPCODE_MULS_DA_LH, + OPCODE_MULS_DA_HH, + OPCODE_MULA_DD_LL, + OPCODE_MULA_DD_HL, + OPCODE_MULA_DD_LH, + OPCODE_MULA_DD_HH, + OPCODE_MULS_DD_LL, + OPCODE_MULS_DD_HL, + OPCODE_MULS_DD_LH, + OPCODE_MULS_DD_HH, + OPCODE_MULA_DA_LL_LDDEC, + OPCODE_MULA_DA_LL_LDINC, + OPCODE_MULA_DA_HL_LDDEC, + OPCODE_MULA_DA_HL_LDINC, + OPCODE_MULA_DA_LH_LDDEC, + OPCODE_MULA_DA_LH_LDINC, + OPCODE_MULA_DA_HH_LDDEC, + OPCODE_MULA_DA_HH_LDINC, + OPCODE_MULA_DD_LL_LDDEC, + OPCODE_MULA_DD_LL_LDINC, + OPCODE_MULA_DD_HL_LDDEC, + OPCODE_MULA_DD_HL_LDINC, + OPCODE_MULA_DD_LH_LDDEC, + OPCODE_MULA_DD_LH_LDINC, + OPCODE_MULA_DD_HH_LDDEC, + OPCODE_MULA_DD_HH_LDINC, + OPCODE_LDDEC, + OPCODE_LDINC, + OPCODE_RSR_M0, + OPCODE_WSR_M0, + OPCODE_XSR_M0, + OPCODE_RSR_M1, + OPCODE_WSR_M1, + OPCODE_XSR_M1, + OPCODE_RSR_M2, + OPCODE_WSR_M2, + OPCODE_XSR_M2, + OPCODE_RSR_M3, + OPCODE_WSR_M3, + OPCODE_XSR_M3, + OPCODE_RSR_ACCLO, + OPCODE_WSR_ACCLO, + OPCODE_XSR_ACCLO, + OPCODE_RSR_ACCHI, + OPCODE_WSR_ACCHI, + OPCODE_XSR_ACCHI, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ANY4, + OPCODE_ALL4, + OPCODE_ANY8, + OPCODE_ALL8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOU, + OPCODE_QUOS, + OPCODE_REMU, + OPCODE_REMS, + OPCODE_RER, + OPCODE_WER, + OPCODE_F64ITER, + OPCODE_F64RND, + OPCODE_F64ADDC, + OPCODE_F64SUBC, + OPCODE_F64SIG, + OPCODE_F64CMPL, + OPCODE_F64CMPH, + OPCODE_F64NORM, + OPCODE_F64SEXP, + OPCODE_RF64R, + OPCODE_WF64R, + OPCODE_RUR_F64R_LO, + OPCODE_WUR_F64R_LO, + OPCODE_RUR_F64R_HI, + OPCODE_WUR_F64R_HI, + OPCODE_RUR_F64S, + OPCODE_WUR_F64S, + OPCODE_RUR_FCR, + OPCODE_WUR_FCR, + OPCODE_RUR_FSR, + OPCODE_WUR_FSR, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_RITLB0; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_PITLB; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_WITLB; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_RITLB1; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RDTLB0; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PDTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WDTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RDTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_XSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_XSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_XSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_XSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_XSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_XSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_XSR_M3; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_XSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_XSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_XSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_XSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_XSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_XSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_XSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_XSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_XSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MULUH; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MULSH; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_RSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_RSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_RSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_RSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_RSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_RSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_RSR_M3; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_RSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_RSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_RSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_RSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_RSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_RSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_RSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_RSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_RSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_WSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_WSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_WSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_WSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_WSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_WSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_WSR_M3; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_WSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_WSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_WSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_WSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_WSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_WSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 232) + return OPCODE_RUR_FCR; + if (Field_st_Slot_inst_get (insn) == 233) + return OPCODE_RUR_FSR; + if (Field_st_Slot_inst_get (insn) == 234) + return OPCODE_RUR_F64R_LO; + if (Field_st_Slot_inst_get (insn) == 235) + return OPCODE_RUR_F64R_HI; + if (Field_st_Slot_inst_get (insn) == 236) + return OPCODE_RUR_F64S; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WUR_FCR; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WUR_FSR; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WUR_F64R_LO; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_WUR_F64R_HI; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WUR_F64S; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 8) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_LSX; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_LSXP; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SSX; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_SSXP; + } + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_op1_Slot_inst_get (insn) == 10) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ADD_S; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_SUB_S; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_MUL_S; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MADD_S; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MSUB_S; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MADDN_S; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_DIVN_S; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ROUND_S; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_TRUNC_S; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_FLOOR_S; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_CEIL_S; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_FLOAT_S; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_UFLOAT_S; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_UTRUNC_S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_MOV_S; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_CONST_S; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_RFR; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_WFR; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_NEG_S; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DIV0_S; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_RECIP0_S; + if (Field_t_Slot_inst_get (insn) == 9) + return OPCODE_SQRT0_S; + if (Field_t_Slot_inst_get (insn) == 10) + return OPCODE_RSQRT0_S; + if (Field_t_Slot_inst_get (insn) == 11) + return OPCODE_NEXP01_S; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MKSADJ_S; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_MKDADJ_S; + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_ADDEXP_S; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_ADDEXPM_S; + } + } + if (Field_op1_Slot_inst_get (insn) == 11) + { + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_UN_S; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OEQ_S; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_UEQ_S; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_OLT_S; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_ULT_S; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_OLE_S; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_ULE_S; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ_S; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ_S; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ_S; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ_S; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF_S; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT_S; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_dfp_fld_op1_Slot_inst_get (insn) == 11) + { + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 0) + { + if (Field_dfp_fld_r_3_1_Slot_inst_get (insn) == 7) + return OPCODE_WF64R; + if (Field_dfp_fld_s_3_1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 12) + return OPCODE_RF64R; + } + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 14) + { + return OPCODE_F64CMPL; + } + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 15) + { + if (Field_dfp_fld_r_3_Slot_inst_get (insn) == 0) + return OPCODE_F64ADDC; + if (Field_dfp_fld_r_3_Slot_inst_get (insn) == 1) + return OPCODE_F64SUBC; + } + } + if (Field_dfp_fld_op1_Slot_inst_get (insn) == 14) + { + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_F64SIG; + } + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 1) + { + return OPCODE_F64SEXP; + } + if (Field_dfp_fld_op2_3_Slot_inst_get (insn) == 1) + return OPCODE_F64ITER; + if (Field_dfp_fld_op2_3_1_Slot_inst_get (insn) == 1) + return OPCODE_F64NORM; + if (Field_dfp_fld_op2_3_2_Slot_inst_get (insn) == 1) + return OPCODE_F64RND; + } + if (Field_dfp_fld_op1_Slot_inst_get (insn) == 15) + { + return OPCODE_F64CMPH; + } + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_S32C1I; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 3) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LSI; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_SSI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LSIP; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_SSIP; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 2) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 3) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 7) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 9) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDDEC; + } + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_dfp_fld_op1_Slot_inst_get, + Field_dfp_fld_op2_Slot_inst_get, + Field_dfp_fld_r_0_Slot_inst_get, + Field_dfp_fld_r_2_1_Slot_inst_get, + Field_dfp_fld_r_3_Slot_inst_get, + Field_dfp_fld_r_3_1_Slot_inst_get, + Field_dfp_fld_s_0_Slot_inst_get, + Field_dfp_fld_s_3_1_Slot_inst_get, + Field_dfp_fld_op2_0_Slot_inst_get, + Field_dfp_fld_op2_1_0_Slot_inst_get, + Field_dfp_fld_op2_2_Slot_inst_get, + Field_dfp_fld_op2_3_Slot_inst_get, + Field_dfp_fld_op2_3_2_Slot_inst_get, + Field_dfp_fld_op2_3_1_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_dfp_fld_op1_Slot_inst_set, + Field_dfp_fld_op2_Slot_inst_set, + Field_dfp_fld_r_0_Slot_inst_set, + Field_dfp_fld_r_2_1_Slot_inst_set, + Field_dfp_fld_r_3_Slot_inst_set, + Field_dfp_fld_r_3_1_Slot_inst_set, + Field_dfp_fld_s_0_Slot_inst_set, + Field_dfp_fld_s_3_1_Slot_inst_set, + Field_dfp_fld_op2_0_Slot_inst_set, + Field_dfp_fld_op2_1_0_Slot_inst_set, + Field_dfp_fld_op2_2_Slot_inst_set, + Field_dfp_fld_op2_3_Slot_inst_set, + Field_dfp_fld_op2_3_2_Slot_inst_set, + Field_dfp_fld_op2_3_1_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst16a_get, + Field_s2_Slot_inst16a_get, + Field_r2_Slot_inst16a_get, + Field_t4_Slot_inst16a_get, + Field_s4_Slot_inst16a_get, + Field_r4_Slot_inst16a_get, + Field_t8_Slot_inst16a_get, + Field_s8_Slot_inst16a_get, + Field_r8_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16a_get, + Field_dfp_fld_r_2_1_Slot_inst16a_get, + Field_dfp_fld_r_3_Slot_inst16a_get, + Field_dfp_fld_r_3_1_Slot_inst16a_get, + Field_dfp_fld_s_0_Slot_inst16a_get, + Field_dfp_fld_s_3_1_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_get, + Field_s3to1_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst16a_set, + Field_s2_Slot_inst16a_set, + Field_r2_Slot_inst16a_set, + Field_t4_Slot_inst16a_set, + Field_s4_Slot_inst16a_set, + Field_r4_Slot_inst16a_set, + Field_t8_Slot_inst16a_set, + Field_s8_Slot_inst16a_set, + Field_r8_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16a_set, + Field_dfp_fld_r_2_1_Slot_inst16a_set, + Field_dfp_fld_r_3_Slot_inst16a_set, + Field_dfp_fld_r_3_1_Slot_inst16a_set, + Field_dfp_fld_s_0_Slot_inst16a_set, + Field_dfp_fld_s_3_1_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_set, + Field_s3to1_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst16b_get, + Field_s2_Slot_inst16b_get, + Field_r2_Slot_inst16b_get, + Field_t4_Slot_inst16b_get, + Field_s4_Slot_inst16b_get, + Field_r4_Slot_inst16b_get, + Field_t8_Slot_inst16b_get, + Field_s8_Slot_inst16b_get, + Field_r8_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16b_get, + Field_dfp_fld_r_2_1_Slot_inst16b_get, + Field_dfp_fld_r_3_Slot_inst16b_get, + Field_dfp_fld_r_3_1_Slot_inst16b_get, + Field_dfp_fld_s_0_Slot_inst16b_get, + Field_dfp_fld_s_3_1_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_get, + Field_s3to1_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst16b_set, + Field_s2_Slot_inst16b_set, + Field_r2_Slot_inst16b_set, + Field_t4_Slot_inst16b_set, + Field_s4_Slot_inst16b_set, + Field_r4_Slot_inst16b_set, + Field_t8_Slot_inst16b_set, + Field_s8_Slot_inst16b_set, + Field_r8_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16b_set, + Field_dfp_fld_r_2_1_Slot_inst16b_set, + Field_dfp_fld_r_3_Slot_inst16b_set, + Field_dfp_fld_r_3_1_Slot_inst16b_set, + Field_dfp_fld_s_0_Slot_inst16b_set, + Field_dfp_fld_s_3_1_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_set, + Field_s3to1_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc) + return 2; /* x16b */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 83 /* num_fields */, + 140, operands, + 390, iclasses, + 513, opcodes, 0, + 8, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 6, interfaces, 0, + 0, funcUnits, 0 +}; From 6d0f4c5d2c09239439b422d230618fa505960205 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:34:45 +0200 Subject: [PATCH 05/16] hw/char: add ESP32 UART --- hw/char/Makefile.objs | 2 + hw/char/esp32_uart.c | 308 +++++++++++++++++++++++++++++++++++ include/hw/char/esp32_uart.h | 88 ++++++++++ 3 files changed, 398 insertions(+) create mode 100644 hw/char/esp32_uart.c create mode 100644 include/hw/char/esp32_uart.h diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 02d8a66925e72..6166c62a9c6b2 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -34,3 +34,5 @@ common-obj-$(CONFIG_SCLPCONSOLE) += sclpconsole.o sclpconsole-lm.o obj-$(CONFIG_VIRTIO) += virtio-serial-bus.o obj-$(CONFIG_TERMINAL3270) += terminal3270.o + +obj-$(CONFIG_ESP32) += esp32_uart.o diff --git a/hw/char/esp32_uart.c b/hw/char/esp32_uart.c new file mode 100644 index 0000000000000..8637e9fb4c3f7 --- /dev/null +++ b/hw/char/esp32_uart.c @@ -0,0 +1,308 @@ +/* + * ESP32 UART emulation + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * The QEMU model of nRF51 UART by Julia Suvorova was used as a template. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "sysemu/sysemu.h" +#include "chardev/char-fe.h" +#include "hw/registerfields.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/char/esp32_uart.h" +#include "trace.h" + + +static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque); +static void uart_receive(void *opaque, const uint8_t *buf, int size); + +static uint8_t fifo8_peek(Fifo8 *fifo) +{ + if (fifo->num == 0) { + abort(); + } + return fifo->data[fifo->head]; +} + +static void esp_uart_update_irq(ESP32UARTState *s) +{ + bool irq = false; + + uint32_t tx_empty_threshold = FIELD_EX32(s->reg[R_UART_CONF1], UART_CONF1, TXFIFO_EMPTY_THRD); + uint32_t rx_full_threshold = FIELD_EX32(s->reg[R_UART_CONF1], UART_CONF1, RXFIFO_FULL_THRD); + + uint32_t tx_empty_raw = (fifo8_num_free(&s->tx_fifo) <= tx_empty_threshold); + uint32_t rx_full_raw = (fifo8_num_used(&s->rx_fifo) >= rx_full_threshold); + uint32_t tx_done_raw = (fifo8_num_used(&s->tx_fifo) == 0); + + uint32_t int_raw = s->reg[R_UART_INT_RAW]; + int_raw = FIELD_DP32(int_raw, UART_INT_RAW, RXFIFO_FULL, rx_full_raw); + int_raw = FIELD_DP32(int_raw, UART_INT_RAW, TXFIFO_EMPTY, tx_empty_raw); + int_raw = FIELD_DP32(int_raw, UART_INT_RAW, TX_DONE, tx_done_raw); + s->reg[R_UART_INT_RAW] = int_raw; + + uint32_t int_st = s->reg[R_UART_INT_RAW] & s->reg[R_UART_INT_ENA]; + irq = int_st != 0; + s->reg[R_UART_INT_ST] |= int_st; + + qemu_set_irq(s->irq, irq); +} + +static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size) +{ + ESP32UARTState *s = ESP32_UART(opaque); + uint64_t r = 0; + + switch (addr) { + case A_UART_FIFO: + if (fifo8_num_used(&s->rx_fifo) == 0) { + r = 0xEE; + error_report("esp_uart: read UART FIFO while it is empty"); + } else { + r = fifo8_pop(&s->rx_fifo); + esp_uart_update_irq(s); + qemu_chr_fe_accept_input(&s->chr); + } + break; + + case A_UART_STATUS: + r = FIELD_DP32(r, UART_STATUS, RXFIFO_CNT, fifo8_num_used(&s->rx_fifo)); + r = FIELD_DP32(r, UART_STATUS, TXFIFO_CNT, fifo8_num_used(&s->tx_fifo)); + break; + + case A_UART_LOWPULSE: + case A_UART_HIGHPULSE: + r = 337; /* FIXME: this should depend on the APB frequency */ + break; + + case A_UART_DATE: + r = 0x15122500; + break; + + default: + r = s->reg[addr / 4]; + break; + } + + return r; +} + + +static void uart_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + ESP32UARTState *s = ESP32_UART(opaque); + + switch (addr) { + case A_UART_FIFO: + if (fifo8_num_free(&s->tx_fifo) == 0) { + error_report("esp_uart: write to UART FIFO while it is full"); + } else { + fifo8_push(&s->tx_fifo, (uint8_t) (value & 0xff)); + uart_transmit(NULL, G_IO_OUT, s); + } + break; + + case A_UART_INT_CLR: + s->reg[R_UART_INT_ST] &= ~((uint32_t) value); + s->reg[addr / 4] = value; + break; + + case A_UART_INT_ENA: + s->reg[addr / 4] = value; + break; + + case A_UART_AUTOBAUD: + s->autobaud_en = FIELD_EX32(value, UART_AUTOBAUD, EN); + if (!s->autobaud_en) { + s->reg[R_UART_RXD_CNT] = 0; + } + s->reg[addr / 4] = value; + break; + + case A_UART_INT_RAW: + case A_UART_INT_ST: + case A_UART_STATUS: + /* no-op */ + break; + + default: + if (addr > sizeof(s->reg)) { + error_report("esp_uart: write to addr=0x%x out of bounds\n", (uint32_t) addr); + } else { + s->reg[addr / 4] = value; + } + break; + + } + esp_uart_update_irq(s); +} + + +static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque) +{ + ESP32UARTState *s = ESP32_UART(opaque); + + s->tx_watch_handle = 0; + + while (fifo8_num_used(&s->tx_fifo) > 0) { + uint8_t b = fifo8_peek(&s->tx_fifo); + int r = qemu_chr_fe_write(&s->chr, &b, 1); + if (r == 1) { + fifo8_pop(&s->tx_fifo); + } else { + s->tx_watch_handle = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, + uart_transmit, s); + break; + } + } + + esp_uart_update_irq(s); + + return FALSE; +} + +static void uart_receive(void *opaque, const uint8_t *buf, int size) +{ + ESP32UARTState *s = ESP32_UART(opaque); + + if (size == 0) { + return; + } + + for (int i = 0; i < size && fifo8_num_free(&s->rx_fifo) > 0; i++) { + fifo8_push(&s->rx_fifo, buf[i]); + + if (s->autobaud_en) { + s->reg[R_UART_RXD_CNT] += __builtin_popcount(buf[i]) + 1; + } + } + + if (fifo8_is_full(&s->rx_fifo)) { + s->throttle_rx = true; + const int bits_per_symbol = 10; + const int baud_rate = 115200; /* FIXME: get from the divider register */ + uint64_t throttle_time_ns = (uint64_t) UART_FIFO_LENGTH * bits_per_symbol * NANOSECONDS_PER_SECOND / baud_rate; + timer_mod_ns(&s->throttle_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + throttle_time_ns); + } + + esp_uart_update_irq(s); +} + +static int uart_can_receive(void *opaque) +{ + ESP32UARTState *s = ESP32_UART(opaque); + if (s->throttle_rx) { + return 0; + } + return fifo8_num_free(&s->rx_fifo); +} + +static void uart_event(void *opaque, int event) +{ + /* TODO: handle UART break */ +} + + +static void uart_throttle_timer_cb(void* opaque) +{ + ESP32UARTState *s = ESP32_UART(opaque); + s->throttle_rx = false; + qemu_chr_fe_accept_input(&s->chr); +} + +static void esp32_uart_reset(DeviceState *dev) +{ + ESP32UARTState *s = ESP32_UART(dev); + + memset(s->reg, 0, sizeof(s->reg)); + s->autobaud_en = false; + s->reg[R_UART_RXD_CNT] = 0; + s->reg[R_UART_INT_ST] = 0; + s->reg[R_UART_INT_RAW] = 0; + s->reg[R_UART_INT_ENA] = 0; + s->reg[R_UART_AUTOBAUD] = 0; + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_fifo); + if (s->tx_watch_handle) { + g_source_remove(s->tx_watch_handle); + s->tx_watch_handle = 0; + } + timer_del(&s->throttle_timer); + s->throttle_rx = false; + qemu_irq_lower(s->irq); +} + + +static void esp32_uart_realize(DeviceState *dev, Error **errp) +{ + ESP32UARTState *s = ESP32_UART(dev); + + qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, + uart_event, NULL, s, NULL, true); +} + + +static const MemoryRegionOps uart_ops = { + .read = uart_read, + .write = uart_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_uart_init(Object *obj) +{ + ESP32UARTState *s = ESP32_UART(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &uart_ops, s, + TYPE_ESP32_UART, UART_REG_CNT * sizeof(uint32_t)); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + fifo8_create(&s->tx_fifo, UART_FIFO_LENGTH); + fifo8_create(&s->rx_fifo, UART_FIFO_LENGTH); + timer_init_ns(&s->throttle_timer, QEMU_CLOCK_VIRTUAL, uart_throttle_timer_cb, s); +} + + +static Property esp32_uart_properties[] = { + DEFINE_PROP_CHR("chardev", ESP32UARTState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_uart_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_uart_reset; + dc->realize = esp32_uart_realize; + dc->props = esp32_uart_properties; +} + +static const TypeInfo esp32_uart_info = { + .name = TYPE_ESP32_UART, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ESP32UARTState), + .instance_init = esp32_uart_init, + .class_init = esp32_uart_class_init +}; + +static void esp32_uart_register_types(void) +{ + type_register_static(&esp32_uart_info); +} + +type_init(esp32_uart_register_types) diff --git a/include/hw/char/esp32_uart.h b/include/hw/char/esp32_uart.h new file mode 100644 index 0000000000000..bfc1283f832d8 --- /dev/null +++ b/include/hw/char/esp32_uart.h @@ -0,0 +1,88 @@ +#pragma once + +#include "qemu/fifo8.h" +#include "hw/sysbus.h" +#include "chardev/char-fe.h" +#include "hw/hw.h" +#include "hw/registerfields.h" + +#define UART_FIFO_LENGTH 128 + +#define TYPE_ESP32_UART "esp_soc.uart" +#define ESP32_UART(obj) OBJECT_CHECK(ESP32UARTState, (obj), TYPE_ESP32_UART) + +REG32(UART_FIFO, 0x0) +REG32(UART_INT_RAW, 0x4) + FIELD(UART_INT_RAW, RXFIFO_FULL, 0, 1) + FIELD(UART_INT_RAW, TXFIFO_EMPTY, 1, 1) + FIELD(UART_INT_RAW, RXFIFO_OVF, 4, 1) + FIELD(UART_INT_RAW, RXFIFO_TOUT, 8, 1) + FIELD(UART_INT_RAW, TX_DONE, 14, 1) +REG32(UART_INT_ST, 0x8) + FIELD(UART_INT_ST, RXFIFO_FULL, 0, 1) + FIELD(UART_INT_ST, TXFIFO_EMPTY, 1, 1) + FIELD(UART_INT_ST, RXFIFO_OVF, 4, 1) + FIELD(UART_INT_ST, RXFIFO_TOUT, 8, 1) + FIELD(UART_INT_ST, TX_DONE, 14, 1) +REG32(UART_INT_ENA, 0xC) + FIELD(UART_INT_ENA, RXFIFO_FULL, 0, 1) + FIELD(UART_INT_ENA, TXFIFO_EMPTY, 1, 1) + FIELD(UART_INT_ENA, RXFIFO_OVF, 4, 1) + FIELD(UART_INT_ENA, RXFIFO_TOUT, 8, 1) + FIELD(UART_INT_ENA, TX_DONE, 14, 1) +REG32(UART_INT_CLR, 0x10) + FIELD(UART_INT_CLR, RXFIFO_FULL, 0, 1) + FIELD(UART_INT_CLR, TXFIFO_EMPTY, 1, 1) + FIELD(UART_INT_CLR, RXFIFO_OVF, 4, 1) + FIELD(UART_INT_CLR, RXFIFO_TOUT, 8, 1) + FIELD(UART_INT_CLR, TX_DONE, 14, 1) + +/* TODO: implement */ +REG32(UART_CLKDIV, 0x14) + FIELD(UART_CLKDIV, CLKDIV, 0, 20) + FIELD(UART_CLKDIV, CLKDIV_FRAG, 20, 4) + +REG32(UART_AUTOBAUD, 0x18) + FIELD(UART_AUTOBAUD, EN, 0, 1) + +REG32(UART_STATUS, 0x1C) + FIELD(UART_STATUS, RXFIFO_CNT, 0, 8) + FIELD(UART_STATUS, ST_URX_OUT, 8, 4) + FIELD(UART_STATUS, TXFIFO_CNT, 16, 8) + FIELD(UART_STATUS, ST_UTX_OUT, 24, 4) + +REG32(UART_LOWPULSE, 0x28) +REG32(UART_HIGHPULSE, 0x2c) +REG32(UART_RXD_CNT, 0x30) + +/* TODO: implement */ +REG32(UART_CONF0, 0x20) +REG32(UART_CONF1, 0x24) + FIELD(UART_CONF1, TOUT_EN, 31, 1) + FIELD(UART_CONF1, TOUT_THRD, 24, 7) + FIELD(UART_CONF1, TXFIFO_EMPTY_THRD, 8, 7) + FIELD(UART_CONF1, RXFIFO_FULL_THRD, 0, 7) + +REG32(UART_DATE, 0x78) + +/* Size of the register file */ +#define UART_REG_CNT (R_UART_DATE + 1) + + +typedef struct ESPUARTState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + CharBackend chr; + qemu_irq irq; + QEMUTimer throttle_timer; + bool throttle_rx; + + Fifo8 rx_fifo; + Fifo8 tx_fifo; + guint tx_watch_handle; + + uint32_t reg[UART_REG_CNT]; + bool autobaud_en; +} ESP32UARTState; + From 1cf97a0a2bd4a760eaf60f74bddf695efd232e5f Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:34:56 +0200 Subject: [PATCH 06/16] hw/gpio: add ESP32 GPIO --- hw/gpio/Makefile.objs | 1 + hw/gpio/esp32_gpio.c | 96 ++++++++++++++++++++++++++++++++++++ include/hw/gpio/esp32_gpio.h | 22 +++++++++ 3 files changed, 119 insertions(+) create mode 100644 hw/gpio/esp32_gpio.c create mode 100644 include/hw/gpio/esp32_gpio.h diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs index d305b3b24b103..36bf24609f41f 100644 --- a/hw/gpio/Makefile.objs +++ b/hw/gpio/Makefile.objs @@ -10,3 +10,4 @@ obj-$(CONFIG_IMX) += imx_gpio.o obj-$(CONFIG_RASPI) += bcm2835_gpio.o obj-$(CONFIG_NRF51_SOC) += nrf51_gpio.o obj-$(CONFIG_ASPEED_SOC) += aspeed_gpio.o +obj-$(CONFIG_ESP32) += esp32_gpio.o diff --git a/hw/gpio/esp32_gpio.c b/hw/gpio/esp32_gpio.c new file mode 100644 index 0000000000000..59e0cd6a87975 --- /dev/null +++ b/hw/gpio/esp32_gpio.c @@ -0,0 +1,96 @@ +/* + * ESP32 GPIO emulation + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/gpio/esp32_gpio.h" + + + +static uint64_t esp32_gpio_read(void *opaque, hwaddr addr, unsigned int size) +{ + Esp32GpioState *s = ESP32_GPIO(opaque); + uint64_t r = 0; + switch (addr) { + case A_GPIO_STRAP: + r = s->strap_mode; + break; + + default: + break; + } + return r; +} + +static void esp32_gpio_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ +} + +static const MemoryRegionOps uart_ops = { + .read = esp32_gpio_read, + .write = esp32_gpio_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_gpio_reset(DeviceState *dev) +{ +} + +static void esp32_gpio_realize(DeviceState *dev, Error **errp) +{ +} + +static void esp32_gpio_init(Object *obj) +{ + Esp32GpioState *s = ESP32_GPIO(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &uart_ops, s, + TYPE_ESP32_GPIO, 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static Property esp32_gpio_properties[] = { + DEFINE_PROP_UINT32("strap_mode", Esp32GpioState, strap_mode, ESP32_STRAP_MODE_FLASH_BOOT), + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_gpio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_gpio_reset; + dc->realize = esp32_gpio_realize; + dc->props = esp32_gpio_properties; +} + +static const TypeInfo esp32_gpio_info = { + .name = TYPE_ESP32_GPIO, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32GpioState), + .instance_init = esp32_gpio_init, + .class_init = esp32_gpio_class_init +}; + +static void esp32_gpio_register_types(void) +{ + type_register_static(&esp32_gpio_info); +} + +type_init(esp32_gpio_register_types) diff --git a/include/hw/gpio/esp32_gpio.h b/include/hw/gpio/esp32_gpio.h new file mode 100644 index 0000000000000..38632c3c08f10 --- /dev/null +++ b/include/hw/gpio/esp32_gpio.h @@ -0,0 +1,22 @@ +#pragma once + +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "hw/registerfields.h" + +#define TYPE_ESP32_GPIO "esp32.gpio" +#define ESP32_GPIO(obj) OBJECT_CHECK(Esp32GpioState, (obj), TYPE_ESP32_GPIO) + +REG32(GPIO_STRAP, 0x0038) + +#define ESP32_STRAP_MODE_FLASH_BOOT 0x12 +#define ESP32_STRAP_MODE_UART_BOOT 0x0f + +typedef struct Esp32GpioState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + uint32_t strap_mode; +} Esp32GpioState; + From f4318f95434887278ce0b126d62645d49cb81c59 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:35:10 +0200 Subject: [PATCH 07/16] hw/nvram: add ESP32 eFuse --- hw/nvram/Makefile.objs | 1 + hw/nvram/esp32_efuse.c | 296 +++++++++++++++++++++++++++++++++ include/hw/nvram/esp32_efuse.h | 121 ++++++++++++++ 3 files changed, 418 insertions(+) create mode 100644 hw/nvram/esp32_efuse.c create mode 100644 include/hw/nvram/esp32_efuse.h diff --git a/hw/nvram/Makefile.objs b/hw/nvram/Makefile.objs index 26f7b4ca35764..d63746dc5b516 100644 --- a/hw/nvram/Makefile.objs +++ b/hw/nvram/Makefile.objs @@ -6,3 +6,4 @@ common-obj-y += chrp_nvram.o common-obj-$(CONFIG_MAC_NVRAM) += mac_nvram.o obj-$(CONFIG_PSERIES) += spapr_nvram.o obj-$(CONFIG_NRF51_SOC) += nrf51_nvm.o +obj-$(CONFIG_ESP32) += esp32_efuse.o diff --git a/hw/nvram/esp32_efuse.c b/hw/nvram/esp32_efuse.c new file mode 100644 index 0000000000000..4809bae31c21e --- /dev/null +++ b/hw/nvram/esp32_efuse.c @@ -0,0 +1,296 @@ +/* + * ESP32 eFuse emulation + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "sysemu/sysemu.h" +#include "chardev/char-fe.h" +#include "hw/registerfields.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/nvram/esp32_efuse.h" + +static void esp32_efuse_read_op(Esp32EfuseState *s); +static void esp32_efuse_program_op(Esp32EfuseState *s); +static void esp32_efuse_update_irq(Esp32EfuseState *s); +static void esp32_efuse_op_timer_start(Esp32EfuseState *s); + +static uint64_t esp32_efuse_read(void *opaque, hwaddr addr, unsigned int size) +{ + Esp32EfuseState *s = ESP32_EFUSE(opaque); + uint64_t r = 0; + int idx; + switch (addr) { + case A_EFUSE_BLK0_RDATA0 ... A_EFUSE_BLK0_WDATA0 - 4: + idx = (addr - A_EFUSE_BLK0_RDATA0) / 4; + r = s->efuse_rd.blk0[idx] & ~(s->efuse_rd_dis.blk0[idx]); + break; + case A_EFUSE_BLK0_WDATA0 ... A_EFUSE_BLK1_RDATA0 - 4: + r = s->efuse_wr.blk0[(addr - A_EFUSE_BLK0_WDATA0) / 4]; + break; + case A_EFUSE_BLK1_RDATA0 ... A_EFUSE_BLK2_RDATA0 - 4: + idx = (addr - A_EFUSE_BLK1_RDATA0) / 4; + r = s->efuse_rd.blk1[idx] & ~(s->efuse_rd_dis.blk1[idx]); + break; + case A_EFUSE_BLK2_RDATA0 ... A_EFUSE_BLK3_RDATA0 - 4: + idx = (addr - A_EFUSE_BLK2_RDATA0) / 4; + r = s->efuse_rd.blk2[idx] & ~(s->efuse_rd_dis.blk2[idx]); + break; + case A_EFUSE_BLK3_RDATA0 ... A_EFUSE_BLK1_WDATA0 - 4: + idx = (addr - A_EFUSE_BLK3_RDATA0) / 4; + r = s->efuse_rd.blk3[idx] & ~(s->efuse_rd_dis.blk3[idx]); + break; + case A_EFUSE_BLK1_WDATA0 ... A_EFUSE_BLK2_WDATA0 - 4: + r = s->efuse_wr.blk1[(addr - A_EFUSE_BLK1_WDATA0) / 4]; + break; + case A_EFUSE_BLK2_WDATA0 ... A_EFUSE_BLK3_WDATA0 - 4: + r = s->efuse_wr.blk2[(addr - A_EFUSE_BLK2_WDATA0) / 4]; + break; + case A_EFUSE_BLK3_WDATA0 ... A_EFUSE_CLK - 4: + r = s->efuse_wr.blk3[(addr - A_EFUSE_BLK3_WDATA0) / 4]; + break; + case A_EFUSE_CLK: + r = s->clk_reg; + break; + case A_EFUSE_CONF: + r = s->conf_reg; + break; + case A_EFUSE_CMD: + r = s->cmd_reg; + break; + case A_EFUSE_STATUS: + r = 0; + break; + case A_EFUSE_DAC_CONF: + r = s->dac_conf_reg; + break; + case A_EFUSE_INT_RAW: + r = s->int_raw_reg; + break; + case A_EFUSE_INT_ST: + r = s->int_st_reg; + break; + case A_EFUSE_INT_ENA: + r = s->int_ena_reg; + break; + case A_EFUSE_DEC_STATUS: + r = 0; + break; + case A_EFUSE_DATE: + r = 0x16042600; + } + return r; +} + +static void esp32_efuse_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + Esp32EfuseState *s = ESP32_EFUSE(opaque); + switch (addr) { + case A_EFUSE_CLK: + s->clk_reg = value; + break; + case A_EFUSE_CONF: + s->conf_reg = value; + break; + case A_EFUSE_CMD: + if ((value & EFUSE_READ) && s->conf_reg == EFUSE_READ_OP_CODE) { + esp32_efuse_read_op(s); + } + if ((value & EFUSE_PGM) && s->conf_reg == EFUSE_PGM_OP_CODE) { + esp32_efuse_program_op(s); + } + break; + case A_EFUSE_DAC_CONF: + s->dac_conf_reg = value; + break; + case A_EFUSE_INT_ENA: + s->int_ena_reg = value; + esp32_efuse_update_irq(s); + break; + case A_EFUSE_INT_CLR: + s->int_raw_reg &= ~value; + esp32_efuse_update_irq(s); + break; + case A_EFUSE_BLK0_WDATA0 ... A_EFUSE_BLK1_RDATA0 - 4: + s->efuse_wr.blk0[(addr - A_EFUSE_BLK0_WDATA0) / 4] = value; + break; + case A_EFUSE_BLK1_WDATA0 ... A_EFUSE_BLK2_WDATA0 - 4: + s->efuse_wr.blk1[(addr - A_EFUSE_BLK1_WDATA0) / 4] = value; + break; + case A_EFUSE_BLK2_WDATA0 ... A_EFUSE_BLK3_WDATA0 - 4: + s->efuse_wr.blk2[(addr - A_EFUSE_BLK2_WDATA0) / 4] = value; + break; + case A_EFUSE_BLK3_WDATA0 ... A_EFUSE_CLK - 4: + s->efuse_wr.blk3[(addr - A_EFUSE_BLK3_WDATA0) / 4] = value; + break; + } +} + +#define APPLY_DIS(rdwr_, ctrl_field_, dest_field_) \ + if (s->efuse_ ## rdwr_ .blk0_d0.ctrl_field_) { \ + memset(&s->efuse_ ## rdwr_ ## _dis.dest_field_, 0xff, sizeof(s->efuse_ ## rdwr_ ## _dis.dest_field_)); \ + } + +#define APPLY_DIS_FIELD(rdwr_, ctrl_field_, dest_field_) \ + if (s->efuse_ ## rdwr_ .blk0_d0.ctrl_field_) { \ + s->efuse_ ## rdwr_ ## _dis.dest_field_ = 0; \ + s->efuse_ ## rdwr_ ## _dis.dest_field_ -= 1; \ + } + + +static void esp32_efuse_read_op(Esp32EfuseState *s) +{ + s->cmd_reg = EFUSE_READ; + if (s->blk != NULL) { + uint64_t perm = BLK_PERM_CONSISTENT_READ | + (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE); + int ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, NULL); + if (ret != 0) { + fprintf(stderr, "%s: failed to set permission (%d)\n", __func__, ret); + } + ret = blk_pread(s->blk, 0, &s->efuse_rd, sizeof(s->efuse_rd)); + if (ret != sizeof(s->efuse_rd)) { + fprintf(stderr, "%s: failed to read the block device (%d)\n", __func__, ret); + } + } + + memset(&s->efuse_rd_dis, 0, sizeof(s->efuse_rd_dis)); + memset(&s->efuse_wr_dis, 0, sizeof(s->efuse_wr_dis)); + + APPLY_DIS(rd, rd_dis_blk1, blk1); + APPLY_DIS(rd, rd_dis_blk2, blk2); + APPLY_DIS(rd, rd_dis_blk3, blk3); + APPLY_DIS_FIELD(rd, rd_dis_blk0_partial, blk0_d5.flash_crypt_config); + APPLY_DIS_FIELD(rd, rd_dis_blk0_partial, blk0_d6.coding_scheme); + APPLY_DIS_FIELD(rd, rd_dis_blk0_partial, blk0_d6.key_status); + + APPLY_DIS(wr, wr_dis_blk1, blk1); + APPLY_DIS(wr, wr_dis_blk2, blk2); + APPLY_DIS(wr, wr_dis_blk3, blk3); + + /* Other wr_dis bits are not emulated, but can be handled here if necessary */ + + esp32_efuse_op_timer_start(s); +} + +static void esp32_efuse_program_op(Esp32EfuseState *s) +{ + s->cmd_reg = EFUSE_PGM; + + Esp32EfuseRegs result; + uint32_t* dst = (uint32_t*) &result; + uint32_t* rd = (uint32_t*) &s->efuse_rd; + uint32_t* wr = (uint32_t*) &s->efuse_wr; + uint32_t* wr_dis = (uint32_t*) &s->efuse_wr_dis; + for (int i = 0; i < sizeof(result) / sizeof(uint32_t); ++i) { + uint32_t wr_word = wr[i]; + uint32_t wr_dis_word = wr_dis[i]; + uint32_t rd_word = rd[i]; + dst[i] = (wr_word & (~wr_dis_word)) | (rd_word & wr_dis_word); + } + + if (s->blk != NULL) { + int ret = blk_pwrite(s->blk, 0, &result, sizeof(result), 0); + if (ret != sizeof(result)) { + fprintf(stderr, "%s: failed to write to block device (%d)\n", __func__, ret); + } + } + + esp32_efuse_op_timer_start(s); +} + +static void esp32_efuse_update_irq(Esp32EfuseState *s) +{ + s->int_st_reg = s->int_ena_reg & s->int_raw_reg; + int level = s->int_st_reg != 0; + qemu_set_irq(s->irq, level); +} + +static void esp32_efuse_op_timer_start(Esp32EfuseState *s) +{ + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t interval_ns = 100000000; /* 10 ms, make this depend on EFUSE_CLK register */ + timer_mod_anticipate_ns(&s->op_timer, ns_now + interval_ns); +} + +static void esp32_efuse_timer_cb(void *opaque) +{ + Esp32EfuseState *s = ESP32_EFUSE(opaque); + uint32_t cmd = s->cmd_reg; + s->cmd_reg = 0; + s->int_raw_reg |= cmd; + esp32_efuse_update_irq(s); +} + +static const MemoryRegionOps esp32_efuse_ops = { + .read = esp32_efuse_read, + .write = esp32_efuse_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_efuse_reset(DeviceState *dev) +{ + Esp32EfuseState *s = ESP32_EFUSE(dev); + esp32_efuse_read_op(s); +} + +static void esp32_efuse_realize(DeviceState *dev, Error **errp) +{ +} + +static void esp32_efuse_init(Object *obj) +{ + Esp32EfuseState *s = ESP32_EFUSE(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &esp32_efuse_ops, s, + TYPE_ESP32_EFUSE, A_EFUSE_DATE + 4); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + + timer_init_ns(&s->op_timer, QEMU_CLOCK_VIRTUAL, esp32_efuse_timer_cb, s); + + memset(&s->efuse_rd, 0, sizeof(s->efuse_rd)); + memset(&s->efuse_wr, 0, sizeof(s->efuse_wr)); +} + +static Property esp32_efuse_properties[] = { + DEFINE_PROP_DRIVE("drive", Esp32EfuseState, blk), + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_efuse_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_efuse_reset; + dc->realize = esp32_efuse_realize; + dc->props = esp32_efuse_properties; +} + +static const TypeInfo esp32_efuse_info = { + .name = TYPE_ESP32_EFUSE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32EfuseState), + .instance_init = esp32_efuse_init, + .class_init = esp32_efuse_class_init +}; + +static void esp32_efuse_register_types(void) +{ + type_register_static(&esp32_efuse_info); +} + +type_init(esp32_efuse_register_types) diff --git a/include/hw/nvram/esp32_efuse.h b/include/hw/nvram/esp32_efuse.h new file mode 100644 index 0000000000000..1dcd2e20b7bdc --- /dev/null +++ b/include/hw/nvram/esp32_efuse.h @@ -0,0 +1,121 @@ +#pragma once + +#include "hw/hw.h" +#include "hw/registerfields.h" +#include "hw/sysbus.h" +#include "hw/misc/esp32_reg.h" +#include "sysemu/block-backend.h" + +#define TYPE_ESP32_EFUSE "nvram.esp32.efuse" +#define ESP32_EFUSE(obj) OBJECT_CHECK(Esp32EfuseState, (obj), TYPE_ESP32_EFUSE) + +REG32(EFUSE_BLK0_RDATA0, 0x00) +REG32(EFUSE_BLK0_WDATA0, 0x1c) +REG32(EFUSE_BLK1_RDATA0, 0x38) +REG32(EFUSE_BLK2_RDATA0, 0x58) +REG32(EFUSE_BLK3_RDATA0, 0x78) +REG32(EFUSE_BLK1_WDATA0, 0x98) +REG32(EFUSE_BLK2_WDATA0, 0xb8) +REG32(EFUSE_BLK3_WDATA0, 0xd8) +REG32(EFUSE_CLK, 0xf8) +REG32(EFUSE_CONF, 0xfc) + FIELD(EFUSE_CONF, OP_CODE, 0, 16) +REG32(EFUSE_STATUS, 0x100) +REG32(EFUSE_CMD, 0x104) +REG32(EFUSE_INT_RAW, 0x108) +REG32(EFUSE_INT_ST, 0x10c) +REG32(EFUSE_INT_ENA, 0x110) +REG32(EFUSE_INT_CLR, 0x114) +REG32(EFUSE_DAC_CONF, 0x118) +REG32(EFUSE_DEC_STATUS, 0x11c) +REG32(EFUSE_DATE, 0x1fc) + +/* the following bit masks apply to CMD, INT_RAW, INT_ST, INT_ENA, INT_CLR */ +#define EFUSE_READ 0x01 +#define EFUSE_PGM 0x02 + +/* expected values of EFUSE_CONF OP_CODE field */ +#define EFUSE_READ_OP_CODE 0x5AA5 +#define EFUSE_PGM_OP_CODE 0x5A5A + + +typedef struct Esp32EfuseRegs { + union { + struct { + struct { + uint32_t wr_dis_rd_dis : 1; + uint32_t wr_dis_wr_dis : 1; + uint32_t wr_dis_flash_crypt_cnt : 1; + uint32_t wr_dis_mac_spi_config : 1; + uint32_t wr_dis_unused1 : 1; + uint32_t wr_dis_xpd_sdio : 1; + uint32_t wr_dis_spi_pad_config : 1; + uint32_t wr_dis_blk1 : 1; + uint32_t wr_dis_blk2 : 1; + uint32_t wr_dis_blk3 : 1; + uint32_t wr_dis_flash_crypt_coding_scheme : 1; + uint32_t wr_dis_unused2 : 1; + uint32_t wr_dis_abs_done_0 : 1; + uint32_t wr_dis_abs_done_1 : 1; + uint32_t wr_dis_jtag_disable : 1; + uint32_t wr_dis_console_dl_disable : 1; + + uint32_t rd_dis_blk1 : 1; + uint32_t rd_dis_blk2 : 1; + uint32_t rd_dis_blk3 : 1; + uint32_t rd_dis_blk0_partial : 1; + + uint32_t flash_crypt_cnt : 7; + } blk0_d0; + uint32_t blk0_d1; + uint32_t blk0_d2; + uint32_t blk0_d3; + uint32_t blk0_d4; + struct { + uint32_t blk0_d5_misc : 28; + uint32_t flash_crypt_config : 4; + } blk0_d5; + struct { + uint32_t coding_scheme : 2; + uint32_t console_debug_dis : 1; + uint32_t dis_sdio_host : 1; + uint32_t abs_done_0 : 1; + uint32_t abs_done_1 : 1; + uint32_t dis_jtag : 1; + uint32_t dis_dl_encrypt : 1; + uint32_t dis_dl_decrypt : 1; + uint32_t dis_dl_cache : 1; + uint32_t key_status : 1; + } blk0_d6; + }; + uint32_t blk0[7]; + }; + uint32_t blk1[8]; + uint32_t blk2[8]; + uint32_t blk3[8]; +} Esp32EfuseRegs; + + +typedef struct Esp32EfuseState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + BlockBackend *blk; + QEMUTimer op_timer; + + Esp32EfuseRegs efuse_wr; + Esp32EfuseRegs efuse_wr_dis; + Esp32EfuseRegs efuse_rd; + Esp32EfuseRegs efuse_rd_dis; + + uint32_t clk_reg; + uint32_t conf_reg; + uint32_t status_reg; + uint32_t cmd_reg; + uint32_t int_raw_reg; + uint32_t int_st_reg; + uint32_t int_ena_reg; + uint32_t dac_conf_reg; +} Esp32EfuseState; + From 402a84b6dbde4dcf45b58eebb4b1ea87e5fd72f6 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:35:25 +0200 Subject: [PATCH 08/16] hw/spi: add ESP32 SPI --- hw/ssi/Makefile.objs | 1 + hw/ssi/esp32_spi.c | 349 +++++++++++++++++++++++++++++++++++++ include/hw/ssi/esp32_spi.h | 88 ++++++++++ 3 files changed, 438 insertions(+) create mode 100644 hw/ssi/esp32_spi.c create mode 100644 include/hw/ssi/esp32_spi.h diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs index f5bcc65fe7995..c995c2f71790e 100644 --- a/hw/ssi/Makefile.objs +++ b/hw/ssi/Makefile.objs @@ -8,3 +8,4 @@ common-obj-$(CONFIG_MSF2) += mss-spi.o obj-$(CONFIG_OMAP) += omap_spi.o obj-$(CONFIG_IMX) += imx_spi.o +obj-$(CONFIG_ESP32) += esp32_spi.o diff --git a/hw/ssi/esp32_spi.c b/hw/ssi/esp32_spi.c new file mode 100644 index 0000000000000..ec0ce1776f22d --- /dev/null +++ b/hw/ssi/esp32_spi.c @@ -0,0 +1,349 @@ +/* + * ESP32 SPI controller + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "sysemu/sysemu.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/ssi/ssi.h" +#include "hw/ssi/esp32_spi.h" + + + +enum { + CMD_RES = 0xab, + CMD_DP = 0xb9, + CMD_CE = 0x60, + CMD_BE = 0xD8, + CMD_SE = 0x20, + CMD_PP = 0x02, + CMD_WRSR = 0x1, + CMD_RDSR = 0x5, + CMD_RDID = 0x9f, + CMD_WRDI = 0x4, + CMD_WREN = 0x6, + CMD_READ = 0x03, +}; + + +#define ESP32_SPI_REG_SIZE 0x1000 + +static void esp32_spi_do_command(Esp32SpiState* state, uint32_t cmd_reg); + +static uint64_t esp32_spi_read(void *opaque, hwaddr addr, unsigned int size) +{ + Esp32SpiState *s = ESP32_SPI(opaque); + uint64_t r = 0; + switch (addr) { + case A_SPI_ADDR: + r = s->addr_reg; + break; + case A_SPI_CTRL: + r = s->ctrl_reg; + break; + case A_SPI_STATUS: + r = s->status_reg; + break; + case A_SPI_CTRL1: + r = s->ctrl1_reg; + break; + case A_SPI_CTRL2: + r = s->ctrl2_reg; + break; + case A_SPI_USER: + r = s->user_reg; + break; + case A_SPI_USER1: + r = s->user1_reg; + break; + case A_SPI_USER2: + r = s->user2_reg; + break; + case A_SPI_MOSI_DLEN: + r = s->mosi_dlen_reg; + break; + case A_SPI_MISO_DLEN: + r = s->miso_dlen_reg; + break; + case A_SPI_PIN: + r = s->pin_reg; + break; + case A_SPI_W0 ... A_SPI_W0 + (ESP32_SPI_BUF_WORDS - 1) * sizeof(uint32_t): + r = s->data_reg[(addr - A_SPI_W0) / sizeof(uint32_t)]; + break; + case A_SPI_EXT2: + r = 0; + break; + } + return r; +} + +static void esp32_spi_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + Esp32SpiState *s = ESP32_SPI(opaque); + switch (addr) { + case A_SPI_W0 ... A_SPI_W0 + (ESP32_SPI_BUF_WORDS - 1) * sizeof(uint32_t): + s->data_reg[(addr - A_SPI_W0) / sizeof(uint32_t)] = value; + break; + case A_SPI_ADDR: + s->addr_reg = value; + break; + case A_SPI_CTRL: + s->ctrl_reg = value; + break; + case A_SPI_STATUS: + s->status_reg = value; + break; + case A_SPI_CTRL1: + s->ctrl1_reg = value; + break; + case A_SPI_CTRL2: + s->ctrl2_reg = value; + break; + case A_SPI_USER: + s->user_reg = value; + break; + case A_SPI_USER1: + s->user1_reg = value; + break; + case A_SPI_USER2: + s->user2_reg = value; + break; + case A_SPI_MOSI_DLEN: + s->mosi_dlen_reg = value; + break; + case A_SPI_MISO_DLEN: + s->miso_dlen_reg = value; + break; + case A_SPI_PIN: + s->pin_reg = value; + break; + case A_SPI_CMD: + esp32_spi_do_command(s, value); + break; + } +} + +typedef struct Esp32SpiTransaction { + int cmd_bytes; + uint32_t cmd; + int addr_bytes; + uint32_t addr; + int data_tx_bytes; + int data_rx_bytes; + uint32_t* data; +} Esp32SpiTransaction; + +static void esp32_spi_txrx_buffer(Esp32SpiState *s, void *buf, int tx_bytes, int rx_bytes) +{ + int bytes = MAX(tx_bytes, rx_bytes); + uint8_t *c_buf = (uint8_t*) buf; + for (int i = 0; i < bytes; ++i) { + uint8_t byte = 0; + if (byte < tx_bytes) { + memcpy(&byte, c_buf + i, 1); + } + uint32_t res = ssi_transfer(s->spi, byte); + if (byte < rx_bytes) { + memcpy(c_buf + i, &res, 1); + } + } +} + +static void esp32_spi_cs_set(Esp32SpiState *s, int value) +{ + for (int i = 0; i < ESP32_SPI_CS_COUNT; ++i) { + qemu_set_irq(s->cs_gpio[i], ((s->pin_reg & (1 << i)) == 0) ? value : 1); + } +} + +static void esp32_spi_transaction(Esp32SpiState *s, Esp32SpiTransaction *t) +{ + esp32_spi_cs_set(s, 0); + esp32_spi_txrx_buffer(s, &t->cmd, t->cmd_bytes, 0); + esp32_spi_txrx_buffer(s, &t->addr, t->addr_bytes, 0); + esp32_spi_txrx_buffer(s, t->data, t->data_tx_bytes, t->data_rx_bytes); + esp32_spi_cs_set(s, 1); +} + +/* Convert one of the hardware "bitlen" registers to a byte count */ +static inline int bitlen_to_bytes(uint32_t val) +{ + return (val + 1 + 7) / 8; /* bitlen registers hold number of bits, minus one */ +} + +static void esp32_spi_do_command(Esp32SpiState* s, uint32_t cmd_reg) +{ + Esp32SpiTransaction t = { + .cmd_bytes = 1 + }; + switch (cmd_reg) { + case R_SPI_CMD_READ_MASK: + t.cmd = CMD_READ; + t.addr_bytes = bitlen_to_bytes(FIELD_EX32(s->user1_reg, SPI_USER1, ADDR_BITLEN)); + t.addr = bswap32(s->addr_reg) >> (32 - t.addr_bytes * 8); + t.data = &s->data_reg[0]; + t.data_rx_bytes = bitlen_to_bytes(s->miso_dlen_reg); + break; + + case R_SPI_CMD_WREN_MASK: + t.cmd = CMD_WREN; + break; + + case R_SPI_CMD_WRDI_MASK: + t.cmd = CMD_WRDI; + break; + + case R_SPI_CMD_RDID_MASK: + t.cmd = CMD_RDID; + t.data = &s->data_reg[0]; + t.data_rx_bytes = 3; + break; + + case R_SPI_CMD_RDSR_MASK: + t.cmd = CMD_RDSR; + t.data = &s->status_reg; + t.data_rx_bytes = 1; + break; + + case R_SPI_CMD_WRSR_MASK: + t.cmd = CMD_WRSR; + t.data = &s->status_reg; + t.data_tx_bytes = 1; + break; + + case R_SPI_CMD_PP_MASK: + t.cmd = CMD_PP; + t.data = &s->data_reg[0]; + t.addr_bytes = bitlen_to_bytes(FIELD_EX32(s->user1_reg, SPI_USER1, ADDR_BITLEN)); + t.addr = bswap32(s->addr_reg) >> 8; + t.data = &s->data_reg[0]; + t.data_tx_bytes = s->addr_reg >> 24; + break; + + case R_SPI_CMD_SE_MASK: + t.cmd = CMD_SE; + t.addr_bytes = bitlen_to_bytes(FIELD_EX32(s->user1_reg, SPI_USER1, ADDR_BITLEN)); + t.addr = bswap32(s->addr_reg) >> (32 - t.addr_bytes * 8); + break; + + case R_SPI_CMD_BE_MASK: + t.cmd = CMD_BE; + t.addr_bytes = bitlen_to_bytes(FIELD_EX32(s->user1_reg, SPI_USER1, ADDR_BITLEN)); + t.addr = bswap32(s->addr_reg) >> (32 - t.addr_bytes * 8); + break; + + case R_SPI_CMD_CE_MASK: + t.cmd = CMD_CE; + break; + + case R_SPI_CMD_DP_MASK: + t.cmd = CMD_DP; + break; + + case R_SPI_CMD_RES_MASK: + t.cmd = CMD_RES; + t.data = &s->data_reg[0]; + t.data_rx_bytes = 3; + break; + + case R_SPI_CMD_USR_MASK: + if (FIELD_EX32(s->user_reg, SPI_USER, COMMAND) || FIELD_EX32(s->user2_reg, SPI_USER2, COMMAND_BITLEN)) { + t.cmd = FIELD_EX32(s->user2_reg, SPI_USER2, COMMAND_VALUE); + t.cmd_bytes = bitlen_to_bytes(FIELD_EX32(s->user2_reg, SPI_USER2, COMMAND_BITLEN)); + } else { + t.cmd_bytes = 0; + } + if (FIELD_EX32(s->user_reg, SPI_USER, ADDR)) { + t.addr_bytes = bitlen_to_bytes(FIELD_EX32(s->user1_reg, SPI_USER1, ADDR_BITLEN)); + t.addr = bswap32(s->addr_reg); + } + if (FIELD_EX32(s->user_reg, SPI_USER, MOSI)) { + t.data = &s->data_reg[0]; + t.data_tx_bytes = bitlen_to_bytes(s->mosi_dlen_reg); + } + if (FIELD_EX32(s->user_reg, SPI_USER, MISO)) { + t.data = &s->data_reg[0]; + t.data_rx_bytes = bitlen_to_bytes(s->miso_dlen_reg); + } + break; + default: + return; + } + esp32_spi_transaction(s, &t); +} + + +static const MemoryRegionOps esp32_spi_ops = { + .read = esp32_spi_read, + .write = esp32_spi_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_spi_reset(DeviceState *dev) +{ + Esp32SpiState *s = ESP32_SPI(dev); + s->pin_reg = 0x6; + s->user1_reg = FIELD_DP32(0, SPI_USER1, ADDR_BITLEN, 23); + s->user1_reg = FIELD_DP32(s->user1_reg, SPI_USER1, DUMMY_CYCLELEN, 7); + s->status_reg = 0; +} + +static void esp32_spi_realize(DeviceState *dev, Error **errp) +{ +} + +static void esp32_spi_init(Object *obj) +{ + Esp32SpiState *s = ESP32_SPI(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &esp32_spi_ops, s, + TYPE_ESP32_SPI, ESP32_SPI_REG_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + + s->spi = ssi_create_bus(DEVICE(s), "spi"); + qdev_init_gpio_out_named(DEVICE(s), &s->cs_gpio[0], SSI_GPIO_CS, ESP32_SPI_CS_COUNT); +} + +static Property esp32_spi_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_spi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_spi_reset; + dc->realize = esp32_spi_realize; + dc->props = esp32_spi_properties; +} + +static const TypeInfo esp32_spi_info = { + .name = TYPE_ESP32_SPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32SpiState), + .instance_init = esp32_spi_init, + .class_init = esp32_spi_class_init +}; + +static void esp32_spi_register_types(void) +{ + type_register_static(&esp32_spi_info); +} + +type_init(esp32_spi_register_types) diff --git a/include/hw/ssi/esp32_spi.h b/include/hw/ssi/esp32_spi.h new file mode 100644 index 0000000000000..9002745ade33f --- /dev/null +++ b/include/hw/ssi/esp32_spi.h @@ -0,0 +1,88 @@ +#pragma once + +#include "hw/hw.h" +#include "hw/registerfields.h" +#include "hw/ssi/ssi.h" + +#define TYPE_ESP32_SPI "ssi.esp32.spi" +#define ESP32_SPI(obj) OBJECT_CHECK(Esp32SpiState, (obj), TYPE_ESP32_SPI) + +#define ESP32_SPI_CS_COUNT 3 +#define ESP32_SPI_BUF_WORDS 16 + +typedef struct Esp32SpiState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + qemu_irq cs_gpio[ESP32_SPI_CS_COUNT]; + int num_cs; + SSIBus *spi; + + uint32_t addr_reg; + uint32_t ctrl_reg; + uint32_t status_reg; + uint32_t ctrl1_reg; + uint32_t ctrl2_reg; + uint32_t user_reg; + uint32_t user1_reg; + uint32_t user2_reg; + uint32_t mosi_dlen_reg; + uint32_t miso_dlen_reg; + uint32_t pin_reg; + uint32_t data_reg[ESP32_SPI_BUF_WORDS]; +} Esp32SpiState; + + +REG32(SPI_CMD, 0x00) + FIELD(SPI_CMD, READ, 31, 1) + FIELD(SPI_CMD, WREN, 30, 1) + FIELD(SPI_CMD, WRDI, 29, 1) + FIELD(SPI_CMD, RDID, 28, 1) + FIELD(SPI_CMD, RDSR, 27, 1) + FIELD(SPI_CMD, WRSR, 26, 1) + FIELD(SPI_CMD, PP, 25, 1) + FIELD(SPI_CMD, SE, 24, 1) + FIELD(SPI_CMD, BE, 23, 1) + FIELD(SPI_CMD, CE, 22, 1) + FIELD(SPI_CMD, DP, 21, 1) + FIELD(SPI_CMD, RES, 20, 1) + FIELD(SPI_CMD, HPM, 19, 1) + FIELD(SPI_CMD, USR, 18, 1) + FIELD(SPI_CMD, PES, 17, 1) + FIELD(SPI_CMD, PER, 16, 1) + +REG32(SPI_ADDR, 0x04) +REG32(SPI_CTRL, 0x08) +REG32(SPI_STATUS, 0x10) + FIELD(SPI_STATUS, STATUS, 0, 16) + +REG32(SPI_CTRL1, 0x0c) +REG32(SPI_CTRL2, 0x14) +REG32(SPI_USER, 0x1C) + FIELD(SPI_USER, COMMAND, 31, 1) + FIELD(SPI_USER, ADDR, 30, 1) + FIELD(SPI_USER, DUMMY, 29, 1) + FIELD(SPI_USER, MISO, 28, 1) + FIELD(SPI_USER, MOSI, 27, 1) + FIELD(SPI_USER, SIO, 16, 1) + FIELD(SPI_USER, DOUTDIN, 0, 1) + +REG32(SPI_USER1, 0x20) + FIELD(SPI_USER1, ADDR_BITLEN, 26, 6) + FIELD(SPI_USER1, DUMMY_CYCLELEN, 0, 8) + +REG32(SPI_USER2, 0x24) + FIELD(SPI_USER2, COMMAND_BITLEN, 28, 4) + FIELD(SPI_USER2, COMMAND_VALUE, 0, 16) + +REG32(SPI_MOSI_DLEN, 0x28) +REG32(SPI_MISO_DLEN, 0x2c) +REG32(SPI_PIN, 0x34) +REG32(SPI_W0, 0x80) +REG32(SPI_EXT0, 0xF0) +REG32(SPI_EXT1, 0xF4) +REG32(SPI_EXT2, 0xF8) +REG32(SPI_EXT3, 0xFC) + + From 17c17071dd9f923bf929e7f6c1ff6b4210ed851f Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:37:31 +0200 Subject: [PATCH 09/16] hw/misc: add ESP32 DPORT peripheral --- hw/misc/Makefile.objs | 4 + hw/misc/esp32_crosscore_int.c | 91 ++++++ hw/misc/esp32_dport.c | 438 ++++++++++++++++++++++++++ hw/misc/esp32_intmatrix.c | 144 +++++++++ include/hw/misc/esp32_crosscore_int.h | 17 + include/hw/misc/esp32_dport.h | 183 +++++++++++ 6 files changed, 877 insertions(+) create mode 100644 hw/misc/esp32_crosscore_int.c create mode 100644 hw/misc/esp32_dport.c create mode 100644 hw/misc/esp32_intmatrix.c create mode 100644 include/hw/misc/esp32_crosscore_int.h create mode 100644 include/hw/misc/esp32_dport.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781afc..311674185991e 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -82,3 +82,7 @@ common-obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o obj-$(CONFIG_MAC_VIA) += mac_via.o common-obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o + +obj-$(CONFIG_ESP32) += esp32_dport.o +obj-$(CONFIG_ESP32) += esp32_intmatrix.o +obj-$(CONFIG_ESP32) += esp32_crosscore_int.o diff --git a/hw/misc/esp32_crosscore_int.c b/hw/misc/esp32_crosscore_int.c new file mode 100644 index 0000000000000..6fec0978355ba --- /dev/null +++ b/hw/misc/esp32_crosscore_int.c @@ -0,0 +1,91 @@ +/* + * ESP32 Cross-core interrupt + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "hw/misc/esp32_reg.h" +#include "hw/misc/esp32_crosscore_int.h" + + +static uint64_t esp32_crosscore_int_read(void *opaque, hwaddr addr, unsigned int size) +{ + return 0; +} + +static void esp32_crosscore_int_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + Esp32CrosscoreInt *s = ESP32_CROSSCORE_INT(opaque); + int index = addr / 4; + assert(index < s->n_irqs); + qemu_set_irq(s->irqs[index], value & 0x1); +} + +static const MemoryRegionOps esp32_crosscore_int_ops = { + .read = esp32_crosscore_int_read, + .write = esp32_crosscore_int_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_crosscore_int_realize(DeviceState *dev, Error **errp) +{ + Esp32CrosscoreInt *s = ESP32_CROSSCORE_INT(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + s->irqs = g_malloc0_n(s->n_irqs, sizeof(qemu_irq)); + assert(s->irqs); + for (int i = 0; i < s->n_irqs; ++i) { + sysbus_init_irq(sbd, &s->irqs[i]); + } + + memory_region_init_io(&s->iomem, OBJECT(dev), &esp32_crosscore_int_ops, s, + TYPE_ESP32_CROSSCORE_INT, + s->n_irqs * sizeof(uint32_t)); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void esp32_crosscore_int_init(Object *obj) +{ + +} + +static Property esp32_crosscore_int_properties[] = { + DEFINE_PROP_INT32("n_irqs", Esp32CrosscoreInt, n_irqs, 4), + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_crosscore_int_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = esp32_crosscore_int_realize; + dc->props = esp32_crosscore_int_properties; +} + +static const TypeInfo esp32_crosscore_int_info = { + .name = TYPE_ESP32_CROSSCORE_INT, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32CrosscoreInt), + .instance_init = esp32_crosscore_int_init, + .class_init = esp32_crosscore_int_class_init +}; + +static void esp32_crosscore_int_register_types(void) +{ + type_register_static(&esp32_crosscore_int_info); +} + +type_init(esp32_crosscore_int_register_types) diff --git a/hw/misc/esp32_dport.c b/hw/misc/esp32_dport.c new file mode 100644 index 0000000000000..bb76f7374e928 --- /dev/null +++ b/hw/misc/esp32_dport.c @@ -0,0 +1,438 @@ +/* + * ESP32 "DPORT" device + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/registerfields.h" +#include "hw/boards.h" +#include "hw/misc/esp32_reg.h" +#include "hw/misc/esp32_dport.h" +#include "target/xtensa/cpu.h" + + +#define ESP32_DPORT_SIZE (DR_REG_DPORT_APB_BASE - DR_REG_DPORT_BASE) + +#define MMU_RANGE_SIZE (ESP32_CACHE_PAGES_PER_REGION * sizeof(uint32_t)) +#define MMU_RANGE_LAST (MMU_RANGE_SIZE - sizeof(uint32_t)) + +#define PRO_DROM0_MMU_FIRST (DR_REG_FLASH_MMU_TABLE_PRO - DR_REG_DPORT_BASE) +#define PRO_DROM0_MMU_LAST (PRO_DROM0_MMU_FIRST + MMU_RANGE_LAST) +#define PRO_IRAM0_MMU_FIRST (DR_REG_FLASH_MMU_TABLE_PRO - DR_REG_DPORT_BASE + MMU_RANGE_SIZE) +#define PRO_IRAM0_MMU_LAST (PRO_IRAM0_MMU_FIRST + MMU_RANGE_LAST) +#define APP_DROM0_MMU_FIRST (DR_REG_FLASH_MMU_TABLE_APP - DR_REG_DPORT_BASE) +#define APP_DROM0_MMU_LAST (APP_DROM0_MMU_FIRST + MMU_RANGE_LAST) +#define APP_IRAM0_MMU_FIRST (DR_REG_FLASH_MMU_TABLE_APP - DR_REG_DPORT_BASE + MMU_RANGE_SIZE) +#define APP_IRAM0_MMU_LAST (APP_IRAM0_MMU_FIRST + MMU_RANGE_LAST) +#define MMU_ENTRY_MASK 0x1ff + +static void esp32_cache_state_update(Esp32CacheState* cs); +static void esp32_cache_data_sync(Esp32CacheRegionState* crs); + +static inline uint32_t get_mmu_entry(Esp32CacheRegionState* crs, hwaddr base, hwaddr addr) +{ + return crs->mmu_table[(addr - base)/sizeof(uint32_t)] & MMU_ENTRY_MASK; +} + +static inline void set_mmu_entry(Esp32CacheRegionState* crs, hwaddr base, hwaddr addr, uint64_t val) +{ + uint32_t old_val = crs->mmu_table[(addr - base)/sizeof(uint32_t)]; + if (val != old_val) { + crs->mmu_table[(addr - base)/sizeof(uint32_t)] = (val & MMU_ENTRY_MASK) | ESP32_CACHE_MMU_ENTRY_CHANGED; + } +} + +static uint64_t esp32_dport_read(void *opaque, hwaddr addr, unsigned int size) +{ + Esp32DportState *s = ESP32_DPORT(opaque); + uint64_t r = 0; + switch (addr) { + case A_DPORT_APPCPU_RESET: + r = s->appcpu_reset_state; + break; + case A_DPORT_APPCPU_CLK: + r = s->appcpu_clkgate_state; + break; + case A_DPORT_APPCPU_RUNSTALL: + r = s->appcpu_stall_state; + break; + case A_DPORT_APPCPU_BOOT_ADDR: + r = s->appcpu_boot_addr; + break; + case A_DPORT_CPU_PER_CONF: + r = s->cpuperiod_sel; + break; + case A_DPORT_PRO_CACHE_CTRL: + r = s->cache_state[0].cache_ctrl_reg; + break; + case A_DPORT_PRO_CACHE_CTRL1: + r = s->cache_state[0].cache_ctrl1_reg; + break; + case A_DPORT_APP_CACHE_CTRL: + r = s->cache_state[1].cache_ctrl_reg; + break; + case A_DPORT_APP_CACHE_CTRL1: + r = s->cache_state[1].cache_ctrl1_reg; + break; + case A_DPORT_PRO_DCACHE_DBUG0: + case A_DPORT_APP_DCACHE_DBUG0: + /* in idle state */ + r = FIELD_DP32(0, DPORT_PRO_DCACHE_DBUG0, CACHE_STATE, 1); + break; + case A_DPORT_CACHE_IA_INT_EN: + r = s->cache_ill_trap_en_reg; + break; + case A_DPORT_PRO_DCACHE_DBUG3: + r = 0; + r = FIELD_DP32(r, DPORT_PRO_DCACHE_DBUG3, IA_INT_DROM0, s->cache_state[0].drom0.illegal_access_status); + r = FIELD_DP32(r, DPORT_PRO_DCACHE_DBUG3, IA_INT_IRAM0, s->cache_state[0].iram0.illegal_access_status); + break; + case A_DPORT_APP_DCACHE_DBUG3: + r = 0; + r = FIELD_DP32(r, DPORT_APP_DCACHE_DBUG3, IA_INT_DROM0, s->cache_state[1].drom0.illegal_access_status); + r = FIELD_DP32(r, DPORT_APP_DCACHE_DBUG3, IA_INT_IRAM0, s->cache_state[1].iram0.illegal_access_status); + break; + case PRO_DROM0_MMU_FIRST ... PRO_DROM0_MMU_LAST: + r = get_mmu_entry(&s->cache_state[0].drom0, PRO_DROM0_MMU_FIRST, addr); + break; + case PRO_IRAM0_MMU_FIRST ... PRO_IRAM0_MMU_LAST: + r = get_mmu_entry(&s->cache_state[0].iram0, PRO_IRAM0_MMU_FIRST, addr); + break; + case APP_DROM0_MMU_FIRST ... APP_DROM0_MMU_LAST: + r = get_mmu_entry(&s->cache_state[1].drom0, APP_DROM0_MMU_FIRST, addr); + break; + case APP_IRAM0_MMU_FIRST ... APP_IRAM0_MMU_LAST: + r = get_mmu_entry(&s->cache_state[1].iram0, APP_IRAM0_MMU_FIRST, addr); + break; + } + + return r; +} + +static void esp32_dport_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + Esp32DportState *s = ESP32_DPORT(opaque); + bool old_state; + uint32_t old_val; + switch (addr) { + case A_DPORT_APPCPU_RESET: + old_state = s->appcpu_reset_state; + s->appcpu_reset_state = value & 1; + if (old_state && !s->appcpu_reset_state) { + qemu_irq_pulse(s->appcpu_reset_req); + } + break; + case A_DPORT_APPCPU_CLK: + s->appcpu_clkgate_state = value & 1; + qemu_set_irq(s->appcpu_stall_req, s->appcpu_stall_state || !s->appcpu_clkgate_state); + break; + case A_DPORT_APPCPU_RUNSTALL: + s->appcpu_stall_state = value & 1; + qemu_set_irq(s->appcpu_stall_req, s->appcpu_stall_state || !s->appcpu_clkgate_state); + break; + case A_DPORT_APPCPU_BOOT_ADDR: + s->appcpu_boot_addr = value; + break; + case A_DPORT_CPU_PER_CONF: + s->cpuperiod_sel = value & R_DPORT_CPU_PER_CONF_CPUPERIOD_SEL_MASK; + qemu_irq_pulse(s->clk_update_req); + break; + case A_DPORT_PRO_CACHE_CTRL: + if (FIELD_EX32(value, DPORT_PRO_CACHE_CTRL, CACHE_FLUSH_ENA)) { + value |= R_DPORT_PRO_CACHE_CTRL_CACHE_FLUSH_DONE_MASK; + value &= ~R_DPORT_PRO_CACHE_CTRL_CACHE_FLUSH_ENA_MASK; + esp32_cache_data_sync(&s->cache_state[0].drom0); + esp32_cache_data_sync(&s->cache_state[0].iram0); + } + old_val = s->cache_state[0].cache_ctrl_reg; + s->cache_state[0].cache_ctrl_reg = value; + if (value != old_val) { + esp32_cache_state_update(&s->cache_state[0]); + } + break; + case A_DPORT_PRO_CACHE_CTRL1: + old_val = s->cache_state[0].cache_ctrl1_reg; + s->cache_state[0].cache_ctrl1_reg = value; + if (value != old_val) { + esp32_cache_state_update(&s->cache_state[0]); + } + break; + case A_DPORT_APP_CACHE_CTRL: + if (FIELD_EX32(value, DPORT_APP_CACHE_CTRL, CACHE_FLUSH_ENA)) { + value |= R_DPORT_APP_CACHE_CTRL_CACHE_FLUSH_DONE_MASK; + value &= ~R_DPORT_APP_CACHE_CTRL_CACHE_FLUSH_ENA_MASK; + esp32_cache_data_sync(&s->cache_state[1].drom0); + esp32_cache_data_sync(&s->cache_state[1].iram0); + } + old_val = s->cache_state[1].cache_ctrl_reg; + s->cache_state[1].cache_ctrl_reg = value; + if (value != old_val) { + esp32_cache_state_update(&s->cache_state[1]); + } + break; + case A_DPORT_APP_CACHE_CTRL1: + old_val = s->cache_state[1].cache_ctrl1_reg; + s->cache_state[1].cache_ctrl1_reg = value; + if (value != old_val) { + esp32_cache_state_update(&s->cache_state[1]); + } + break; + case A_DPORT_CACHE_IA_INT_EN: + s->cache_ill_trap_en_reg = value; + s->cache_state[0].drom0.illegal_access_trap_en = (FIELD_EX32(value, DPORT_CACHE_IA_INT_EN, IA_INT_PRO_DROM0)); + s->cache_state[0].iram0.illegal_access_trap_en = (FIELD_EX32(value, DPORT_CACHE_IA_INT_EN, IA_INT_PRO_IRAM0)); + s->cache_state[1].drom0.illegal_access_trap_en = (FIELD_EX32(value, DPORT_CACHE_IA_INT_EN, IA_INT_APP_DROM0)); + s->cache_state[1].iram0.illegal_access_trap_en = (FIELD_EX32(value, DPORT_CACHE_IA_INT_EN, IA_INT_APP_IRAM0)); + break; + case PRO_DROM0_MMU_FIRST ... PRO_DROM0_MMU_LAST: + set_mmu_entry(&s->cache_state[0].drom0, PRO_DROM0_MMU_FIRST, addr, value); + break; + case PRO_IRAM0_MMU_FIRST ... PRO_IRAM0_MMU_LAST: + set_mmu_entry(&s->cache_state[0].iram0, PRO_IRAM0_MMU_FIRST, addr, value); + break; + case APP_DROM0_MMU_FIRST ... APP_DROM0_MMU_LAST: + set_mmu_entry(&s->cache_state[1].drom0, APP_DROM0_MMU_FIRST, addr, value); + break; + case APP_IRAM0_MMU_FIRST ... APP_IRAM0_MMU_LAST: + set_mmu_entry(&s->cache_state[1].iram0, APP_IRAM0_MMU_FIRST, addr, value); + break; + } +} + +static const MemoryRegionOps esp32_dport_ops = { + .read = esp32_dport_read, + .write = esp32_dport_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_cache_data_sync(Esp32CacheRegionState* crs) +{ + if (crs->cache->dport->flash_blk == NULL) { + return; + } + + uint8_t* cache_data = (uint8_t*) memory_region_get_ram_ptr(&crs->mem); + int n = 0; + for (int i = 0; i < ESP32_CACHE_PAGES_PER_REGION; ++i) { + uint32_t* cache_page = (uint32_t*) (cache_data + i * ESP32_CACHE_PAGE_SIZE); + uint32_t mmu_entry = crs->mmu_table[i]; + if (!(mmu_entry & ESP32_CACHE_MMU_ENTRY_CHANGED)) { + continue; + } + mmu_entry &= MMU_ENTRY_MASK; + if (mmu_entry & ESP32_CACHE_MMU_INVALID_VAL) { + uint32_t fill_val = crs->type == ESP32_DCACHE ? 0xbaadbaad : 0x00000000; + for (int word = 0; word < ESP32_CACHE_PAGE_SIZE / sizeof(uint32_t); ++word) { + cache_page[word] = fill_val; + } + } else { + uint32_t phys_addr = mmu_entry * ESP32_CACHE_PAGE_SIZE; + blk_pread(crs->cache->dport->flash_blk, phys_addr, cache_page, ESP32_CACHE_PAGE_SIZE); + } + crs->mmu_table[i] &= ~ESP32_CACHE_MMU_ENTRY_CHANGED; + n++; + } + memory_region_flush_rom_device(&crs->mem, 0, ESP32_CACHE_REGION_SIZE); +} + +static void esp32_cache_state_update(Esp32CacheState* cs) +{ + bool cache_enabled = FIELD_EX32(cs->cache_ctrl_reg, DPORT_PRO_CACHE_CTRL, CACHE_ENA) != 0; + + bool drom0_enabled = cache_enabled && + FIELD_EX32(cs->cache_ctrl1_reg, DPORT_PRO_CACHE_CTRL1, MASK_DROM0) == 0; + if (!cs->drom0.mem.enabled && drom0_enabled) { + esp32_cache_data_sync(&cs->drom0); + } + memory_region_set_enabled(&cs->drom0.mem, drom0_enabled); + + bool iram0_enabled = cache_enabled && + FIELD_EX32(cs->cache_ctrl1_reg, DPORT_PRO_CACHE_CTRL1, MASK_IRAM0) == 0; + if (!cs->iram0.mem.enabled && iram0_enabled) { + esp32_cache_data_sync(&cs->iram0); + } + memory_region_set_enabled(&cs->iram0.mem, iram0_enabled); +} + +static void esp32_cache_region_reset(Esp32CacheRegionState *crs) +{ + for (int i = 0; i < ESP32_CACHE_PAGES_PER_REGION; ++i) { + crs->mmu_table[i] = ESP32_CACHE_MMU_ENTRY_CHANGED; + } + crs->illegal_access_trap_en = false; +} + +static void esp32_cache_reset(Esp32CacheState *cs) +{ + esp32_cache_region_reset(&cs->drom0); + esp32_cache_region_reset(&cs->iram0); +} + +static uint64_t esp32_cache_ill_read(void *opaque, hwaddr addr, unsigned int size) +{ + Esp32CacheRegionState *crs = (Esp32CacheRegionState*) opaque; + uint32_t ill_data[] = { crs->illegal_access_retval, crs->illegal_access_retval }; + uint32_t result; + memcpy(&result, ((uint8_t*) ill_data) + (addr % 4), size); + if (crs->illegal_access_trap_en) { + crs->illegal_access_status = true; + qemu_irq cache_ill_irq = qdev_get_gpio_in(DEVICE(&crs->cache->dport->intmatrix), ETS_CACHE_IA_INTR_SOURCE); + qemu_irq_raise(cache_ill_irq); + } + return result; +} + +void esp32_dport_clear_ill_trap_state(Esp32DportState* s) +{ + s->cache_state[0].drom0.illegal_access_status = false; + s->cache_state[0].drom0.illegal_access_status = false; + s->cache_state[1].iram0.illegal_access_status = false; + s->cache_state[1].iram0.illegal_access_status = false; + qemu_irq cache_ill_irq = qdev_get_gpio_in(DEVICE(&s->intmatrix), ETS_CACHE_IA_INTR_SOURCE); + qemu_irq_lower(cache_ill_irq); +} + +static const MemoryRegionOps esp32_cache_ops = { + .write = NULL, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + + +static const MemoryRegionOps esp32_cache_ill_trap_ops = { + .read = esp32_cache_ill_read, +}; + +static void esp32_dport_reset(DeviceState *dev) +{ + Esp32DportState *s = ESP32_DPORT(dev); + + s->appcpu_boot_addr = 0; + s->appcpu_clkgate_state = false; + s->appcpu_reset_state = true; + s->appcpu_stall_state = false; + s->cache_ill_trap_en_reg = 0; + esp32_cache_reset(&s->cache_state[0]); + esp32_cache_reset(&s->cache_state[1]); + device_reset(DEVICE(&s->intmatrix)); + qemu_irq_lower(s->appcpu_stall_req); +} + +static void esp32_dport_realize(DeviceState *dev, Error **errp) +{ + Esp32DportState *s = ESP32_DPORT(dev); + MachineState *ms = MACHINE(qdev_get_machine()); + + s->cpu_count = ms->smp.cpus; + + for (int i = 0; i < s->cpu_count; ++i) { + char name[16]; + snprintf(name, sizeof(name), "cpu%d", i); + object_property_set_link(OBJECT(&s->intmatrix), OBJECT(qemu_get_cpu(i)), name, &error_abort); + } + object_property_set_bool(OBJECT(&s->intmatrix), true, "realized", &error_abort); + + int n_crosscore_irqs = ESP32_DPORT_CROSSCORE_INT_COUNT; + object_property_set_int(OBJECT(&s->crosscore_int), n_crosscore_irqs, "n_irqs", &error_abort); + object_property_set_bool(OBJECT(&s->crosscore_int), true, "realized", &error_abort); + memory_region_add_subregion_overlap(&s->iomem, ESP32_DPORT_CROSSCORE_INT_BASE, &s->crosscore_int.iomem, -1); + + for (int index = 0; index < n_crosscore_irqs; ++index) { + qemu_irq target = qdev_get_gpio_in(DEVICE(&s->intmatrix), ETS_FROM_CPU_INTR0_SOURCE + index); + assert(target); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->crosscore_int), index, target); + } +} + +static void esp32_cache_init_region(Esp32CacheState *cs, + Esp32CacheRegionState *crs, + Esp32CacheRegionType type, + const char* name, hwaddr base, + uint32_t illegal_access_retval) +{ + char desc[16]; + crs->cache = cs; + crs->type = type; + crs->base = base; + crs->illegal_access_retval = illegal_access_retval; + snprintf(desc, sizeof(desc), "cpu%d-%s", cs->core_id, name); + memory_region_init_rom_device(&crs->mem, OBJECT(cs->dport), + &esp32_cache_ops, crs, + desc, ESP32_CACHE_REGION_SIZE, &error_abort); + + snprintf(desc, sizeof(desc), "cpu%d-%s-ill", cs->core_id, name); + memory_region_init_io(&crs->illegal_access_trap_mem, OBJECT(cs->dport), + &esp32_cache_ill_trap_ops, crs, + desc, ESP32_CACHE_REGION_SIZE); +} + +static void esp32_dport_init(Object *obj) +{ + Esp32DportState *s = ESP32_DPORT(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &esp32_dport_ops, s, + TYPE_ESP32_DPORT, ESP32_DPORT_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + + object_initialize_child(obj, "intmatrix", &s->intmatrix, sizeof(s->intmatrix), TYPE_ESP32_INTMATRIX, &error_abort, NULL); + memory_region_add_subregion_overlap(&s->iomem, ESP32_DPORT_PRO_INTMATRIX_BASE, &s->intmatrix.iomem, -1); + + object_initialize_child(obj, "crosscore_int", &s->crosscore_int, sizeof(s->crosscore_int), TYPE_ESP32_CROSSCORE_INT, + &error_abort, NULL); + /* memory_region_add_subregion_overlap is called from esp32_dport_realize, since crosscore_int doesn't know its iomem size yet */ + + for (int i = 0; i < ESP32_CPU_COUNT; ++i) { + Esp32CacheState* cs = &s->cache_state[i]; + cs->core_id = i; + cs->dport = s; + esp32_cache_init_region(cs, &cs->drom0, ESP32_DCACHE, "drom0", + 0x3F400000, 0xbaadbaad); + esp32_cache_init_region(cs, &cs->iram0, ESP32_ICACHE, "iram0", + 0x40000000, 0x00000000); + } + + qdev_init_gpio_out_named(DEVICE(sbd), &s->appcpu_stall_req, ESP32_DPORT_APPCPU_STALL_GPIO, 1); + qdev_init_gpio_out_named(DEVICE(sbd), &s->appcpu_reset_req, ESP32_DPORT_APPCPU_RESET_GPIO, 1); + qdev_init_gpio_out_named(DEVICE(sbd), &s->clk_update_req, ESP32_DPORT_CLK_UPDATE_GPIO, 1); +} + +static Property esp32_dport_properties[] = { + DEFINE_PROP_DRIVE("flash", Esp32DportState, flash_blk), + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_dport_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_dport_reset; + dc->realize = esp32_dport_realize; + dc->props = esp32_dport_properties; +} + +static const TypeInfo esp32_dport_info = { + .name = TYPE_ESP32_DPORT, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32DportState), + .instance_init = esp32_dport_init, + .class_init = esp32_dport_class_init +}; + +static void esp32_dport_register_types(void) +{ + type_register_static(&esp32_dport_info); +} + +type_init(esp32_dport_register_types) diff --git a/hw/misc/esp32_intmatrix.c b/hw/misc/esp32_intmatrix.c new file mode 100644 index 0000000000000..dafb995dceb2a --- /dev/null +++ b/hw/misc/esp32_intmatrix.c @@ -0,0 +1,144 @@ +/* + * ESP32 Interrupt Matrix + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/misc/esp32_reg.h" +#include "hw/misc/esp32_dport.h" + +#define INTMATRIX_UNINT_VALUE 6 + +#define IRQ_MAP(cpu, input) s->irq_map[cpu][input] + +static void esp32_intmatrix_irq_handler(void *opaque, int n, int level) +{ + Esp32IntMatrixState *s = ESP32_INTMATRIX(opaque); + for (int i = 0; i < ESP32_CPU_COUNT; ++i) { + if (s->outputs[i] == NULL) { + continue; + } + int out_index = IRQ_MAP(i, n); + for (int int_index = 0; int_index < s->cpu[i]->env.config->nextint; ++int_index) { + if (s->cpu[i]->env.config->extint[int_index] == out_index) { + qemu_set_irq(s->outputs[i][int_index], level); + break; + } + } + } +} + +static inline uint8_t* get_map_entry(Esp32IntMatrixState* s, hwaddr addr) +{ + int source_index = addr / sizeof(uint32_t); + if (source_index > ESP32_INT_MATRIX_INPUTS * ESP32_CPU_COUNT) { + error_report("%s: source_index %d out of range", __func__, source_index); + return NULL; + } + int cpu_index = source_index / ESP32_INT_MATRIX_INPUTS; + source_index = source_index % ESP32_INT_MATRIX_INPUTS; + return &IRQ_MAP(cpu_index, source_index); +} + +static uint64_t esp32_intmatrix_read(void* opaque, hwaddr addr, unsigned int size) +{ + Esp32IntMatrixState *s = ESP32_INTMATRIX(opaque); + uint8_t* map_entry = get_map_entry(s, addr); + return (map_entry != NULL) ? *map_entry : 0; +} + +static void esp32_intmatrix_write(void* opaque, hwaddr addr, uint64_t value, unsigned int size) +{ + Esp32IntMatrixState *s = ESP32_INTMATRIX(opaque); + uint8_t* map_entry = get_map_entry(s, addr); + if (map_entry != NULL) { + *map_entry = value & 0x1f; + } +} + +static const MemoryRegionOps esp_intmatrix_ops = { + .read = esp32_intmatrix_read, + .write = esp32_intmatrix_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_intmatrix_reset(DeviceState *dev) +{ + Esp32IntMatrixState *s = ESP32_INTMATRIX(dev); + memset(s->irq_map, INTMATRIX_UNINT_VALUE, sizeof(s->irq_map)); + for (int i = 0; i < ESP32_CPU_COUNT; ++i) { + if (s->outputs[i] == NULL) { + continue; + } + for (int int_index = 0; int_index < s->cpu[i]->env.config->nextint; ++int_index) { + qemu_irq_lower(s->outputs[i][int_index]); + } + } + +} + +static void esp32_intmatrix_realize(DeviceState *dev, Error **errp) +{ + Esp32IntMatrixState *s = ESP32_INTMATRIX(dev); + + for (int i = 0; i < ESP32_CPU_COUNT; ++i) { + if (s->cpu[i]) { + s->outputs[i] = xtensa_get_extints(&s->cpu[i]->env); + } + } + esp32_intmatrix_reset(dev); +} + +static void esp32_intmatrix_init(Object *obj) +{ + Esp32IntMatrixState *s = ESP32_INTMATRIX(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &esp_intmatrix_ops, s, + TYPE_ESP32_INTMATRIX, ESP32_INT_MATRIX_INPUTS * ESP32_CPU_COUNT * sizeof(uint32_t)); + sysbus_init_mmio(sbd, &s->iomem); + + qdev_init_gpio_in(DEVICE(s), esp32_intmatrix_irq_handler, ESP32_INT_MATRIX_INPUTS); +} + +static Property esp32_intmatrix_properties[] = { + DEFINE_PROP_LINK("cpu0", Esp32IntMatrixState, cpu[0], TYPE_XTENSA_CPU, XtensaCPU *), + DEFINE_PROP_LINK("cpu1", Esp32IntMatrixState, cpu[1], TYPE_XTENSA_CPU, XtensaCPU *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_intmatrix_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_intmatrix_reset; + dc->realize = esp32_intmatrix_realize; + dc->props = esp32_intmatrix_properties; +} + +static const TypeInfo esp32_intmatrix_info = { + .name = TYPE_ESP32_INTMATRIX, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32IntMatrixState), + .instance_init = esp32_intmatrix_init, + .class_init = esp32_intmatrix_class_init +}; + +static void esp32_intmatrix_register_types(void) +{ + type_register_static(&esp32_intmatrix_info); +} + +type_init(esp32_intmatrix_register_types) diff --git a/include/hw/misc/esp32_crosscore_int.h b/include/hw/misc/esp32_crosscore_int.h new file mode 100644 index 0000000000000..35c8739dda71e --- /dev/null +++ b/include/hw/misc/esp32_crosscore_int.h @@ -0,0 +1,17 @@ +#pragma once + +#include "hw/hw.h" +#include "hw/registerfields.h" +#include "hw/sysbus.h" +#include "sysemu/block-backend.h" + + +#define TYPE_ESP32_CROSSCORE_INT "misc.esp32.crosscoreint" +#define ESP32_CROSSCORE_INT(obj) OBJECT_CHECK(Esp32CrosscoreInt, (obj), TYPE_ESP32_CROSSCORE_INT) + +typedef struct Esp32CrosscoreInt { + SysBusDevice parent_obj; + MemoryRegion iomem; + int n_irqs; + qemu_irq *irqs; +} Esp32CrosscoreInt; diff --git a/include/hw/misc/esp32_dport.h b/include/hw/misc/esp32_dport.h new file mode 100644 index 0000000000000..15ee26458463f --- /dev/null +++ b/include/hw/misc/esp32_dport.h @@ -0,0 +1,183 @@ +#pragma once + +#include "hw/hw.h" +#include "hw/registerfields.h" +#include "hw/sysbus.h" +#include "hw/misc/esp32_reg.h" +#include "hw/misc/esp32_crosscore_int.h" +#include "sysemu/block-backend.h" +#include "target/xtensa/cpu.h" +#include "target/xtensa/cpu-qom.h" + +typedef struct Esp32DportState Esp32DportState; +typedef struct Esp32CacheState Esp32CacheState; + +#define TYPE_ESP32_INTMATRIX "misc.esp32.intmatrix" +#define ESP32_INTMATRIX(obj) OBJECT_CHECK(Esp32IntMatrixState, (obj), TYPE_ESP32_INTMATRIX) + +typedef struct Esp32IntMatrixState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq *outputs[ESP32_CPU_COUNT]; + uint8_t irq_map[ESP32_CPU_COUNT][ESP32_INT_MATRIX_INPUTS]; + + /* properties */ + XtensaCPU *cpu[ESP32_CPU_COUNT]; +} Esp32IntMatrixState; + + + +#define TYPE_ESP32_DPORT "misc.esp32.dport" +#define ESP32_DPORT(obj) OBJECT_CHECK(Esp32DportState, (obj), TYPE_ESP32_DPORT) + +#define ESP32_CACHE_PAGE_SIZE 0x10000 +#define ESP32_CACHE_PAGES_PER_REGION 64 +#define ESP32_CACHE_REGION_SIZE (ESP32_CACHE_PAGE_SIZE * ESP32_CACHE_PAGES_PER_REGION) +#define ESP32_CACHE_MMU_INVALID_VAL 0x100 +#define ESP32_CACHE_MMU_ENTRY_CHANGED 0x200 /* not a hardware flag; used here to check if the page data needs to be updated */ +#define ESP32_CACHE_MAX_PHYS_PAGES 0x100 + +typedef enum Esp32CacheRegionType { + ESP32_DCACHE, + ESP32_ICACHE, +} Esp32CacheRegionType; + +typedef struct Esp32CacheRegionState { + Esp32CacheState* cache; + MemoryRegion mem; + MemoryRegion illegal_access_trap_mem; + Esp32CacheRegionType type; + hwaddr base; + uint32_t illegal_access_retval; + bool illegal_access_trap_en; + bool illegal_access_status; + uint16_t mmu_table[ESP32_CACHE_PAGES_PER_REGION]; +} Esp32CacheRegionState; + +typedef struct Esp32CacheState { + Esp32DportState* dport; + int core_id; + + uint32_t cache_ctrl_reg; + uint32_t cache_ctrl1_reg; + /* Using only the first 4MB range. + * TODO: add memory regions for other ports: iram1, irom0 + */ + Esp32CacheRegionState iram0; + Esp32CacheRegionState drom0; +} Esp32CacheState; + +typedef struct Esp32DportState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + int cpu_count; + Esp32IntMatrixState intmatrix; + Esp32CrosscoreInt crosscore_int; + Esp32CacheState cache_state[ESP32_CPU_COUNT]; + BlockBackend *flash_blk; + qemu_irq appcpu_stall_req; + qemu_irq appcpu_reset_req; + qemu_irq clk_update_req; + + bool appcpu_reset_state; + bool appcpu_stall_state; + bool appcpu_clkgate_state; + uint32_t appcpu_boot_addr; + uint32_t cpuperiod_sel; + uint32_t cache_ill_trap_en_reg; +} Esp32DportState; + +void esp32_dport_clear_ill_trap_state(Esp32DportState* s); + +#define ESP32_DPORT_APPCPU_STALL_GPIO "appcpu-stall" +#define ESP32_DPORT_APPCPU_RESET_GPIO "appcpu-reset" +#define ESP32_DPORT_CLK_UPDATE_GPIO "clk-update" + + +REG32(DPORT_APPCPU_RESET, 0x2c) +REG32(DPORT_APPCPU_CLK, 0x30) +REG32(DPORT_APPCPU_RUNSTALL, 0x34) +REG32(DPORT_APPCPU_BOOT_ADDR, 0x38) + +REG32(DPORT_CPU_PER_CONF, 0x3c) + FIELD(DPORT_CPU_PER_CONF, CPUPERIOD_SEL, 0, 2) + +REG32(DPORT_PRO_CACHE_CTRL, 0x40) + FIELD(DPORT_PRO_CACHE_CTRL, CACHE_FLUSH_DONE, 5, 1) + FIELD(DPORT_PRO_CACHE_CTRL, CACHE_FLUSH_ENA, 4, 1) + FIELD(DPORT_PRO_CACHE_CTRL, CACHE_ENA, 3, 1) + +REG32(DPORT_PRO_CACHE_CTRL1, 0x44) + FIELD(DPORT_PRO_CACHE_CTRL1, MMU_IA_CLR, 13, 1) + FIELD(DPORT_PRO_CACHE_CTRL1, MASK_OPSDRAM, 5, 1) + FIELD(DPORT_PRO_CACHE_CTRL1, MASK_DROM0, 4, 1) + FIELD(DPORT_PRO_CACHE_CTRL1, MASK_DRAM1, 3, 1) + FIELD(DPORT_PRO_CACHE_CTRL1, MASK_IROM0, 2, 1) + FIELD(DPORT_PRO_CACHE_CTRL1, MASK_IRAM1, 1, 1) + FIELD(DPORT_PRO_CACHE_CTRL1, MASK_IRAM0, 0, 1) + +REG32(DPORT_APP_CACHE_CTRL, 0x58) + FIELD(DPORT_APP_CACHE_CTRL, CACHE_FLUSH_DONE, 5, 1) + FIELD(DPORT_APP_CACHE_CTRL, CACHE_FLUSH_ENA, 4, 1) + FIELD(DPORT_APP_CACHE_CTRL, CACHE_ENA, 3, 1) + +REG32(DPORT_APP_CACHE_CTRL1, 0x5C) + FIELD(DPORT_APP_CACHE_CTRL1, MMU_IA_CLR, 13, 1) + FIELD(DPORT_APP_CACHE_CTRL1, MASK_OPSDRAM, 5, 1) + FIELD(DPORT_APP_CACHE_CTRL1, MASK_DROM0, 4, 1) + FIELD(DPORT_APP_CACHE_CTRL1, MASK_DRAM1, 3, 1) + FIELD(DPORT_APP_CACHE_CTRL1, MASK_IROM0, 2, 1) + FIELD(DPORT_APP_CACHE_CTRL1, MASK_IRAM1, 1, 1) + FIELD(DPORT_APP_CACHE_CTRL1, MASK_IRAM0, 0, 1) + +REG32(DPORT_CPU_INTR_FROM_CPU_0, 0xdc) +REG32(DPORT_CPU_INTR_FROM_CPU_1, 0xe0) +REG32(DPORT_CPU_INTR_FROM_CPU_2, 0xe4) +REG32(DPORT_CPU_INTR_FROM_CPU_3, 0xe8) + +REG32(DPORT_PRO_MAC_INTR_MAP, 0x104) +REG32(DPORT_APP_MAC_INTR_MAP, 0x218) + +REG32(DPORT_PRO_DCACHE_DBUG0, 0x3f0) + FIELD(DPORT_PRO_DCACHE_DBUG0, CACHE_STATE, 7, 12) + +REG32(DPORT_PRO_DCACHE_DBUG3, 0x3FC) + FIELD(DPORT_PRO_DCACHE_DBUG3, IA_INT_OPPOSITE, 9, 1) + FIELD(DPORT_PRO_DCACHE_DBUG3, IA_INT_DRAM1, 10, 1) + FIELD(DPORT_PRO_DCACHE_DBUG3, IA_INT_IROM0, 11, 1) + FIELD(DPORT_PRO_DCACHE_DBUG3, IA_INT_IRAM1, 12, 1) + FIELD(DPORT_PRO_DCACHE_DBUG3, IA_INT_IRAM0, 13, 1) + FIELD(DPORT_PRO_DCACHE_DBUG3, IA_INT_DROM0, 14, 1) + +REG32(DPORT_APP_DCACHE_DBUG0, 0x418) + FIELD(DPORT_APP_DCACHE_DBUG0, CACHE_STATE, 7, 12) + +REG32(DPORT_APP_DCACHE_DBUG3, 0x424) + FIELD(DPORT_APP_DCACHE_DBUG3, IA_INT_OPPOSITE, 9, 1) + FIELD(DPORT_APP_DCACHE_DBUG3, IA_INT_DRAM1, 10, 1) + FIELD(DPORT_APP_DCACHE_DBUG3, IA_INT_IROM0, 11, 1) + FIELD(DPORT_APP_DCACHE_DBUG3, IA_INT_IRAM1, 12, 1) + FIELD(DPORT_APP_DCACHE_DBUG3, IA_INT_IRAM0, 13, 1) + FIELD(DPORT_APP_DCACHE_DBUG3, IA_INT_DROM0, 14, 1) + +REG32(DPORT_CACHE_IA_INT_EN, 0x5A0) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_PRO_OPPOSITE, 19, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_PRO_DRAM1, 18, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_PRO_IROM0, 17, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_PRO_IRAM1, 16, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_PRO_IRAM0, 15, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_PRO_DROM0, 14, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_APP_OPPOSITE, 5, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_APP_DRAM1, 4, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_APP_IROM0, 3, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_APP_IRAM1, 2, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_APP_IRAM0, 1, 1) + FIELD(DPORT_CACHE_IA_INT_EN, IA_INT_APP_DROM0, 0, 1) + + +#define ESP32_DPORT_PRO_INTMATRIX_BASE A_DPORT_PRO_MAC_INTR_MAP +#define ESP32_DPORT_APP_INTMATRIX_BASE A_DPORT_APP_MAC_INTR_MAP +#define ESP32_DPORT_CROSSCORE_INT_BASE A_DPORT_CPU_INTR_FROM_CPU_0 + From aefdadd09d0f8d887fbaa2718e503d6e55440cb8 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:38:01 +0200 Subject: [PATCH 10/16] hw/misc: ESP32 RTC controller --- hw/misc/Makefile.objs | 1 + hw/misc/esp32_rtc_cntl.c | 244 +++++++++++++++++++++++++++++++ include/hw/misc/esp32_rtc_cntl.h | 119 +++++++++++++++ 3 files changed, 364 insertions(+) create mode 100644 hw/misc/esp32_rtc_cntl.c create mode 100644 include/hw/misc/esp32_rtc_cntl.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 311674185991e..70d44adede5c1 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -86,3 +86,4 @@ common-obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o obj-$(CONFIG_ESP32) += esp32_dport.o obj-$(CONFIG_ESP32) += esp32_intmatrix.o obj-$(CONFIG_ESP32) += esp32_crosscore_int.o +obj-$(CONFIG_ESP32) += esp32_rtc_cntl.o diff --git a/hw/misc/esp32_rtc_cntl.c b/hw/misc/esp32_rtc_cntl.c new file mode 100644 index 0000000000000..fac295afc573f --- /dev/null +++ b/hw/misc/esp32_rtc_cntl.c @@ -0,0 +1,244 @@ +/* + * ESP32 RTC_CNTL (RTC block controller) device + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/timer.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/misc/esp32_reg.h" +#include "hw/misc/esp32_rtc_cntl.h" + +static void esp32_rtc_update_cpu_stall(Esp32RtcCntlState* s); +static void esp32_rtc_update_clk(Esp32RtcCntlState* s); + +static uint64_t esp32_rtc_cntl_read(void *opaque, hwaddr addr, unsigned int size) +{ + Esp32RtcCntlState *s = ESP32_RTC_CNTL(opaque); + uint64_t r = 0; + switch (addr) { + case A_RTC_CNTL_OPTIONS0: + r = s->options0_reg; + break; + case A_RTC_CNTL_TIME_UPDATE: + r = R_RTC_CNTL_TIME_UPDATE_VALID_MASK; + break; + case A_RTC_CNTL_TIME0: + r = s->time_reg & UINT32_MAX; + break; + case A_RTC_CNTL_TIME1: + r = s->time_reg >> 32; + break; + + case A_RTC_CNTL_RESET_STATE: + r = FIELD_DP32(r, RTC_CNTL_RESET_STATE, RESET_CAUSE_PROCPU, s->reset_cause[0]); + r = FIELD_DP32(r, RTC_CNTL_RESET_STATE, RESET_CAUSE_APPCPU, s->reset_cause[1]); + r = FIELD_DP32(r, RTC_CNTL_RESET_STATE, PROCPU_STAT_VECTOR_SEL, s->stat_vector_sel[0]); + r = FIELD_DP32(r, RTC_CNTL_RESET_STATE, APPCPU_STAT_VECTOR_SEL, s->stat_vector_sel[1]); + break; + + case A_RTC_CNTL_STORE0: + case A_RTC_CNTL_STORE1: + case A_RTC_CNTL_STORE2: + case A_RTC_CNTL_STORE3: + r = s->scratch_reg[(addr - A_RTC_CNTL_STORE0) / 4]; + break; + + case A_RTC_CNTL_CLK_CONF: + r = FIELD_DP32(r, RTC_CNTL_CLK_CONF, SOC_CLK_SEL, s->soc_clk); + r = FIELD_DP32(r, RTC_CNTL_CLK_CONF, FAST_CLK_RTC_SEL, s->rtc_fastclk); + r = FIELD_DP32(r, RTC_CNTL_CLK_CONF, ANA_CLK_RTC_SEL, s->rtc_slowclk); + break; + + case A_RTC_CNTL_SW_CPU_STALL: + r = s->sw_cpu_stall_reg; + break; + + case A_RTC_CNTL_STORE4: + case A_RTC_CNTL_STORE5: + case A_RTC_CNTL_STORE6: + case A_RTC_CNTL_STORE7: + r = s->scratch_reg[(addr - A_RTC_CNTL_STORE4) / 4 + 4]; + break; + } + return r; +} + +static void esp32_rtc_cntl_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + Esp32RtcCntlState *s = ESP32_RTC_CNTL(opaque); + switch (addr) { + case A_RTC_CNTL_OPTIONS0: + if (value & R_RTC_CNTL_OPTIONS0_SW_SYS_RESET_MASK) { + s->reset_cause[0] = ESP32_SW_SYS_RESET; + s->reset_cause[1] = ESP32_SW_SYS_RESET; + qemu_irq_pulse(s->dig_reset_req); + value &= ~(R_RTC_CNTL_OPTIONS0_SW_SYS_RESET_MASK); + } + if (value & R_RTC_CNTL_OPTIONS0_SW_APPCPU_RESET_MASK) { + s->reset_cause[1] = ESP32_SW_CPU_RESET; + qemu_irq_pulse(s->cpu_reset_req[1]); + value &= ~(R_RTC_CNTL_OPTIONS0_SW_APPCPU_RESET_MASK); + } + if (value & R_RTC_CNTL_OPTIONS0_SW_PROCPU_RESET_MASK) { + s->reset_cause[0] = ESP32_SW_CPU_RESET; + qemu_irq_pulse(s->cpu_reset_req[0]); + value &= ~(R_RTC_CNTL_OPTIONS0_SW_PROCPU_RESET_MASK); + } + s->options0_reg = value; + esp32_rtc_update_cpu_stall(s); + break; + + case A_RTC_CNTL_TIME_UPDATE: + if (value & R_RTC_CNTL_TIME_UPDATE_UPDATE_MASK) { + s->time_reg = muldiv64( + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->time_base_ns, + s->rtc_slowclk_freq, NANOSECONDS_PER_SECOND); + } + break; + + case A_RTC_CNTL_RESET_STATE: + s->stat_vector_sel[0] = FIELD_EX32(value, RTC_CNTL_RESET_STATE, + PROCPU_STAT_VECTOR_SEL); + s->stat_vector_sel[1] = FIELD_EX32(value, RTC_CNTL_RESET_STATE, + APPCPU_STAT_VECTOR_SEL); + break; + + case A_RTC_CNTL_STORE0: + case A_RTC_CNTL_STORE1: + case A_RTC_CNTL_STORE2: + case A_RTC_CNTL_STORE3: + s->scratch_reg[(addr - A_RTC_CNTL_STORE0) / 4] = value; + break; + + case A_RTC_CNTL_CLK_CONF: + s->soc_clk = FIELD_EX32(value, RTC_CNTL_CLK_CONF, SOC_CLK_SEL); + s->rtc_fastclk = FIELD_EX32(value, RTC_CNTL_CLK_CONF, FAST_CLK_RTC_SEL); + s->rtc_slowclk = FIELD_EX32(value, RTC_CNTL_CLK_CONF, ANA_CLK_RTC_SEL); + esp32_rtc_update_clk(s); + break; + + case A_RTC_CNTL_SW_CPU_STALL: + s->sw_cpu_stall_reg = value; + esp32_rtc_update_cpu_stall(s); + break; + + case A_RTC_CNTL_STORE4: + case A_RTC_CNTL_STORE5: + case A_RTC_CNTL_STORE6: + case A_RTC_CNTL_STORE7: + s->scratch_reg[(addr - A_RTC_CNTL_STORE4) / 4 + 4] = value; + break; + } +} + +static void esp32_rtc_update_cpu_stall(Esp32RtcCntlState* s) +{ + uint32_t procpu_stall = (FIELD_EX32(s->sw_cpu_stall_reg, RTC_CNTL_SW_CPU_STALL, PROCPU_C1) << 2) | + (FIELD_EX32(s->options0_reg, RTC_CNTL_OPTIONS0, SW_STALL_PROCPU_C0)); + + uint32_t appcpu_stall = (FIELD_EX32(s->sw_cpu_stall_reg, RTC_CNTL_SW_CPU_STALL, APPCPU_C1) << 2) | + (FIELD_EX32(s->options0_reg, RTC_CNTL_OPTIONS0, SW_STALL_APPCPU_C0)); + + const uint32_t stall_magic_val = 0x86; + + s->cpu_stall_state[0] = procpu_stall == stall_magic_val; + s->cpu_stall_state[1] = appcpu_stall == stall_magic_val; + + qemu_set_irq(s->cpu_stall_req[0], s->cpu_stall_state[0]); + qemu_set_irq(s->cpu_stall_req[1], s->cpu_stall_state[1]); +} + +static void esp32_rtc_update_clk(Esp32RtcCntlState* s) +{ + const uint32_t slowclk_freq[] = {150000, 32768, 8000000/256}; + const uint32_t fastclk_freq[] = {s->xtal_apb_freq / 4, 8000000}; + s->rtc_slowclk_freq = slowclk_freq[s->rtc_slowclk]; + s->rtc_fastclk_freq = fastclk_freq[s->rtc_fastclk]; + qemu_irq_pulse(s->clk_update); +} + +static const MemoryRegionOps esp32_rtc_cntl_ops = { + .read = esp32_rtc_cntl_read, + .write = esp32_rtc_cntl_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_rtc_cntl_reset(DeviceState *dev) +{ + Esp32RtcCntlState *s = ESP32_RTC_CNTL(dev); + + s->time_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); +} + +static void esp32_rtc_cntl_realize(DeviceState *dev, Error **errp) +{ +} + +static void esp32_rtc_cntl_init(Object *obj) +{ + Esp32RtcCntlState *s = ESP32_RTC_CNTL(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &esp32_rtc_cntl_ops, s, + TYPE_ESP32_RTC_CNTL, ESP32_RTC_CNTL_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + qdev_init_gpio_out_named(DEVICE(sbd), &s->dig_reset_req, ESP32_RTC_DIG_RESET_GPIO, 1); + qdev_init_gpio_out_named(DEVICE(sbd), &s->cpu_reset_req[0], ESP32_RTC_CPU_RESET_GPIO, ESP32_CPU_COUNT); + qdev_init_gpio_out_named(DEVICE(sbd), &s->cpu_stall_req[0], ESP32_RTC_CPU_STALL_GPIO, ESP32_CPU_COUNT); + qdev_init_gpio_out_named(DEVICE(sbd), &s->clk_update, ESP32_RTC_CLK_UPDATE_GPIO, 1); + + for (int i = 0; i < ESP32_CPU_COUNT; ++i) { + s->reset_cause[i] = ESP32_POWERON_RESET; + s->stat_vector_sel[i] = true; + } + + s->rtc_slowclk = ESP32_SLOW_CLK_RC; + s->rtc_fastclk = ESP32_FAST_CLK_8M; + s->soc_clk = ESP32_SOC_CLK_XTAL; + s->xtal_apb_freq = 40000000; + s->pll_apb_freq = 80000000; + esp32_rtc_update_clk(s); +} + +static Property esp32_rtc_cntl_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_rtc_cntl_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_rtc_cntl_reset; + dc->realize = esp32_rtc_cntl_realize; + dc->props = esp32_rtc_cntl_properties; +} + +static const TypeInfo esp32_rtc_cntl_info = { + .name = TYPE_ESP32_RTC_CNTL, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32RtcCntlState), + .instance_init = esp32_rtc_cntl_init, + .class_init = esp32_rtc_cntl_class_init +}; + +static void esp32_rtc_cntl_register_types(void) +{ + type_register_static(&esp32_rtc_cntl_info); +} + +type_init(esp32_rtc_cntl_register_types) diff --git a/include/hw/misc/esp32_rtc_cntl.h b/include/hw/misc/esp32_rtc_cntl.h new file mode 100644 index 0000000000000..9e21b0f8d90bf --- /dev/null +++ b/include/hw/misc/esp32_rtc_cntl.h @@ -0,0 +1,119 @@ +#pragma once + +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "target/xtensa/cpu.h" +#include "target/xtensa/cpu-qom.h" +#include "hw/misc/esp32_reg.h" +#define TYPE_ESP32_RTC_CNTL "misc.esp32.rtc_cntl" +#define ESP32_RTC_CNTL(obj) OBJECT_CHECK(Esp32RtcCntlState, (obj), TYPE_ESP32_RTC_CNTL) + +#define ESP32_RTC_DIG_RESET_GPIO "dig-reset" +#define ESP32_RTC_CPU_RESET_GPIO "cpu-reset" +#define ESP32_RTC_CPU_STALL_GPIO "cpu-stall" +#define ESP32_RTC_CLK_UPDATE_GPIO "clk-update" + +typedef enum Esp32ResetCause { + ESP32_POWERON_RESET = 1, + ESP32_SW_SYS_RESET = 3, + ESP32_OWDT_RESET = 4, + ESP32_DEEPSLEEP_RESET = 5, + ESP32_SDIO_RESET = 6, + ESP32_TG0WDT_SYS_RESET = 7, + ESP32_TG1WDT_SYS_RESET = 8, + ESP32_RTCWDT_SYS_RESET = 9, + ESP32_TGWDT_CPU_RESET = 11, + ESP32_SW_CPU_RESET = 12, + ESP32_RTCWDT_CPU_RESET = 13, + ESP32_EXT_CPU_RESET = 14, + ESP32_RTCWDT_BROWN_OUT_RESET = 15, + ESP32_RTCWDT_RTC_RESET = 16 +} Esp32ResetCause; + +typedef enum Esp32SocClkSel { + ESP32_SOC_CLK_XTAL = 0, + ESP32_SOC_CLK_PLL = 1, + ESP32_SOC_CLK_8M = 2, + ESP32_SOC_CLK_APLL = 3 +} Esp32SocClkSel; + +typedef enum Esp32FastClkSel { + ESP32_FAST_CLK_XTALD4 = 0, + ESP32_FAST_CLK_8M = 1 +} Esp32FastClkSel; + +typedef enum Esp32SlowClkSel { + ESP32_SLOW_CLK_RC = 0, + ESP32_SLOW_CLK_32KXTAL = 1, + ESP32_SLOW_CLK_8MD256 = 2 +} Esp32SlowClkSel; + +typedef struct Esp32RtcCntlState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + qemu_irq dig_reset_req; + qemu_irq cpu_reset_req[ESP32_CPU_COUNT]; + qemu_irq cpu_stall_req[ESP32_CPU_COUNT]; + qemu_irq clk_update; + bool cpu_stall_state[ESP32_CPU_COUNT]; + + uint32_t xtal_apb_freq; + uint32_t pll_apb_freq; + Esp32SocClkSel soc_clk; + Esp32FastClkSel rtc_fastclk; + uint32_t rtc_fastclk_freq; + Esp32SlowClkSel rtc_slowclk; + uint32_t rtc_slowclk_freq; + int64_t time_base_ns; + + uint32_t options0_reg; + uint64_t time_reg; + uint32_t sw_cpu_stall_reg; + uint32_t scratch_reg[ESP32_RTC_CNTL_SCRATCH_REG_COUNT]; + Esp32ResetCause reset_cause[ESP32_CPU_COUNT]; + bool stat_vector_sel[ESP32_CPU_COUNT]; +} Esp32RtcCntlState; + +REG32(RTC_CNTL_OPTIONS0, 0x00) + FIELD(RTC_CNTL_OPTIONS0, SW_SYS_RESET, 31, 1) + FIELD(RTC_CNTL_OPTIONS0, SW_PROCPU_RESET, 5, 1) + FIELD(RTC_CNTL_OPTIONS0, SW_APPCPU_RESET, 4, 1) + FIELD(RTC_CNTL_OPTIONS0, SW_STALL_PROCPU_C0, 2, 2) + FIELD(RTC_CNTL_OPTIONS0, SW_STALL_APPCPU_C0, 0, 2) + +REG32(RTC_CNTL_TIME_UPDATE, 0xc) + FIELD(RTC_CNTL_TIME_UPDATE, UPDATE, 31, 1) + FIELD(RTC_CNTL_TIME_UPDATE, VALID, 30, 1) +REG32(RTC_CNTL_TIME0, 0x10) +REG32(RTC_CNTL_TIME1, 0x14) + +REG32(RTC_CNTL_RESET_STATE, 0x34) + FIELD(RTC_CNTL_RESET_STATE, PROCPU_STAT_VECTOR_SEL, 13, 1) + FIELD(RTC_CNTL_RESET_STATE, APPCPU_STAT_VECTOR_SEL, 12, 1) + FIELD(RTC_CNTL_RESET_STATE, RESET_CAUSE_APPCPU, 6, 6) + FIELD(RTC_CNTL_RESET_STATE, RESET_CAUSE_PROCPU, 0, 6) + +REG32(RTC_CNTL_STORE0, 0x4c) +REG32(RTC_CNTL_STORE1, 0x50) +REG32(RTC_CNTL_STORE2, 0x54) +REG32(RTC_CNTL_STORE3, 0x58) + +REG32(RTC_CNTL_CLK_CONF, 0x70) + FIELD(RTC_CNTL_CLK_CONF, ANA_CLK_RTC_SEL, 30, 2) + FIELD(RTC_CNTL_CLK_CONF, FAST_CLK_RTC_SEL, 29, 1) + FIELD(RTC_CNTL_CLK_CONF, SOC_CLK_SEL, 27, 2) + +REG32(RTC_CNTL_SW_CPU_STALL, 0xac) + FIELD(RTC_CNTL_SW_CPU_STALL, PROCPU_C1, 26, 6) + FIELD(RTC_CNTL_SW_CPU_STALL, APPCPU_C1, 20, 6) + +REG32(RTC_CNTL_STORE4, 0xb0) +REG32(RTC_CNTL_STORE5, 0xb4) +REG32(RTC_CNTL_STORE6, 0xb8) +REG32(RTC_CNTL_STORE7, 0xbc) +REG32(RTC_CNTL_DATE, 0x13c) + +#define ESP32_RTC_CNTL_SIZE (A_RTC_CNTL_DATE + 4) From 84ccfb907e6a54b13656f1c55c17100da6b07227 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:38:22 +0200 Subject: [PATCH 11/16] hw/misc: ESP32 RNG --- hw/misc/Makefile.objs | 1 + hw/misc/esp32_rng.c | 56 +++++++++++++++++++++++++++++++++++++ include/hw/misc/esp32_rng.h | 17 +++++++++++ 3 files changed, 74 insertions(+) create mode 100644 hw/misc/esp32_rng.c create mode 100644 include/hw/misc/esp32_rng.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 70d44adede5c1..42455feb9b75e 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -87,3 +87,4 @@ obj-$(CONFIG_ESP32) += esp32_dport.o obj-$(CONFIG_ESP32) += esp32_intmatrix.o obj-$(CONFIG_ESP32) += esp32_crosscore_int.o obj-$(CONFIG_ESP32) += esp32_rtc_cntl.o +obj-$(CONFIG_ESP32) += esp32_rng.o diff --git a/hw/misc/esp32_rng.c b/hw/misc/esp32_rng.c new file mode 100644 index 0000000000000..9df49de9a5278 --- /dev/null +++ b/hw/misc/esp32_rng.c @@ -0,0 +1,56 @@ +/* + * ESP32 Random Number Generator peripheral + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qemu/guest-random.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/misc/esp32_rng.h" + + +static uint64_t esp32_rng_read(void *opaque, hwaddr addr, unsigned int size) +{ + uint32_t r = 0; + qemu_guest_getrandom_nofail(&r, sizeof(r)); + return r; +} + +static const MemoryRegionOps esp32_rng_ops = { + .read = esp32_rng_read, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_rng_init(Object *obj) +{ + Esp32RngState *s = ESP32_RNG(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &esp32_rng_ops, s, + TYPE_ESP32_RNG, sizeof(uint32_t)); + sysbus_init_mmio(sbd, &s->iomem); +} + + +static const TypeInfo esp32_rng_info = { + .name = TYPE_ESP32_RNG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32RngState), + .instance_init = esp32_rng_init, +}; + +static void esp32_rng_register_types(void) +{ + type_register_static(&esp32_rng_info); +} + +type_init(esp32_rng_register_types) diff --git a/include/hw/misc/esp32_rng.h b/include/hw/misc/esp32_rng.h new file mode 100644 index 0000000000000..1065310a3c161 --- /dev/null +++ b/include/hw/misc/esp32_rng.h @@ -0,0 +1,17 @@ +#pragma once + +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/misc/esp32_reg.h" + + +#define TYPE_ESP32_RNG "misc.esp32.rng" +#define ESP32_RNG(obj) OBJECT_CHECK(Esp32RngState, (obj), TYPE_ESP32_RNG) + +typedef struct Esp32RngState { + SysBusDevice parent_obj; + MemoryRegion iomem; +} Esp32RngState; + +#define ESP32_RNG_BASE (DR_REG_WDEV_BASE + 0x144) + From 19c36d3fafd1cab8a342205ad0cfa317637c9e7d Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:38:50 +0200 Subject: [PATCH 12/16] hw/misc: add ESP32 SHA --- hw/misc/Makefile.objs | 1 + hw/misc/esp32_sha.c | 184 ++++++++++++++++++++++++++++++++++++ include/hw/misc/esp32_sha.h | 31 ++++++ 3 files changed, 216 insertions(+) create mode 100644 hw/misc/esp32_sha.c create mode 100644 include/hw/misc/esp32_sha.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 42455feb9b75e..3fee730e3c313 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -88,3 +88,4 @@ obj-$(CONFIG_ESP32) += esp32_intmatrix.o obj-$(CONFIG_ESP32) += esp32_crosscore_int.o obj-$(CONFIG_ESP32) += esp32_rtc_cntl.o obj-$(CONFIG_ESP32) += esp32_rng.o +obj-$(CONFIG_ESP32) += esp32_sha.o diff --git a/hw/misc/esp32_sha.c b/hw/misc/esp32_sha.c new file mode 100644 index 0000000000000..387e20c10c5c6 --- /dev/null +++ b/hw/misc/esp32_sha.c @@ -0,0 +1,184 @@ +/* + * ESP32 SHA accelerator + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "crypto/hash.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/boards.h" +#include "hw/misc/esp32_sha.h" + +#define ESP32_SHA_REGS_SIZE (A_SHA512_BUSY + 4) + +/* QEMU hash API includes only the "qcrypto_hash_bytes" function which takes + * bytes as input, and calculates the digest. It doesn't allow "updating" + * the state multiple times with blocks of input. Therefore we collect all + * the input in an array (s->full_text) and when SHA_X_LOAD_REG is set, + * we call "qcrypto_hash_bytes" to get the digest. + */ + +static void esp32_sha_text_reg_byteswap_to(Esp32ShaState* s, uint32_t* dst, size_t len_words) +{ + for (int i = 0; i < len_words; ++i) { + dst[i] = __builtin_bswap32(s->text[i]); + } +} + + +static inline QCryptoHashAlgorithm algorithm_for_addr(hwaddr reg_addr) +{ + const QCryptoHashAlgorithm hash_alg_for_reg[] = { + QCRYPTO_HASH_ALG_SHA1, + QCRYPTO_HASH_ALG_SHA256, + QCRYPTO_HASH_ALG_SHA384, + QCRYPTO_HASH_ALG_SHA512 + }; + size_t index = (reg_addr - A_SHA1_START) / 0x10; + return hash_alg_for_reg[index]; +} + +static uint32_t hash_block_bytes[] = { + [QCRYPTO_HASH_ALG_SHA1] = 64, + [QCRYPTO_HASH_ALG_SHA256] = 64, + [QCRYPTO_HASH_ALG_SHA384] = 128, + [QCRYPTO_HASH_ALG_SHA512] = 128, +}; + +static void esp32_sha_update_text(Esp32ShaState* s, QCryptoHashAlgorithm hash_alg) +{ + uint32_t block_len_bytes = hash_block_bytes[hash_alg]; + if (s->full_text_len + block_len_bytes > s->full_text_reserved) { + uint32_t full_text_reserved = MAX(s->full_text_reserved * 2, s->full_text_reserved + block_len_bytes); + uint8_t *new_full_text = g_realloc(s->full_text, full_text_reserved); + s->full_text_reserved = full_text_reserved; + s->full_text = new_full_text; + } + esp32_sha_text_reg_byteswap_to(s, (uint32_t*) (s->full_text + s->full_text_len), block_len_bytes/4); + s->full_text_len += block_len_bytes; +} + +static void esp32_sha_finish(Esp32ShaState *s, QCryptoHashAlgorithm hash_alg) +{ + /* ESP32 SHA accelerator accepts padded blocks (doesn't do any extra padding), but + * qcrypto_hash_bytes adds padding after the last block. Remove the padding by checking + * the bit count in the last block. This may give results different from what the hardware + * would give if the guest application pads the block incorrectly. + */ + uint8_t *result = (uint8_t*) s->text; + size_t result_len = qcrypto_hash_digest_len(hash_alg); + assert(result_len <= sizeof(s->text)); + if (s->full_text_len % hash_block_bytes[hash_alg] != 0) { + error_report("esp32_sha_finish: invalid text length %" PRIx32 "\n", s->full_text_len); + } else { + uint32_t byte_count; + memcpy(&byte_count, s->full_text + s->full_text_len - sizeof(byte_count), sizeof(byte_count)); + byte_count = __builtin_bswap32(byte_count) / 8; + if (byte_count > s->full_text_len) { + error_report("esp32_sha_finish: invalid byte count %" PRIx32 "\n", byte_count); + } else { + qcrypto_hash_bytes(hash_alg, (const char*) s->full_text, byte_count, &result, &result_len, &error_abort); + esp32_sha_text_reg_byteswap_to(s, (uint32_t*) s->text, result_len/4); + } + } + g_free(s->full_text); + s->full_text = NULL; + s->full_text_len = 0; + s->full_text_reserved = 0; +} + +static uint64_t esp32_sha_read(void *opaque, hwaddr addr, unsigned int size) +{ + Esp32ShaState *s = ESP32_SHA(opaque); + uint64_t r = 0; + switch (addr) { + case 0 ... (ESP32_SHA_TEXT_REG_CNT - 1) * sizeof(uint32_t): + r = s->text[addr / sizeof(uint32_t)]; + break; + } + return r; +} + +static void esp32_sha_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + Esp32ShaState *s = ESP32_SHA(opaque); + switch (addr) { + case 0 ... (ESP32_SHA_TEXT_REG_CNT - 1) * sizeof(uint32_t): + s->text[addr / sizeof(uint32_t)] = value; + break; + case A_SHA1_START: + case A_SHA1_CONTINUE: + case A_SHA256_START: + case A_SHA256_CONTINUE: + case A_SHA384_START: + case A_SHA384_CONTINUE: + case A_SHA512_START: + case A_SHA512_CONTINUE: + esp32_sha_update_text(s, algorithm_for_addr(addr)); + break; + case A_SHA1_LOAD: + case A_SHA256_LOAD: + case A_SHA384_LOAD: + case A_SHA512_LOAD: + esp32_sha_finish(s, algorithm_for_addr(addr)); + break; + } +} + +static const MemoryRegionOps esp32_sha_ops = { + .read = esp32_sha_read, + .write = esp32_sha_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_sha_reset(DeviceState *dev) +{ + Esp32ShaState *s = ESP32_SHA(dev); + g_free(s->full_text); + s->full_text = NULL; + s->full_text_len = 0; + s->full_text_reserved = 0; +} + +static void esp32_sha_init(Object *obj) +{ + Esp32ShaState *s = ESP32_SHA(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &esp32_sha_ops, s, + TYPE_ESP32_SHA, ESP32_SHA_REGS_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void esp32_sha_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_sha_reset; +} + +static const TypeInfo esp32_sha_info = { + .name = TYPE_ESP32_SHA, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32ShaState), + .instance_init = esp32_sha_init, + .class_init = esp32_sha_class_init +}; + +static void esp32_sha_register_types(void) +{ + type_register_static(&esp32_sha_info); +} + +type_init(esp32_sha_register_types) diff --git a/include/hw/misc/esp32_sha.h b/include/hw/misc/esp32_sha.h new file mode 100644 index 0000000000000..40fc599365711 --- /dev/null +++ b/include/hw/misc/esp32_sha.h @@ -0,0 +1,31 @@ +#pragma once + +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/misc/esp32_reg.h" + +#define TYPE_ESP32_SHA "misc.esp32.sha" +#define ESP32_SHA(obj) OBJECT_CHECK(Esp32ShaState, (obj), TYPE_ESP32_SHA) + +#define ESP32_SHA_TEXT_REG_CNT 32 + +typedef struct Esp32ShaState { + SysBusDevice parent_obj; + MemoryRegion iomem; + uint32_t text[ESP32_SHA_TEXT_REG_CNT]; + uint8_t* full_text; + uint32_t full_text_reserved; + uint32_t full_text_len; +} Esp32ShaState; + +#define SHA_REG_GROUP(name, base) \ + REG32(name ## _START, (base)) \ + REG32(name ## _CONTINUE, (base + 0x4)) \ + REG32(name ## _LOAD, (base + 0x8)) \ + REG32(name ## _BUSY, (base + 0xc)) + +SHA_REG_GROUP(SHA1, 0x80) +SHA_REG_GROUP(SHA256, 0x90) +SHA_REG_GROUP(SHA384, 0xa0) +SHA_REG_GROUP(SHA512, 0xb0) From e203074e4100ac1ab56100ab7e40897b6e5520a4 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:39:32 +0200 Subject: [PATCH 13/16] hw/timer: add ESP32 timers --- hw/timer/Makefile.objs | 3 + hw/timer/esp32_frc_timer.c | 245 +++++++++++ hw/timer/esp32_timg.c | 664 +++++++++++++++++++++++++++++ hw/timer/trace-events | 7 + include/hw/timer/esp32_frc_timer.h | 49 +++ include/hw/timer/esp32_timg.h | 217 ++++++++++ 6 files changed, 1185 insertions(+) create mode 100644 hw/timer/esp32_frc_timer.c create mode 100644 hw/timer/esp32_timg.c create mode 100644 include/hw/timer/esp32_frc_timer.h create mode 100644 include/hw/timer/esp32_timg.h diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index dece235fd72e6..e73504bcdc769 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -35,3 +35,6 @@ common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o common-obj-$(CONFIG_CMSDK_APB_DUALTIMER) += cmsdk-apb-dualtimer.o common-obj-$(CONFIG_MSF2) += mss-timer.o common-obj-$(CONFIG_RASPI) += bcm2835_systmr.o + +obj-$(CONFIG_ESP32) += esp32_frc_timer.o +obj-$(CONFIG_ESP32) += esp32_timg.o diff --git a/hw/timer/esp32_frc_timer.c b/hw/timer/esp32_frc_timer.c new file mode 100644 index 0000000000000..b9fab2d503232 --- /dev/null +++ b/hw/timer/esp32_frc_timer.c @@ -0,0 +1,245 @@ +/* + * ESP32 FRC (legacy) timer + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/boards.h" +#include "hw/timer/esp32_frc_timer.h" +#include "trace.h" + +static uint64_t esp32_frc_timer_get_count(Esp32FrcTimerState *s, uint64_t ns_now) +{ + if (!s->enable) { + return s->count_base; + } + uint64_t ns_from_base = ns_now - s->ns_base; + uint64_t ticks_from_base = muldiv64(ns_from_base, s->apb_freq, NANOSECONDS_PER_SECOND * s->prescaler); + uint64_t count = (ticks_from_base + s->count_base) & s->count_mask; + return count; +} + +static uint64_t esp32_frc_timer_count_to_ns(Esp32FrcTimerState *s, uint64_t count) +{ + return muldiv64(count, NANOSECONDS_PER_SECOND * s->prescaler, s->apb_freq); +} + +static void esp32_frc_timer_update_alarm(Esp32FrcTimerState *s, uint64_t ticks_alarm, uint32_t ticks_now, uint64_t ns_now) +{ + if (ticks_alarm <= ticks_now) { + ticks_alarm += (1ULL << 32); + } + uint64_t ticks_to_alarm = ticks_alarm - ticks_now; + uint64_t ns_to_alarm = esp32_frc_timer_count_to_ns(s, ticks_to_alarm); + trace_esp32_frc_timer_update_alarm(ns_now, ticks_now, ticks_alarm, ns_to_alarm); + timer_mod_anticipate_ns(&s->alarm_timer, ns_now + ns_to_alarm); +} + +static void esp32_frc_timer_cb(void *opaque) +{ + Esp32FrcTimerState *s = ESP32_FRC_TIMER(opaque); + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint32_t count_now = esp32_frc_timer_get_count(s, ns_now); + trace_esp32_frc_timer_cb(ns_now, count_now); + + if (s->level_int) { + s->level_int_status = true; + qemu_irq_raise(s->irq); + } else { + qemu_irq_pulse(s->irq); + } + + if (s->autoload) { + esp32_frc_timer_update_alarm(s, s->alarm_reg, count_now, ns_now); + } +} + +static void esp32_frc_timer_update_config(Esp32FrcTimerState *s, + bool enable, bool level_int, bool autoload, int prescaler) +{ + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint32_t count_now = esp32_frc_timer_get_count(s, ns_now); + trace_esp32_frc_timer_update_config(ns_now, count_now, enable, level_int, autoload, prescaler); + + s->count_base = count_now; + s->ns_base = ns_now; + + if (!enable) { + timer_del(&s->alarm_timer); + } else { + esp32_frc_timer_update_alarm(s, s->alarm_reg, count_now, ns_now); + } + + s->enable = enable; + s->level_int = level_int; + s->autoload = autoload; + s->prescaler = prescaler; +} + + +static uint64_t esp32_frc_timer_read(void *opaque, hwaddr addr, unsigned int size) +{ + Esp32FrcTimerState *s = ESP32_FRC_TIMER(opaque); + uint64_t r = 0; + switch (addr) { + case A_FRC_TIMER_ALARM: + r = s->alarm_reg; + break; + case A_FRC_TIMER_LOAD: + r = s->load_reg; + break; + case A_FRC_TIMER_CTRL: + r = FIELD_DP32(r, FRC_TIMER_CTRL, LEVEL_INT, s->level_int); + r = FIELD_DP32(r, FRC_TIMER_CTRL, PRESCALER, (s->prescaler == 1) ? 0 : (s->prescaler == 16) ? 2 : 4); + r = FIELD_DP32(r, FRC_TIMER_CTRL, AUTOLOAD, s->autoload); + r = FIELD_DP32(r, FRC_TIMER_CTRL, ENABLE, s->enable); + r = FIELD_DP32(r, FRC_TIMER_CTRL, STATUS, s->level_int_status); + break; + case A_FRC_TIMER_COUNT: { + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + r = (uint32_t) esp32_frc_timer_get_count(s, ns_now); + break; + } + case A_FRC_TIMER_INT_CLR: + default: + break; + } + trace_esp32_frc_timer_read(addr, r); + return r; +} + +static void esp32_frc_timer_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + Esp32FrcTimerState *s = ESP32_FRC_TIMER(opaque); + trace_esp32_frc_timer_write(addr, value); + switch (addr) { + case A_FRC_TIMER_INT_CLR: + if (value & 1) { + if (s->level_int_status) { + qemu_irq_lower(s->irq); + } + s->level_int_status = false; + } + break; + case A_FRC_TIMER_LOAD: + s->load_reg = value; + s->ns_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->count_base = value; + break; + case A_FRC_TIMER_CTRL: { + bool level_int = FIELD_EX32(value, FRC_TIMER_CTRL, LEVEL_INT); + int prescaler = FIELD_EX32(value, FRC_TIMER_CTRL, PRESCALER); + bool autoload = FIELD_EX32(value, FRC_TIMER_CTRL, AUTOLOAD); + bool enable = FIELD_EX32(value, FRC_TIMER_CTRL, ENABLE); + if (prescaler == 2) { + prescaler = 16; + } else if (prescaler == 4) { + prescaler = 256; + } else { + prescaler = 1; + } + esp32_frc_timer_update_config(s, enable, level_int, autoload, prescaler); + break; + } + case A_FRC_TIMER_ALARM: { + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint32_t count_now = esp32_frc_timer_get_count(s, ns_now); + s->alarm_reg = value; + esp32_frc_timer_update_alarm(s, s->alarm_reg, count_now, ns_now); + break; + } + } +} + +static void esp32_frc_timer_set_apb_freq(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + Esp32FrcTimerState *s = ESP32_FRC_TIMER(opaque); + visit_type_uint32(v, name, &s->apb_freq, errp); + +} + +static const MemoryRegionOps esp32_frc_timer_ops = { + .read = esp32_frc_timer_read, + .write = esp32_frc_timer_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_frc_timer_reset(DeviceState *dev) +{ + Esp32FrcTimerState *s = ESP32_FRC_TIMER(dev); + + s->prescaler = 1; +} + +static void esp32_frc_timer_realize(DeviceState *dev, Error **errp) +{ +} + +static void esp32_frc_timer_init(Object *obj) +{ + Esp32FrcTimerState *s = ESP32_FRC_TIMER(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &esp32_frc_timer_ops, s, + TYPE_ESP32_FRC_TIMER, A_FRC_TIMER_ALARM + 4); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + + object_property_add(obj, "apb_freq", "uint32", + NULL, + esp32_frc_timer_set_apb_freq, + NULL, + obj, &error_abort); + + + timer_init_ns(&s->alarm_timer, QEMU_CLOCK_VIRTUAL, esp32_frc_timer_cb, s); + + s->apb_freq = 80000000; + s->count_mask = UINT32_MAX; + s->has_alarm = true; +} + +static Property esp32_frc_timer_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_frc_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_frc_timer_reset; + dc->realize = esp32_frc_timer_realize; + dc->props = esp32_frc_timer_properties; +} + +static const TypeInfo esp32_frc_timer_info = { + .name = TYPE_ESP32_FRC_TIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32FrcTimerState), + .instance_init = esp32_frc_timer_init, + .class_init = esp32_frc_timer_class_init +}; + +static void esp32_frc_timer_register_types(void) +{ + type_register_static(&esp32_frc_timer_info); +} + +type_init(esp32_frc_timer_register_types) diff --git a/hw/timer/esp32_timg.c b/hw/timer/esp32_timg.c new file mode 100644 index 0000000000000..0590cc488758d --- /dev/null +++ b/hw/timer/esp32_timg.c @@ -0,0 +1,664 @@ +/* + * ESP32 "Timer Group" peripheral + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/registerfields.h" +#include "hw/boards.h" +#include "hw/timer/esp32_timg.h" + + +#define TIMG_REGFILE_SIZE 0x100 + +static uint64_t esp32_timg_timer_get_count(Esp32TimgTimerState *s, uint64_t ns_now); +static uint64_t esp32_timg_timer_count_to_ns(Esp32TimgTimerState *s, uint64_t count); +static void esp32_timg_timer_update_config(Esp32TimgTimerState *ts); +static void esp32_timg_timer_update_alarm(Esp32TimgTimerState *ts, uint64_t ns_now); +static void esp32_timg_timer_reload(Esp32TimgTimerState *ts, uint64_t ns_now); +static void esp32_timg_do_calibration(Esp32TimgState* s); +static void esp32_timg_int_update(Esp32TimgState *s); +static bool esp32_timg_wdt_protected(Esp32TimgWdtState *ws); +static void esp32_timg_wdt_update_config(Esp32TimgWdtState *ws); +static void esp32_timg_wdt_feed(Esp32TimgWdtState *ws); +static void esp32_timg_wdt_arm(Esp32TimgWdtState *ws, uint64_t ns_now); + + +#define TIMG_DEBUG_LOG(...) // qemu_log(__VA_ARGS__) + +static inline void set_low_word(uint64_t *dst, uint32_t word) +{ + *dst = (*dst & ~UINT32_MAX) | word; +} + +static inline void set_high_word(uint64_t *dst, uint32_t word) +{ + *dst = (*dst & UINT32_MAX) | (((uint64_t)word) << 32); +} + +static inline qemu_irq get_level_irq(Esp32TimgState* s, Esp32TimgInterruptType it) +{ + return s->irqs[it]; +} + +static inline qemu_irq get_edge_irq(Esp32TimgState* s, Esp32TimgInterruptType it) +{ + return s->irqs[TIMG_INT_MAX + it]; +} + + +static uint64_t esp32_timg_read(void *opaque, hwaddr addr, unsigned int size) +{ + Esp32TimgState *s = ESP32_TIMG(opaque); + Esp32TimgTimerState *ts = NULL; + if (addr <= A_TIMG_T0LOAD) { + ts = &s->t0; + } else if (addr <= A_TIMG_T1LOAD) { + ts = &s->t1; + } else if (addr >= A_TIMG_LACTCONFIG && addr < A_TIMG_LACTLOAD) { + ts = &s->lact; + } + uint64_t r = 0; + switch (addr) { + case A_TIMG_T0CONFIG: + case A_TIMG_T1CONFIG: + case A_TIMG_LACTCONFIG: + r = ts->config_reg; + break; + case A_TIMG_T0LO: + case A_TIMG_T1LO: + case A_TIMG_LACTLO: + r = ts->last_val & UINT32_MAX; + break; + case A_TIMG_T0HI: + case A_TIMG_T1HI: + case A_TIMG_LACTHI: + r = ts->last_val >> 32; + break; + case A_TIMG_T0LOADLO: + case A_TIMG_T1LOADLO: + case A_TIMG_LACTLOADLO: + r = ts->load_val & UINT32_MAX; + break; + case A_TIMG_T0LOADHI: + case A_TIMG_T1LOADHI: + case A_TIMG_LACTLOADHI: + r = ts->load_val >> 32; + break; + case A_TIMG_T0ALARMLO: + case A_TIMG_T1ALARMLO: + case A_TIMG_LACTALARMLO: + r = ts->alarm_val & UINT32_MAX; + break; + case A_TIMG_T0ALARMHI: + case A_TIMG_T1ALARMHI: + case A_TIMG_LACTALARMHI: + r = ts->alarm_val >> 32; + break; + + case A_TIMG_WDTCONFIG0: + r = s->wdt.config0_reg; + break; + case A_TIMG_WDTCONFIG1: + r = FIELD_DP32(r, TIMG_WDTCONFIG1, PRESCALE, s->wdt.prescale); + break; + case A_TIMG_WDTCONFIG2: + case A_TIMG_WDTCONFIG3: + case A_TIMG_WDTCONFIG4: + case A_TIMG_WDTCONFIG5: { + int stage = (addr - A_TIMG_WDTCONFIG2) / 4; + r = s->wdt.timeout[stage]; + break; + } + case A_TIMG_WDTPROTECT: + r = s->wdt.protect_reg; + break; + + case A_TIMG_RTCCALICFG: + r = FIELD_DP32(r, TIMG_RTCCALICFG, START, s->rtc_cal_start); + r = FIELD_DP32(r, TIMG_RTCCALICFG, MAX, s->rtc_cal_max); + r = FIELD_DP32(r, TIMG_RTCCALICFG, RDY, s->rtc_cal_ready); + r = FIELD_DP32(r, TIMG_RTCCALICFG, CLK_SEL, s->rtc_cal_clk_sel); + break; + case A_TIMG_RTCCALICFG1: + r = FIELD_DP32(0, TIMG_RTCCALICFG1, VALUE, s->rtc_cal_value); + break; + + case A_TIMG_INT_ENA: + r = s->int_ena; + break; + case A_TIMG_INT_RAW: + r = s->int_raw; + break; + case A_TIMG_INT_ST: + r = s->int_ena & s->int_raw; + break; + } + return r; +} + +static void esp32_timg_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + Esp32TimgState *s = ESP32_TIMG(opaque); + Esp32TimgTimerState *ts = NULL; + if (addr <= A_TIMG_T0LOAD) { + ts = &s->t0; + } else if (addr <= A_TIMG_T1LOAD) { + ts = &s->t1; + } else if (addr >= A_TIMG_LACTCONFIG && addr < A_TIMG_LACTLOAD) { + ts = &s->lact; + } + + switch (addr) { + case A_TIMG_T0CONFIG: + case A_TIMG_T1CONFIG: + case A_TIMG_LACTCONFIG: + ts->config_reg = value; + esp32_timg_timer_update_config(ts); + break; + case A_TIMG_T0UPDATE: + case A_TIMG_T1UPDATE: + case A_TIMG_LACTUPDATE: { + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ts->last_val = esp32_timg_timer_get_count(ts, ns_now); + break; + } + case A_TIMG_T0LOADLO: + case A_TIMG_T1LOADLO: + case A_TIMG_LACTLOADLO: + set_low_word(&ts->load_val, value); + break; + case A_TIMG_T0LOADHI: + case A_TIMG_T1LOADHI: + case A_TIMG_LACTLOADHI: + set_high_word(&ts->load_val, value); + break; + case A_TIMG_T0LOAD: + case A_TIMG_T1LOAD: + case A_TIMG_LACTLOAD: { + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + esp32_timg_timer_reload(ts, ns_now); + break; + } + case A_TIMG_T0ALARMLO: + case A_TIMG_T1ALARMLO: + case A_TIMG_LACTALARMLO: + set_low_word(&ts->alarm_val, value); + break; + case A_TIMG_T0ALARMHI: + case A_TIMG_T1ALARMHI: + case A_TIMG_LACTALARMHI: + set_high_word(&ts->alarm_val, value); + break; + + case A_TIMG_WDTCONFIG0: + if (!esp32_timg_wdt_protected(&s->wdt)) { + s->wdt.config0_reg = value; + esp32_timg_wdt_update_config(&s->wdt); + } else { + TIMG_DEBUG_LOG("failed to write TIMG_WDTCONFIG0, write protected (0x%08x)\n", s->wdt.protect_reg); + } + break; + case A_TIMG_WDTCONFIG1: + if (!esp32_timg_wdt_protected(&s->wdt)) { + s->wdt.config1_reg = value; + esp32_timg_wdt_update_config(&s->wdt); + } + break; + case A_TIMG_WDTCONFIG2: + case A_TIMG_WDTCONFIG3: + case A_TIMG_WDTCONFIG4: + case A_TIMG_WDTCONFIG5: { + if (!esp32_timg_wdt_protected(&s->wdt)) { + int stage = (addr - A_TIMG_WDTCONFIG2) / 4; + s->wdt.timeout[stage] = value; + } + break; + } + case A_TIMG_WDTFEED: + if (!esp32_timg_wdt_protected(&s->wdt)) { + esp32_timg_wdt_feed(&s->wdt); + } + break; + case A_TIMG_WDTPROTECT: + s->wdt.protect_reg = value; + break; + + + case A_TIMG_RTCCALICFG: + s->rtc_cal_start = FIELD_EX32(value, TIMG_RTCCALICFG, START); + s->rtc_cal_ready = FIELD_EX32(value, TIMG_RTCCALICFG, RDY); + s->rtc_cal_clk_sel = FIELD_EX32(value, TIMG_RTCCALICFG, CLK_SEL); + s->rtc_cal_max = FIELD_EX32(value, TIMG_RTCCALICFG, MAX); + esp32_timg_do_calibration(s); + break; + + case A_TIMG_INT_ENA: + s->int_ena = value; + esp32_timg_int_update(s); + break; + case A_TIMG_INT_CLR: + s->int_raw &= ~value; + esp32_timg_int_update(s); + break; + } +} + +static const MemoryRegionOps esp32_timg_ops = { + .read = esp32_timg_read, + .write = esp32_timg_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void esp32_timg_timer_reset(Esp32TimgTimerState* ts) +{ + timer_del(&ts->alarm_timer); + ts->config_reg = R_TIMG_T0CONFIG_INCREASE_MASK + | R_TIMG_T0CONFIG_AUTORELOAD_MASK + | (1 << R_TIMG_T0CONFIG_DIVIDER_SHIFT); + ts->alarm_val = 0; + ts->load_val = 0; + ts->count_base = 0; + ts->ns_base = 0; + esp32_timg_timer_update_config(ts); +} + +static void esp32_timg_wdt_reset(Esp32TimgWdtState* ws) +{ + timer_del(&ws->stage_timer); + + ws->config0_reg = 0x0004c000; + ws->config1_reg = 0x00010000; + ws->timeout[0] = 0x018cba80; + ws->timeout[1] = 0x07ffffff; + ws->timeout[2] = 0x000fffff; + ws->timeout[3] = 0x000fffff; + ws->protect_reg = ESP32_TIMG_WDT_PROTECT_WORD; + + if (ws->parent->wdt_en_at_reset) { + /* On reset, stage0 is configured as system reset, however this is done by + * hardware state, not in config0 register. Emulate this by temporarily setting STG0 field here. + */ + ws->config0_reg |= (WDT_MODE_SYSRESET << R_TIMG_WDTCONFIG0_STG0_SHIFT); + } + esp32_timg_wdt_update_config(ws); + if (ws->parent->wdt_en_at_reset) { + ws->config0_reg &= (~R_TIMG_WDTCONFIG0_STG0_MASK); + } +} + +static void esp32_timg_reset(DeviceState *dev) +{ + Esp32TimgState *s = ESP32_TIMG(dev); + s->rtc_cal_max = 1; + s->rtc_cal_clk_sel = ESP32_TIMG_CAL_8MD256; + s->rtc_cal_ready = 0; + s->rtc_cal_start = 1; + esp32_timg_do_calibration(s); + + esp32_timg_timer_reset(&s->t0); + esp32_timg_timer_reset(&s->t1); + esp32_timg_timer_reset(&s->lact); + esp32_timg_wdt_reset(&s->wdt); +} + +static void esp32_timg_set_apb_freq(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + Esp32TimgState *s = ESP32_TIMG(opaque); + visit_type_uint32(v, name, &s->apb_freq_hz, errp); + TIMG_DEBUG_LOG("%s: TG%d apb_freq_hz=%d\n", __func__, s->id, s->apb_freq_hz); +} + +static void esp32_timg_do_calibration(Esp32TimgState* s) +{ + uint32_t cal_clk_freq; + if (s->rtc_cal_clk_sel == ESP32_TIMG_CAL_RTC_MUX) { + cal_clk_freq = s->rtc_slow_freq_hz; + } else if (s->rtc_cal_clk_sel == ESP32_TIMG_CAL_32K_XTAL) { + cal_clk_freq = 32768; + } else { + cal_clk_freq = 8000000 / 256; + } + + s->rtc_cal_value = muldiv64(s->xtal_freq_hz, s->rtc_cal_max, cal_clk_freq); + s->rtc_cal_ready = true; +} + +static void esp32_timg_timer_cb(void *opaque) +{ + Esp32TimgTimerState *ts = (Esp32TimgTimerState*) opaque; + Esp32TimgState *s = ts->parent; + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + TIMG_DEBUG_LOG("%s: TG%d ns=0x%llx\n", __func__, s->id, ns_now); + uint32_t int_mask = 1 << (ts->int_type); + + if (ts->level_int_en) { + s->int_raw |= int_mask; + if (s->int_ena & int_mask) { + qemu_irq_raise(get_level_irq(s, ts->int_type)); + } + } + + if (ts->edge_int_en) { + if (s->int_ena & int_mask) { + qemu_irq_pulse(get_edge_irq(s, ts->int_type)); + } + } + + ts->alarm = false; + + if (ts->autoreload) { + esp32_timg_timer_reload(ts, ns_now); + } else { + /* ignore overflow modulo 64 bits */ + timer_del(&ts->alarm_timer); + } +} + +static void esp32_timg_int_update_inttype(Esp32TimgState *s, uint32_t int_st, Esp32TimgInterruptType it) +{ + if (int_st & (1 << it)) { + qemu_irq_raise(get_level_irq(s, it)); + } else { + qemu_irq_lower(get_level_irq(s, it)); + } +} + +static void esp32_timg_int_update(Esp32TimgState *s) +{ + uint32_t int_st = s->int_ena & s->int_raw; + esp32_timg_int_update_inttype(s, int_st, TIMG_T0_INT); + esp32_timg_int_update_inttype(s, int_st, TIMG_T1_INT); + esp32_timg_int_update_inttype(s, int_st, TIMG_WDT_INT); + esp32_timg_int_update_inttype(s, int_st, TIMG_LACT_INT); +} + +static int esp32_timg_timer_direction(Esp32TimgTimerState *s) +{ + if (!s->en) { + return 0; + } + if (s->inc) { + return 1; + } else { + return -1; + } +} + +static uint64_t esp32_timg_timer_get_count(Esp32TimgTimerState *s, uint64_t ns_now) +{ + if (!s->en) { + return s->count_base; + } + uint64_t ns_from_base = ns_now - s->ns_base; + uint64_t ticks_from_base = muldiv64(ns_from_base, s->parent->apb_freq_hz / 1000000, 1000 * s->divider); + uint64_t count = esp32_timg_timer_direction(s) * ticks_from_base + s->count_base; + return count; +} + +static uint64_t esp32_timg_timer_count_to_ns(Esp32TimgTimerState *s, uint64_t count) +{ + return muldiv64(count, 1000 * s->divider, s->parent->apb_freq_hz / 1000000); +} + +static uint32_t esp32_timg_timer_div_from_reg(uint32_t reg_val) +{ + if (reg_val == 0) { + return 65536; + } + if (reg_val == 1 || reg_val == 2) { + return 2; + } + return reg_val; +} + +static void esp32_timg_timer_update_config(Esp32TimgTimerState *ts) +{ + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ts->count_base = esp32_timg_timer_get_count(ts, ns_now); + ts->ns_base = ns_now; + + ts->en = FIELD_EX32(ts->config_reg, TIMG_T0CONFIG, EN); + ts->inc = FIELD_EX32(ts->config_reg, TIMG_T0CONFIG, INCREASE); + ts->autoreload = FIELD_EX32(ts->config_reg, TIMG_T0CONFIG, AUTORELOAD); + ts->divider = esp32_timg_timer_div_from_reg(FIELD_EX32(ts->config_reg, TIMG_T0CONFIG, DIVIDER)); + ts->edge_int_en = FIELD_EX32(ts->config_reg, TIMG_T0CONFIG, EDGE_INT); + ts->level_int_en = FIELD_EX32(ts->config_reg, TIMG_T0CONFIG, LEVEL_INT); + ts->alarm = FIELD_EX32(ts->config_reg, TIMG_T0CONFIG, ALARM); + + TIMG_DEBUG_LOG("%s: TG%d base=0x%llx ns=0x%llx en=%d inc=%d autoreload=%d div=%d li=%d ei=%d alarm=%d\n", __func__, ts->parent->id, + ts->count_base, ts->ns_base, ts->en, ts->inc, ts->autoreload, ts->divider, + ts->level_int_en, ts->edge_int_en, ts->alarm); + + esp32_timg_timer_update_alarm(ts, ns_now); +} + +static void esp32_timg_timer_reload(Esp32TimgTimerState *ts, uint64_t ns_now) +{ + timer_del(&ts->alarm_timer); + + ts->ns_base = ns_now; + ts->count_base = ts->load_val; + + TIMG_DEBUG_LOG("%s: TG%d base=0x%llx ns=0x%llx\n", __func__, ts->parent->id, + ts->count_base, ts->ns_base); + + esp32_timg_timer_update_alarm(ts, ns_now); +} + +static void esp32_timg_timer_update_alarm(Esp32TimgTimerState *ts, uint64_t ns_now) +{ + if (!ts->en || !ts->alarm) { + timer_del(&ts->alarm_timer); + return; + } + + int64_t count_to_alarm = ((int64_t) ts->alarm_val - (int64_t) ts->count_base) + * esp32_timg_timer_direction(ts); + if (count_to_alarm <= 0) { + /* ignore overflow modulo 64 bits */ + timer_del(&ts->alarm_timer); + return; + } + + uint64_t ns_to_alarm = esp32_timg_timer_count_to_ns(ts, count_to_alarm); + + TIMG_DEBUG_LOG("%s: TG%d count_to_alarm=0x%llx ns_to_alarm=0x%llx\n", __func__, ts->parent->id, + count_to_alarm, ns_to_alarm); + + timer_mod_anticipate_ns(&ts->alarm_timer, ns_now + ns_to_alarm); +} + +static bool esp32_timg_wdt_protected(Esp32TimgWdtState *ws) +{ + return ws->protect_reg != ESP32_TIMG_WDT_PROTECT_WORD; +} + +static uint64_t esp32_timg_wdt_get_count(Esp32TimgWdtState *ws, uint64_t ns_now) +{ + if (!ws->en) { + return ws->count_base; + } + uint64_t ns_from_base = ns_now - ws->ns_base; + uint64_t ticks_from_base = muldiv64(ns_from_base, ws->parent->apb_freq_hz / 1000000, 1000 * MAX(ws->prescale, 1)); + uint64_t count = ticks_from_base + ws->count_base; + return count; +} + +static void esp32_timg_wdt_update_config(Esp32TimgWdtState *ws) +{ + Esp32TimgState *s = ws->parent; + + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ws->count_base = esp32_timg_wdt_get_count(ws, ns_now); + ws->ns_base = ns_now; + + bool old_en = ws->en; + ws->en = FIELD_EX32(ws->config0_reg, TIMG_WDTCONFIG0, EN); + ws->mode[0] = FIELD_EX32(ws->config0_reg, TIMG_WDTCONFIG0, STG0); + ws->mode[1] = FIELD_EX32(ws->config0_reg, TIMG_WDTCONFIG0, STG1); + ws->mode[2] = FIELD_EX32(ws->config0_reg, TIMG_WDTCONFIG0, STG2); + ws->mode[3] = FIELD_EX32(ws->config0_reg, TIMG_WDTCONFIG0, STG3); + ws->edge_int_en = FIELD_EX32(ws->config0_reg, TIMG_WDTCONFIG0, EDGE_INT); + ws->level_int_en = FIELD_EX32(ws->config0_reg, TIMG_WDTCONFIG0, LEVEL_INT); + ws->flashboot_en = FIELD_EX32(ws->config0_reg, TIMG_WDTCONFIG0, FLASHBOOT_MODE_EN); + + ws->prescale = FIELD_EX32(ws->config1_reg, TIMG_WDTCONFIG1, PRESCALE); + + if (ws->en && !old_en) { + ws->cur_stage = 0; + ws->count_base = 0; + } else if (!ws->en && old_en) { + qemu_irq_lower(get_level_irq(s, TIMG_WDT_INT)); + } + + TIMG_DEBUG_LOG("%s: TG%d config 0x%08x prescale=0x%08x en=%d fb_en=%d level_int_en=%d\n", __func__, ws->parent->id, + ws->config0_reg, ws->prescale, ws->en, ws->flashboot_en, ws->level_int_en); + esp32_timg_wdt_arm(ws, ns_now); +} + +static void esp32_timg_wdt_feed(Esp32TimgWdtState *ws) +{ + TIMG_DEBUG_LOG("%s TG%d\n", __func__, ws->parent->id); + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ws->cur_stage = 0; + ws->ns_base = ns_now; + ws->count_base = 0; + esp32_timg_wdt_arm(ws, ns_now); +} + +static void esp32_timg_wdt_arm(Esp32TimgWdtState *ws, uint64_t ns_now) +{ + timer_del(&ws->stage_timer); + + if (ws->parent->wdt_disable || !(ws->en || (ws->flashboot_en && ws->parent->flash_boot_mode))) { + return; + } + + uint32_t stage_timeout = ws->timeout[ws->cur_stage]; + uint32_t cur_count = esp32_timg_wdt_get_count(ws, ns_now); + uint32_t count_to_timeout = stage_timeout - cur_count; + uint64_t ns_to_timeout = muldiv64(count_to_timeout, 1000 * ws->prescale, ws->parent->apb_freq_hz / 1000000); + TIMG_DEBUG_LOG("%s: TG%d ns=0x%08llx stage %d count=0x%08x count_to_timeout=0x%08x ns_to_timeout=0x%08llx\n", + __func__, ws->parent->id, ns_now, ws->cur_stage, cur_count, count_to_timeout, ns_to_timeout); + timer_mod_anticipate_ns(&ws->stage_timer, ns_now + ns_to_timeout); +} + +static void esp32_timg_wdt_cb(void *opaque) +{ + Esp32TimgWdtState *ws = (Esp32TimgWdtState*) opaque; + Esp32TimgState *s = ws->parent; + Esp32TimgWdtStageMode mode = ws->mode[ws->cur_stage]; + TIMG_DEBUG_LOG("%s: TG%d stage %d timeout mode %d\n", __func__, s->id, ws->cur_stage, mode); + if (mode == WDT_MODE_INT) { + uint32_t mask = 1 << TIMG_WDT_INT; + if (ws->level_int_en) { + s->int_raw |= mask; + if (true) { /* should be checking s->int_ena & mask, but ESP32 seems to raise interrupt regardless? */ + qemu_irq_raise(get_level_irq(s, TIMG_WDT_INT)); + } + } + if (ws->edge_int_en) { + if (s->int_ena & mask) { + qemu_irq_pulse(get_edge_irq(s, TIMG_WDT_INT)); + } + } + } else if (mode == WDT_MODE_CPURESET) { + qemu_irq_pulse(s->wdt_cpu_reset_req); + } else if (mode == WDT_MODE_SYSRESET) { + qemu_irq_pulse(s->wdt_sys_reset_req); + } + + int next_stage = (ws->cur_stage + 1) % ESP32_TIMG_WDT_STAGE_COUNT; + uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + ws->count_base = 0; + ws->cur_stage = next_stage; + ws->ns_base = ns_now; + esp32_timg_wdt_arm(ws, ns_now); +} + +static void esp32_timg_realize(DeviceState *dev, Error **errp) +{ +} + +static void esp32_timg_timer_init(Esp32TimgState *s, Esp32TimgTimerState *ts, Esp32TimgInterruptType int_type) { + ts->parent = s; + timer_init_ns(&ts->alarm_timer, QEMU_CLOCK_VIRTUAL, esp32_timg_timer_cb, ts); + ts->int_type = int_type; +} + +static void esp32_timg_init(Object *obj) +{ + Esp32TimgState *s = ESP32_TIMG(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &esp32_timg_ops, s, + TYPE_ESP32_TIMG, TIMG_REGFILE_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + qdev_init_gpio_out_named(DEVICE(sbd), s->irqs, SYSBUS_DEVICE_GPIO_IRQ, 2*TIMG_INT_MAX); + + object_property_add(obj, "apb_freq", "uint32", + NULL, + esp32_timg_set_apb_freq, + NULL, + obj, &error_abort); + + s->rtc_slow_freq_hz = 150000; + s->xtal_freq_hz = 40000000; + s->apb_freq_hz = 40000000; + + esp32_timg_timer_init(s, &s->t0, TIMG_T0_INT); + esp32_timg_timer_init(s, &s->t1, TIMG_T1_INT); + esp32_timg_timer_init(s, &s->lact, TIMG_T0_INT); + + s->wdt.parent = s; + timer_init_ns(&s->wdt.stage_timer, QEMU_CLOCK_VIRTUAL, esp32_timg_wdt_cb, &s->wdt); + qdev_init_gpio_out_named(DEVICE(sbd), &s->wdt_cpu_reset_req, ESP32_TIMG_WDT_CPU_RESET_GPIO, 1); + qdev_init_gpio_out_named(DEVICE(sbd), &s->wdt_sys_reset_req, ESP32_TIMG_WDT_SYS_RESET_GPIO, 1); +} + +static Property esp32_timg_properties[] = { + DEFINE_PROP_BOOL("wdt_disable", Esp32TimgState, wdt_disable, false), + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_timg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_timg_reset; + dc->realize = esp32_timg_realize; + dc->props = esp32_timg_properties; +} + +static const TypeInfo esp32_timg_info = { + .name = TYPE_ESP32_TIMG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32TimgState), + .instance_init = esp32_timg_init, + .class_init = esp32_timg_class_init +}; + +static void esp32_timg_register_types(void) +{ + type_register_static(&esp32_timg_info); +} + +type_init(esp32_timg_register_types) diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 29fda7870e05b..d6fadeebce037 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -74,3 +74,10 @@ nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" bcm2835_systmr_irq(bool enable) "timer irq state %u" bcm2835_systmr_read(uint64_t offset, uint64_t data) "timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 bcm2835_systmr_write(uint64_t offset, uint64_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 + +# esp32_frc_timer.c +esp32_frc_timer_read(uint64_t addr, uint32_t value) "read addr 0x%" PRIx64 " data 0x%" PRIx32 +esp32_frc_timer_write(uint64_t addr, uint32_t value) "write addr 0x%" PRIx64 " data 0x%" PRIx32 +esp32_frc_timer_update_config(uint64_t ns_now, uint32_t count_now, bool enable, bool level_int, bool autoload, uint32_t prescaler) "update now: %" PRIu64 " count: 0x%" PRIx32 " enable: %" PRIu8 " level_int: %" PRIu8 " autoload: %" PRIu8 " prescaler: %" PRIu32 +esp32_frc_timer_cb(uint64_t ns_now, uint32_t count_now) "alarm now: %" PRIu64 " count: 0x%" PRIx32 +esp32_frc_timer_update_alarm(uint64_t ns_now, uint32_t count_now, uint64_t ticks, uint64_t ns_to_alarm) "set alarm now: %" PRIu64 " count: 0x%" PRIx32 " ticks: %" PRIu64 " ns_to_alarm: %" PRIu64 diff --git a/include/hw/timer/esp32_frc_timer.h b/include/hw/timer/esp32_frc_timer.h new file mode 100644 index 0000000000000..cdb09b4cf0d71 --- /dev/null +++ b/include/hw/timer/esp32_frc_timer.h @@ -0,0 +1,49 @@ +#pragma once + +#include "hw/hw.h" +#include "hw/registerfields.h" +#include "hw/sysbus.h" +#include "hw/misc/esp32_reg.h" + +#define TYPE_ESP32_FRC_TIMER "timer.esp32.frc" +#define ESP32_FRC_TIMER(obj) OBJECT_CHECK(Esp32FrcTimerState, (obj), TYPE_ESP32_FRC_TIMER) + +typedef struct Esp32FrcTimerState { + /* private */ + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + QEMUTimer alarm_timer; + + /* properties */ + uint32_t apb_freq; + bool has_alarm; + uint32_t count_mask; + + /* state */ + uint32_t count_base; + uint64_t ns_base; + bool level_int_status; + + /* registers */ + uint32_t load_reg; + bool enable; + bool autoload; + uint32_t prescaler; + bool level_int; + uint32_t alarm_reg; +} Esp32FrcTimerState; + +REG32(FRC_TIMER_LOAD, 0x00) +REG32(FRC_TIMER_COUNT, 0x04) +REG32(FRC_TIMER_CTRL, 0x08) + FIELD(FRC_TIMER_CTRL, LEVEL_INT, 0, 1) + FIELD(FRC_TIMER_CTRL, PRESCALER, 1, 3) + FIELD(FRC_TIMER_CTRL, AUTOLOAD, 6, 1) + FIELD(FRC_TIMER_CTRL, ENABLE, 7, 1) + FIELD(FRC_TIMER_CTRL, STATUS, 8, 1) +REG32(FRC_TIMER_INT_CLR, 0x0c) +REG32(FRC_TIMER_ALARM, 0x10) + +#define ESP32_FRC_TIMER_STRIDE 0x20 diff --git a/include/hw/timer/esp32_timg.h b/include/hw/timer/esp32_timg.h new file mode 100644 index 0000000000000..dbf554ae120b8 --- /dev/null +++ b/include/hw/timer/esp32_timg.h @@ -0,0 +1,217 @@ +#pragma once + +#include "hw/hw.h" +#include "hw/registerfields.h" + +#define TYPE_ESP32_TIMG "timer.esp32.timg" +#define ESP32_TIMG(obj) OBJECT_CHECK(Esp32TimgState, (obj), TYPE_ESP32_TIMG) + +#define ESP32_TIMG_WDT_STAGE_COUNT 4 + +typedef enum Esp32TimgCalClkSel { + ESP32_TIMG_CAL_RTC_MUX = 0, + ESP32_TIMG_CAL_8MD256 = 1, + ESP32_TIMG_CAL_32K_XTAL = 2 +} Esp32TimgCalClkSel; + +typedef enum Esp32TimgInterruptType { + TIMG_T0_INT, + TIMG_T1_INT, + TIMG_WDT_INT, + TIMG_LACT_INT, + TIMG_INT_MAX +} Esp32TimgInterruptType; + +typedef struct Esp32TimgState Esp32TimgState; + +typedef struct Esp32TimgTimerState { + Esp32TimgState *parent; + uint32_t config_reg; + int divider; + bool en; + bool autoreload; + bool inc; + bool edge_int_en; + bool level_int_en; + bool alarm; + uint64_t alarm_val; + uint64_t load_val; + uint64_t count_base; + uint64_t last_val; + uint64_t ns_base; + Esp32TimgInterruptType int_type; + QEMUTimer alarm_timer; +} Esp32TimgTimerState; + +typedef enum Esp32TimgWdtStageMode { + WDT_MODE_OFF = 0, + WDT_MODE_INT = 1, + WDT_MODE_CPURESET = 2, + WDT_MODE_SYSRESET = 3 +} Esp32TimgWdtStageMode; + +typedef struct Esp32TimgWdtState { + Esp32TimgState *parent; + uint32_t config0_reg; + uint32_t config1_reg; + bool en; + bool flashboot_en; + bool level_int_en; + bool edge_int_en; + int prescale; + Esp32TimgWdtStageMode mode[ESP32_TIMG_WDT_STAGE_COUNT]; + int timeout[ESP32_TIMG_WDT_STAGE_COUNT]; + uint32_t count_base; + uint64_t ns_base; + int cur_stage; + uint32_t protect_reg; + QEMUTimer stage_timer; +} Esp32TimgWdtState; + +typedef struct Esp32TimgState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + int id; + qemu_irq irqs[2*TIMG_INT_MAX]; + qemu_irq wdt_cpu_reset_req; + qemu_irq wdt_sys_reset_req; + + Esp32TimgTimerState t0; + Esp32TimgTimerState t1; + Esp32TimgTimerState lact; + Esp32TimgWdtState wdt; + + uint32_t int_ena; + uint32_t int_raw; + + uint32_t rtc_slow_freq_hz; + uint32_t xtal_freq_hz; + uint32_t apb_freq_hz; + bool flash_boot_mode; + bool wdt_en_at_reset; + bool wdt_disable; + + bool rtc_cal_start; + bool rtc_cal_ready; + Esp32TimgCalClkSel rtc_cal_clk_sel; + uint32_t rtc_cal_max; + uint32_t rtc_cal_value; +} Esp32TimgState; + +#define ESP32_TIMG_WDT_CPU_RESET_GPIO "mwdt-cpu-reset" +#define ESP32_TIMG_WDT_SYS_RESET_GPIO "mwdt-sys-reset" + +#define RTC_CLK_CAL_FRACT 19 +#define RTC_CLK_CAL_FACTOR (1 << RTC_CLK_CAL_FRACT) + +REG32(TIMG_T0CONFIG, 0x00) + FIELD(TIMG_T0CONFIG, EN, 31, 1) + FIELD(TIMG_T0CONFIG, INCREASE, 30, 1) + FIELD(TIMG_T0CONFIG, AUTORELOAD, 29, 1) + FIELD(TIMG_T0CONFIG, DIVIDER, 13, 16) + FIELD(TIMG_T0CONFIG, EDGE_INT, 12, 1) + FIELD(TIMG_T0CONFIG, LEVEL_INT, 11, 1) + FIELD(TIMG_T0CONFIG, ALARM, 10, 1) + +REG32(TIMG_T0LO, 0x04) +REG32(TIMG_T0HI, 0x08) +REG32(TIMG_T0UPDATE, 0x0c) +REG32(TIMG_T0ALARMLO, 0x10) +REG32(TIMG_T0ALARMHI, 0x14) +REG32(TIMG_T0LOADLO, 0x18) +REG32(TIMG_T0LOADHI, 0x1c) +REG32(TIMG_T0LOAD, 0x20) + +REG32(TIMG_T1CONFIG, 0x24) + FIELD(TIMG_T1CONFIG, EN, 31, 1) + FIELD(TIMG_T1CONFIG, INCREASE, 30, 1) + FIELD(TIMG_T1CONFIG, AUTORELOAD, 29, 1) + FIELD(TIMG_T1CONFIG, DIVIDER, 13, 16) + FIELD(TIMG_T1CONFIG, EDGE_INT, 12, 1) + FIELD(TIMG_T1CONFIG, LEVEL_INT, 11, 1) + FIELD(TIMG_T1CONFIG, ALARM, 10, 1) + +REG32(TIMG_T1LO, 0x28) +REG32(TIMG_T1HI, 0x2c) +REG32(TIMG_T1UPDATE, 0x30) +REG32(TIMG_T1ALARMLO, 0x34) +REG32(TIMG_T1ALARMHI, 0x38) +REG32(TIMG_T1LOADLO, 0x3c) +REG32(TIMG_T1LOADHI, 0x40) +REG32(TIMG_T1LOAD, 0x44) + +REG32(TIMG_WDTCONFIG0, 0x48) + FIELD(TIMG_WDTCONFIG0, EN, 31, 1) + FIELD(TIMG_WDTCONFIG0, STG0, 29, 2) + FIELD(TIMG_WDTCONFIG0, STG1, 27, 2) + FIELD(TIMG_WDTCONFIG0, STG2, 25, 2) + FIELD(TIMG_WDTCONFIG0, STG3, 23, 2) + FIELD(TIMG_WDTCONFIG0, EDGE_INT, 22, 1) + FIELD(TIMG_WDTCONFIG0, LEVEL_INT, 21, 1) + FIELD(TIMG_WDTCONFIG0, FLASHBOOT_MODE_EN, 14, 1) +REG32(TIMG_WDTCONFIG1, 0x4c) + FIELD(TIMG_WDTCONFIG1, PRESCALE, 16, 16) +REG32(TIMG_WDTCONFIG2, 0x50) +REG32(TIMG_WDTCONFIG3, 0x54) +REG32(TIMG_WDTCONFIG4, 0x58) +REG32(TIMG_WDTCONFIG5, 0x5c) +REG32(TIMG_WDTFEED, 0x60) + FIELD(TIMG_WDTFEED, FEED, 31, 1) +REG32(TIMG_WDTPROTECT, 0x64) + + +REG32(TIMG_RTCCALICFG, 0x68) + FIELD(TIMG_RTCCALICFG, START, 31, 1) + FIELD(TIMG_RTCCALICFG, MAX, 16, 15) + FIELD(TIMG_RTCCALICFG, RDY, 15, 1) + FIELD(TIMG_RTCCALICFG, CLK_SEL, 13, 2) + FIELD(TIMG_RTCCALICFG, START_CYCLING, 12, 1) + +REG32(TIMG_RTCCALICFG1, 0x6c) + FIELD(TIMG_RTCCALICFG1, VALUE, 7, 25) + +REG32(TIMG_LACTCONFIG, 0x70) + FIELD(TIMG_LACTCONFIG, EN, 31, 1) + FIELD(TIMG_LACTCONFIG, INCREASE, 30, 1) + FIELD(TIMG_LACTCONFIG, AUTORELOAD, 29, 1) + FIELD(TIMG_LACTCONFIG, DIVIDER, 13, 16) + FIELD(TIMG_LACTCONFIG, EDGE_INT, 12, 1) + FIELD(TIMG_LACTCONFIG, LEVEL_INT, 11, 1) + FIELD(TIMG_LACTCONFIG, ALARM, 10, 1) +REG32(TIMG_LACTRTC, 0x74) + FIELD(TIMG_LACTRTC, STEP_LEN, 6, 26) +REG32(TIMG_LACTLO, 0x78) +REG32(TIMG_LACTHI, 0x7c) +REG32(TIMG_LACTUPDATE, 0x80) +REG32(TIMG_LACTALARMLO, 0x84) +REG32(TIMG_LACTALARMHI, 0x88) +REG32(TIMG_LACTLOADLO, 0x8c) +REG32(TIMG_LACTLOADHI, 0x90) +REG32(TIMG_LACTLOAD, 0x94) + +REG32(TIMG_INT_ENA, 0x98) + FIELD(TIMG_INT_ENA, LACT, 3, 1) + FIELD(TIMG_INT_ENA, WDT, 2, 1) + FIELD(TIMG_INT_ENA, T1, 1, 1) + FIELD(TIMG_INT_ENA, T0, 0, 1) + +REG32(TIMG_INT_RAW, 0x9c) + FIELD(TIMG_INT_RAW, LACT, 3, 1) + FIELD(TIMG_INT_RAW, WDT, 2, 1) + FIELD(TIMG_INT_RAW, T1, 1, 1) + FIELD(TIMG_INT_RAW, T0, 0, 1) + +REG32(TIMG_INT_ST, 0xa0) + FIELD(TIMG_INT_ST, LACT, 3, 1) + FIELD(TIMG_INT_ST, WDT, 2, 1) + FIELD(TIMG_INT_ST, T1, 1, 1) + FIELD(TIMG_INT_ST, T0, 0, 1) + +REG32(TIMG_INT_CLR, 0xa4) + FIELD(TIMG_INT_CLR, LACT, 3, 1) + FIELD(TIMG_INT_CLR, WDT, 2, 1) + FIELD(TIMG_INT_CLR, T1, 1, 1) + FIELD(TIMG_INT_CLR, T0, 0, 1) + +#define ESP32_TIMG_WDT_PROTECT_WORD 0x50D83AA1 From 179835a195d57f5fbb72e22a15127f6a02b017b7 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:39:56 +0200 Subject: [PATCH 14/16] hw/misc: add ESP32 register base addresses --- include/hw/misc/esp32_reg.h | 145 ++++++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 include/hw/misc/esp32_reg.h diff --git a/include/hw/misc/esp32_reg.h b/include/hw/misc/esp32_reg.h new file mode 100644 index 0000000000000..ff806c926ebbe --- /dev/null +++ b/include/hw/misc/esp32_reg.h @@ -0,0 +1,145 @@ +#pragma once + + +#define DR_REG_DPORT_BASE 0x3ff00000 +#define DR_REG_AES_BASE 0x3ff01000 +#define DR_REG_RSA_BASE 0x3ff02000 +#define DR_REG_SHA_BASE 0x3ff03000 +#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000 +#define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000 +#define DR_REG_DPORT_END 0x3ff13FFC +#define DR_REG_DPORT_APB_BASE 0x3ff40000 +#define DR_REG_UART_BASE 0x3ff40000 +#define DR_REG_SPI1_BASE 0x3ff42000 +#define DR_REG_SPI0_BASE 0x3ff43000 +#define DR_REG_GPIO_BASE 0x3ff44000 +#define DR_REG_GPIO_SD_BASE 0x3ff44f00 +#define DR_REG_FE2_BASE 0x3ff45000 +#define DR_REG_FE_BASE 0x3ff46000 +#define DR_REG_FRC_TIMER_BASE 0x3ff47000 +#define DR_REG_RTCCNTL_BASE 0x3ff48000 +#define DR_REG_RTCIO_BASE 0x3ff48400 +#define DR_REG_SENS_BASE 0x3ff48800 +#define DR_REG_RTC_I2C_BASE 0x3ff48C00 +#define DR_REG_IO_MUX_BASE 0x3ff49000 +#define DR_REG_HINF_BASE 0x3ff4B000 +#define DR_REG_UHCI1_BASE 0x3ff4C000 +#define DR_REG_ANA_BASE 0x3ff4E000 +#define DR_REG_I2S_BASE 0x3ff4F000 +#define DR_REG_UART1_BASE 0x3ff50000 +#define DR_REG_BT_BASE 0x3ff51000 +#define DR_REG_I2C_EXT_BASE 0x3ff53000 +#define DR_REG_UHCI0_BASE 0x3ff54000 +#define DR_REG_SLCHOST_BASE 0x3ff55000 +#define DR_REG_RMT_BASE 0x3ff56000 +#define DR_REG_PCNT_BASE 0x3ff57000 +#define DR_REG_SLC_BASE 0x3ff58000 +#define DR_REG_LEDC_BASE 0x3ff59000 +#define DR_REG_EFUSE_BASE 0x3ff5A000 +#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 +#define DR_REG_NRX_BASE 0x3ff5CC00 +#define DR_REG_BB_BASE 0x3ff5D000 +#define DR_REG_PWM_BASE 0x3ff5E000 +#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 +#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 +#define DR_REG_RTCMEM0_BASE 0x3ff61000 +#define DR_REG_RTCMEM1_BASE 0x3ff62000 +#define DR_REG_RTCMEM2_BASE 0x3ff63000 +#define DR_REG_SPI2_BASE 0x3ff64000 +#define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_SYSCON_BASE 0x3ff66000 +#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x3ff67000 +#define DR_REG_SDMMC_BASE 0x3ff68000 +#define DR_REG_EMAC_BASE 0x3ff69000 +#define DR_REG_CAN_BASE 0x3ff6B000 +#define DR_REG_PWM1_BASE 0x3ff6C000 +#define DR_REG_I2S1_BASE 0x3ff6D000 +#define DR_REG_UART2_BASE 0x3ff6E000 +#define DR_REG_PWM2_BASE 0x3ff6F000 +#define DR_REG_PWM3_BASE 0x3ff70000 +#define DR_REG_WDEV_BASE 0x3ff75000 + +#define APB_REG_BASE 0x60000000 + +#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/ +#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ +#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/ +#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/ +#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/ +#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ +#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/ +#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/ +#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ +#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ +#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/ +#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/ +#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/ +#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/ +#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ +#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ +#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ +#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/ +#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ +#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ +#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ +#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/ +#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/ +#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/ +#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ +#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ +#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ +#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ +#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/ +#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ +#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/ +#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/ +#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/ +#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/ +#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/ +#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/ +#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/ +#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/ +#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/ +#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/ +#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/ +#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/ +#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/ +#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/ +#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/ +#define ETS_CAN_INTR_SOURCE 45/**< interrupt of can, level*/ +#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/ +#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/ +#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/ +#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/ +#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/ +#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/ +#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/ +#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/ +#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/ +#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/ +#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/ +#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/ +#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ +#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ +#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ +#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ +#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ +#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ +#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ +#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ +#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/ +#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/ +#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/ + + +#define ESP32_DPORT_CROSSCORE_INT_COUNT 4 +#define ESP32_INT_MATRIX_OUTPUTS 32 +#define ESP32_INT_MATRIX_INPUTS 69 +#define ESP32_CPU_COUNT 2 +#define ESP32_UART_COUNT 3 +#define ESP32_FRC_COUNT 2 +#define ESP32_TIMG_COUNT 2 +#define ESP32_SPI_COUNT 4 +#define ESP32_RTC_CNTL_SCRATCH_REG_COUNT 8 + From f70cc8bfe44509b6999056110f24c4a4b718099c Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 27 Sep 2019 11:40:25 +0200 Subject: [PATCH 15/16] hw/xtensa: add ESP32 machine --- Makefile | 1 + default-configs/xtensa-softmmu.mak | 1 + hw/xtensa/Kconfig | 9 + hw/xtensa/Makefile.objs | 1 + hw/xtensa/esp32.c | 691 +++++++++++++++++++++++++++++ pc-bios/esp32-r0-rom.bin | Bin 0 -> 458752 bytes 6 files changed, 703 insertions(+) create mode 100644 hw/xtensa/esp32.c create mode 100644 pc-bios/esp32-r0-rom.bin diff --git a/Makefile b/Makefile index b437a346d71a5..e83b7e240d211 100644 --- a/Makefile +++ b/Makefile @@ -791,6 +791,7 @@ palcode-clipper \ u-boot.e500 u-boot-sam460-20100605.bin \ qemu_vga.ndrv \ edk2-licenses.txt \ +esp32-r0-rom.bin \ hppa-firmware.img \ opensbi-riscv32-virt-fw_jump.bin \ opensbi-riscv64-sifive_u-fw_jump.bin opensbi-riscv64-virt-fw_jump.bin diff --git a/default-configs/xtensa-softmmu.mak b/default-configs/xtensa-softmmu.mak index 4fe1bf00c94bd..e520bec8df9f2 100644 --- a/default-configs/xtensa-softmmu.mak +++ b/default-configs/xtensa-softmmu.mak @@ -7,3 +7,4 @@ CONFIG_SEMIHOSTING=y CONFIG_XTENSA_SIM=y CONFIG_XTENSA_VIRT=y CONFIG_XTENSA_XTFPGA=y +CONFIG_ESP32=y diff --git a/hw/xtensa/Kconfig b/hw/xtensa/Kconfig index 0740657ea58ff..2d294207581e6 100644 --- a/hw/xtensa/Kconfig +++ b/hw/xtensa/Kconfig @@ -12,3 +12,12 @@ config XTENSA_XTFPGA select OPENCORES_ETH select PFLASH_CFI01 select SERIAL + +config ESP32 + bool + select SSI + select SSI_M25P80 + select UNIMP + select OPENCORES_ETH + + diff --git a/hw/xtensa/Makefile.objs b/hw/xtensa/Makefile.objs index 2b40e1b60a0e3..89e63fe986cb7 100644 --- a/hw/xtensa/Makefile.objs +++ b/hw/xtensa/Makefile.objs @@ -4,3 +4,4 @@ obj-y += xtensa_memory.o obj-$(CONFIG_XTENSA_SIM) += sim.o obj-$(CONFIG_XTENSA_VIRT) += virt.o obj-$(CONFIG_XTENSA_XTFPGA) += xtfpga.o +obj-$(CONFIG_ESP32) += esp32.o diff --git a/hw/xtensa/esp32.c b/hw/xtensa/esp32.c new file mode 100644 index 0000000000000..20d8ea8bf16c8 --- /dev/null +++ b/hw/xtensa/esp32.c @@ -0,0 +1,691 @@ +/* + * ESP32 SoC and machine + * + * Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/sysbus.h" +#include "target/xtensa/cpu.h" +#include "hw/misc/esp32_reg.h" +#include "hw/char/esp32_uart.h" +#include "hw/gpio/esp32_gpio.h" +#include "hw/misc/esp32_dport.h" +#include "hw/misc/esp32_rtc_cntl.h" +#include "hw/misc/esp32_rng.h" +#include "hw/misc/esp32_sha.h" +#include "hw/timer/esp32_frc_timer.h" +#include "hw/timer/esp32_timg.h" +#include "hw/ssi/esp32_spi.h" +#include "hw/nvram/esp32_efuse.h" +#include "hw/xtensa/xtensa_memory.h" +#include "hw/misc/unimp.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "sysemu/sysemu.h" +#include "sysemu/reset.h" +#include "sysemu/runstate.h" +#include "sysemu/blockdev.h" +#include "sysemu/block-backend.h" +#include "exec/exec-all.h" +#include "net/net.h" +#include "elf.h" + +#define TYPE_ESP32_SOC "xtensa.esp32" +#define ESP32_SOC(obj) OBJECT_CHECK(Esp32SocState, (obj), TYPE_ESP32_SOC) + +#define TYPE_ESP32_CPU XTENSA_CPU_TYPE_NAME("esp32") + +typedef struct XtensaCPU XtensaCPU; + + +enum { + ESP32_MEMREGION_IROM, + ESP32_MEMREGION_DROM, + ESP32_MEMREGION_DRAM, + ESP32_MEMREGION_IRAM, + ESP32_MEMREGION_ICACHE0, + ESP32_MEMREGION_ICACHE1, + ESP32_MEMREGION_RTCSLOW, + ESP32_MEMREGION_RTCFAST_D, + ESP32_MEMREGION_RTCFAST_I, +}; + +static const struct MemmapEntry { + hwaddr base; + hwaddr size; +} esp32_memmap[] = { + [ESP32_MEMREGION_DROM] = { 0x3ff90000, 0x10000 }, + [ESP32_MEMREGION_IROM] = { 0x40000000, 0x70000 }, + [ESP32_MEMREGION_DRAM] = { 0x3ffae000, 0x52000 }, + [ESP32_MEMREGION_IRAM] = { 0x40080000, 0x20000 }, + [ESP32_MEMREGION_ICACHE0] = { 0x40070000, 0x8000 }, + [ESP32_MEMREGION_ICACHE1] = { 0x40078000, 0x8000 }, + [ESP32_MEMREGION_RTCSLOW] = { 0x50000000, 0x2000 }, + [ESP32_MEMREGION_RTCFAST_I] = { 0x400C0000, 0x2000 }, + [ESP32_MEMREGION_RTCFAST_D] = { 0x3ff80000, 0x2000 }, +}; + + +#define ESP32_SOC_RESET_PROCPU 0x1 +#define ESP32_SOC_RESET_APPCPU 0x2 +#define ESP32_SOC_RESET_PERIPH 0x4 +#define ESP32_SOC_RESET_DIG (ESP32_SOC_RESET_PROCPU | ESP32_SOC_RESET_APPCPU | ESP32_SOC_RESET_PERIPH) +#define ESP32_SOC_RESET_RTC 0x8 +#define ESP32_SOC_RESET_ALL (ESP32_SOC_RESET_RTC | ESP32_SOC_RESET_DIG) + + +typedef struct Esp32SocState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + XtensaCPU cpu[ESP32_CPU_COUNT]; + Esp32DportState dport; + ESP32UARTState uart[ESP32_UART_COUNT]; + Esp32GpioState gpio; + Esp32RngState rng; + Esp32RtcCntlState rtc_cntl; + Esp32FrcTimerState frc_timer[ESP32_FRC_COUNT]; + Esp32TimgState timg[ESP32_TIMG_COUNT]; + Esp32SpiState spi[ESP32_SPI_COUNT]; + Esp32ShaState sha; + Esp32EfuseState efuse; + DeviceState *eth; + + MemoryRegion cpu_specific_mem[ESP32_CPU_COUNT]; + + uint32_t requested_reset; +} Esp32SocState; + + +static void esp32_dig_reset(void *opaque, int n, int level) +{ + Esp32SocState *s = ESP32_SOC(opaque); + if (level) { + esp32_dport_clear_ill_trap_state(&s->dport); + s->requested_reset = ESP32_SOC_RESET_DIG; + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + +static void esp32_cpu_reset(void* opaque, int n, int level) +{ + Esp32SocState *s = ESP32_SOC(opaque); + if (level) { + s->requested_reset = (n == 0) ? ESP32_SOC_RESET_PROCPU : ESP32_SOC_RESET_APPCPU; + /* Use different cause for APP CPU so that its reset doesn't cause QEMU to exit, + * when -no-reboot option is given. + */ + ShutdownCause cause = (n == 0) ? SHUTDOWN_CAUSE_GUEST_RESET : SHUTDOWN_CAUSE_SUBSYSTEM_RESET; + qemu_system_reset_request(cause); + } +} + +static void esp32_timg_cpu_reset(void* opaque, int n, int level) +{ + Esp32SocState *s = ESP32_SOC(opaque); + if (level) { + s->requested_reset = (n == 0) ? ESP32_SOC_RESET_PROCPU : ESP32_SOC_RESET_APPCPU; + /* Use different cause for APP CPU so that its reset doesn't cause QEMU to exit, + * when -no-reboot option is given. + */ + ShutdownCause cause = (n == 0) ? SHUTDOWN_CAUSE_GUEST_RESET : SHUTDOWN_CAUSE_SUBSYSTEM_RESET; + s->rtc_cntl.reset_cause[n] = ESP32_TGWDT_CPU_RESET; + qemu_system_reset_request(cause); + } +} + +static void esp32_timg_sys_reset(void* opaque, int n, int level) +{ + Esp32SocState *s = ESP32_SOC(opaque); + if (level) { + esp32_dport_clear_ill_trap_state(&s->dport); + s->requested_reset = ESP32_SOC_RESET_DIG; + for (int i = 0; i < ESP32_CPU_COUNT; ++i) { + s->rtc_cntl.reset_cause[i] = ESP32_TG0WDT_SYS_RESET + n; + } + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + +static void remove_cpu_watchpoints(XtensaCPU* xcs) +{ + for (int i = 0; i < MAX_NDBREAK; ++i) { + if (xcs->env.cpu_watchpoint[i]) { + cpu_watchpoint_remove_by_ref(CPU(xcs), xcs->env.cpu_watchpoint[i]); + xcs->env.cpu_watchpoint[i] = NULL; + } + } +} + +static void esp32_soc_reset(DeviceState *dev) +{ + Esp32SocState *s = ESP32_SOC(dev); + + uint32_t strap_mode = s->gpio.strap_mode; + + bool flash_boot_mode = ((strap_mode & 0x10) || (strap_mode & 0x1f) == 0x0c); + + if (s->requested_reset == 0) { + s->requested_reset = ESP32_SOC_RESET_ALL; + } + if (s->requested_reset & ESP32_SOC_RESET_RTC) { + device_reset(DEVICE(&s->rtc_cntl)); + } + if (s->requested_reset & ESP32_SOC_RESET_PERIPH) { + device_reset(DEVICE(&s->dport)); + device_reset(DEVICE(&s->sha)); + device_reset(DEVICE(&s->gpio)); + for (int i = 0; i < ESP32_UART_COUNT; ++i) { + device_reset(DEVICE(&s->uart)); + } + for (int i = 0; i < ESP32_FRC_COUNT; ++i) { + device_reset(DEVICE(&s->frc_timer[i])); + } + for (int i = 0; i < ESP32_TIMG_COUNT; ++i) { + device_reset(DEVICE(&s->timg[i])); + } + s->timg[0].flash_boot_mode = flash_boot_mode; + for (int i = 0; i < ESP32_SPI_COUNT; ++i) { + device_reset(DEVICE(&s->spi[i])); + } + device_reset(DEVICE(&s->efuse)); + if (s->eth) { + device_reset(s->eth); + } + } + if (s->requested_reset & ESP32_SOC_RESET_PROCPU) { + xtensa_select_static_vectors(&s->cpu[0].env, s->rtc_cntl.stat_vector_sel[0]); + remove_cpu_watchpoints(&s->cpu[0]); + cpu_reset(CPU(&s->cpu[0])); + } + if (s->requested_reset & ESP32_SOC_RESET_APPCPU) { + xtensa_select_static_vectors(&s->cpu[1].env, s->rtc_cntl.stat_vector_sel[1]); + remove_cpu_watchpoints(&s->cpu[1]); + cpu_reset(CPU(&s->cpu[1])); + } + s->requested_reset = 0; +} + +static void esp32_cpu_stall(void* opaque, int n, int level) +{ + Esp32SocState *s = ESP32_SOC(opaque); + + bool stall; + if (n == 0) { + stall = s->rtc_cntl.cpu_stall_state[0]; + } else { + stall = s->rtc_cntl.cpu_stall_state[1] || s->dport.appcpu_stall_state; + } + + if (stall != s->cpu[n].env.runstall) { + xtensa_runstall(&s->cpu[n].env, stall); + } +} + +static void esp32_clk_update(void* opaque, int n, int level) +{ + Esp32SocState *s = ESP32_SOC(opaque); + if (!level) { + return; + } + + /* APB clock */ + uint32_t apb_clk_freq, cpu_clk_freq; + if (s->rtc_cntl.soc_clk == ESP32_SOC_CLK_PLL) { + const uint32_t cpu_clk_mul[] = {1, 2, 3}; + apb_clk_freq = s->rtc_cntl.pll_apb_freq; + cpu_clk_freq = cpu_clk_mul[s->dport.cpuperiod_sel] * apb_clk_freq; + } else { + apb_clk_freq = s->rtc_cntl.xtal_apb_freq; + cpu_clk_freq = apb_clk_freq; + } + qdev_prop_set_int32(DEVICE(&s->frc_timer), "apb_freq", apb_clk_freq); + qdev_prop_set_int32(DEVICE(&s->timg[0]), "apb_freq", apb_clk_freq); + qdev_prop_set_int32(DEVICE(&s->timg[1]), "apb_freq", apb_clk_freq); + *(uint32_t*)(&s->cpu[0].env.config->clock_freq_khz) = cpu_clk_freq / 1000; +} + +static void esp32_soc_add_periph_device(MemoryRegion *dest, void* dev, hwaddr dport_base_addr) +{ + MemoryRegion *mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion_overlap(dest, dport_base_addr, mr, 0); + MemoryRegion *mr_apb = g_new(MemoryRegion, 1); + char *name = g_strdup_printf("mr-apb-0x%08x", (uint32_t) dport_base_addr); + memory_region_init_alias(mr_apb, OBJECT(dev), name, mr, 0, memory_region_size(mr)); + memory_region_add_subregion_overlap(dest, dport_base_addr - DR_REG_DPORT_APB_BASE + APB_REG_BASE, mr_apb, 0); + g_free(name); +} + +static void esp32_soc_add_unimp_device(MemoryRegion *dest, const char* name, hwaddr dport_base_addr, size_t size) +{ + create_unimplemented_device(name, dport_base_addr, size); + char * name_apb = g_strdup_printf("%s-apb", name); + create_unimplemented_device(name_apb, dport_base_addr - DR_REG_DPORT_APB_BASE + APB_REG_BASE, size); + g_free(name_apb); +} + +static void esp32_soc_realize(DeviceState *dev, Error **errp) +{ + Esp32SocState *s = ESP32_SOC(dev); + MachineState *ms = MACHINE(qdev_get_machine()); + + const struct MemmapEntry *memmap = esp32_memmap; + MemoryRegion *sys_mem = get_system_memory(); + + MemoryRegion *dram = g_new(MemoryRegion, 1); + MemoryRegion *iram = g_new(MemoryRegion, 1); + MemoryRegion *drom = g_new(MemoryRegion, 1); + MemoryRegion *irom = g_new(MemoryRegion, 1); + MemoryRegion *icache0 = g_new(MemoryRegion, 1); + MemoryRegion *icache1 = g_new(MemoryRegion, 1); + MemoryRegion *rtcslow = g_new(MemoryRegion, 1); + MemoryRegion *rtcfast_i = g_new(MemoryRegion, 1); + MemoryRegion *rtcfast_d = g_new(MemoryRegion, 1); + + memory_region_init_rom(irom, NULL, "esp32.irom", + memmap[ESP32_MEMREGION_IROM].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[ESP32_MEMREGION_IROM].base, irom); + + memory_region_init_alias(drom, NULL, "esp32.drom", irom, 0x60000, memmap[ESP32_MEMREGION_DROM].size); + memory_region_add_subregion(sys_mem, memmap[ESP32_MEMREGION_DROM].base, drom); + + memory_region_init_ram(dram, NULL, "esp32.dram", + memmap[ESP32_MEMREGION_DRAM].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[ESP32_MEMREGION_DRAM].base, dram); + + memory_region_init_ram(iram, NULL, "esp32.iram", + memmap[ESP32_MEMREGION_IRAM].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[ESP32_MEMREGION_IRAM].base, iram); + + memory_region_init_ram(icache0, NULL, "esp32.icache0", + memmap[ESP32_MEMREGION_ICACHE0].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[ESP32_MEMREGION_ICACHE0].base, icache0); + + memory_region_init_ram(icache1, NULL, "esp32.icache1", + memmap[ESP32_MEMREGION_ICACHE1].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[ESP32_MEMREGION_ICACHE1].base, icache1); + + memory_region_init_ram(rtcslow, NULL, "esp32.rtcslow", + memmap[ESP32_MEMREGION_RTCSLOW].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[ESP32_MEMREGION_RTCSLOW].base, rtcslow); + + /* RTC Fast memory is only accessible by the PRO CPU */ + + memory_region_init_ram(rtcfast_i, NULL, "esp32.rtcfast_i", + memmap[ESP32_MEMREGION_RTCSLOW].size, &error_fatal); + memory_region_add_subregion(&s->cpu_specific_mem[0], memmap[ESP32_MEMREGION_RTCFAST_I].base, rtcfast_i); + + memory_region_init_alias(rtcfast_d, NULL, "esp32.rtcfast_d", rtcfast_i, 0, memmap[ESP32_MEMREGION_RTCFAST_D].size); + memory_region_add_subregion(&s->cpu_specific_mem[0], memmap[ESP32_MEMREGION_RTCFAST_D].base, rtcfast_d); + + for (int i = 0; i < ms->smp.cpus; ++i) { + object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &error_abort); + } + + object_property_set_bool(OBJECT(&s->dport), true, "realized", &error_abort); + + memory_region_add_subregion(sys_mem, DR_REG_DPORT_BASE, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dport), 0)); + qdev_connect_gpio_out_named(DEVICE(&s->dport), ESP32_DPORT_APPCPU_RESET_GPIO, 0, + qdev_get_gpio_in_named(dev, ESP32_RTC_CPU_RESET_GPIO, 1)); + qdev_connect_gpio_out_named(DEVICE(&s->dport), ESP32_DPORT_APPCPU_STALL_GPIO, 0, + qdev_get_gpio_in_named(dev, ESP32_RTC_CPU_STALL_GPIO, 1)); + qdev_connect_gpio_out_named(DEVICE(&s->rtc_cntl), ESP32_DPORT_CLK_UPDATE_GPIO, 0, + qdev_get_gpio_in_named(dev, ESP32_RTC_CLK_UPDATE_GPIO, 0)); + DeviceState* intmatrix_dev = DEVICE(&s->dport.intmatrix); + + if (s->dport.flash_blk) { + for (int i = 0; i < ESP32_CPU_COUNT; ++i) { + Esp32CacheRegionState *drom0 = &s->dport.cache_state[i].drom0; + memory_region_add_subregion_overlap(&s->cpu_specific_mem[i], drom0->base, &drom0->illegal_access_trap_mem, -2); + memory_region_add_subregion_overlap(&s->cpu_specific_mem[i], drom0->base, &drom0->mem, -1); + Esp32CacheRegionState *iram0 = &s->dport.cache_state[i].iram0; + memory_region_add_subregion_overlap(&s->cpu_specific_mem[i], iram0->base, &iram0->illegal_access_trap_mem, -2); + memory_region_add_subregion_overlap(&s->cpu_specific_mem[i], iram0->base, &iram0->mem, -1); + } + } + + object_property_set_bool(OBJECT(&s->sha), true, "realized", &error_abort); + esp32_soc_add_periph_device(sys_mem, &s->sha, DR_REG_SHA_BASE); + + object_property_set_bool(OBJECT(&s->rtc_cntl), true, "realized", &error_abort); + esp32_soc_add_periph_device(sys_mem, &s->rtc_cntl, DR_REG_RTCCNTL_BASE); + + qdev_connect_gpio_out_named(DEVICE(&s->rtc_cntl), ESP32_RTC_DIG_RESET_GPIO, 0, + qdev_get_gpio_in_named(dev, ESP32_RTC_DIG_RESET_GPIO, 0)); + qdev_connect_gpio_out_named(DEVICE(&s->rtc_cntl), ESP32_RTC_CLK_UPDATE_GPIO, 0, + qdev_get_gpio_in_named(dev, ESP32_RTC_CLK_UPDATE_GPIO, 0)); + for (int i = 0; i < ms->smp.cpus; ++i) { + qdev_connect_gpio_out_named(DEVICE(&s->rtc_cntl), ESP32_RTC_CPU_RESET_GPIO, i, + qdev_get_gpio_in_named(dev, ESP32_RTC_CPU_RESET_GPIO, i)); + qdev_connect_gpio_out_named(DEVICE(&s->rtc_cntl), ESP32_RTC_CPU_STALL_GPIO, i, + qdev_get_gpio_in_named(dev, ESP32_RTC_CPU_STALL_GPIO, i)); + } + + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &error_abort); + esp32_soc_add_periph_device(sys_mem, &s->gpio, DR_REG_GPIO_BASE); + + for (int i = 0; i < ESP32_UART_COUNT; ++i) { + const hwaddr uart_base[] = {DR_REG_UART_BASE, DR_REG_UART1_BASE, DR_REG_UART2_BASE}; + object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &error_abort); + esp32_soc_add_periph_device(sys_mem, &s->uart[i], uart_base[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + qdev_get_gpio_in(intmatrix_dev, ETS_UART0_INTR_SOURCE + i)); + } + + for (int i = 0; i < ESP32_FRC_COUNT; ++i) { + object_property_set_bool(OBJECT(&s->frc_timer[i]), true, "realized", &error_abort); + + esp32_soc_add_periph_device(sys_mem, &s->frc_timer[i], DR_REG_FRC_TIMER_BASE + i * ESP32_FRC_TIMER_STRIDE); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->frc_timer[i]), 0, + qdev_get_gpio_in(intmatrix_dev, ETS_TIMER1_INTR_SOURCE + i)); + } + + for (int i = 0; i < ESP32_TIMG_COUNT; ++i) { + s->timg[i].id = i; + + const hwaddr timg_base[] = {DR_REG_TIMERGROUP0_BASE, DR_REG_TIMERGROUP1_BASE}; + object_property_set_bool(OBJECT(&s->timg[i]), true, "realized", &error_abort); + + esp32_soc_add_periph_device(sys_mem, &s->timg[i], timg_base[i]); + + int timg_level_int[] = { ETS_TG0_T0_LEVEL_INTR_SOURCE, ETS_TG1_T0_LEVEL_INTR_SOURCE }; + int timg_edge_int[] = { ETS_TG0_T0_EDGE_INTR_SOURCE, ETS_TG1_T0_EDGE_INTR_SOURCE }; + for (Esp32TimgInterruptType it = TIMG_T0_INT; it < TIMG_INT_MAX; ++it) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timg[i]), it, qdev_get_gpio_in(intmatrix_dev, timg_level_int[i] + it)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timg[i]), TIMG_INT_MAX + it, qdev_get_gpio_in(intmatrix_dev, timg_edge_int[i] + it)); + } + + qdev_connect_gpio_out_named(DEVICE(&s->timg[i]), ESP32_TIMG_WDT_CPU_RESET_GPIO, 0, + qdev_get_gpio_in_named(dev, ESP32_TIMG_WDT_CPU_RESET_GPIO, i)); + qdev_connect_gpio_out_named(DEVICE(&s->timg[i]), ESP32_TIMG_WDT_SYS_RESET_GPIO, 0, + qdev_get_gpio_in_named(dev, ESP32_TIMG_WDT_SYS_RESET_GPIO, i)); + } + s->timg[0].wdt_en_at_reset = true; + + for (int i = 0; i < ESP32_SPI_COUNT; ++i) { + const hwaddr spi_base[] = { + DR_REG_SPI0_BASE, DR_REG_SPI1_BASE, DR_REG_SPI2_BASE, DR_REG_SPI3_BASE + }; + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &error_abort); + + esp32_soc_add_periph_device(sys_mem, &s->spi[i], spi_base[i]); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + qdev_get_gpio_in(intmatrix_dev, ETS_SPI0_INTR_SOURCE + i)); + } + + object_property_set_bool(OBJECT(&s->rng), true, "realized", &error_abort); + esp32_soc_add_periph_device(sys_mem, &s->rng, ESP32_RNG_BASE); + + object_property_set_bool(OBJECT(&s->efuse), true, "realized", &error_abort); + esp32_soc_add_periph_device(sys_mem, &s->efuse, DR_REG_EFUSE_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->efuse), 0, + qdev_get_gpio_in(intmatrix_dev, ETS_EFUSE_INTR_SOURCE)); + + + esp32_soc_add_unimp_device(sys_mem, "esp32.analog", DR_REG_ANA_BASE, 0x1000); + esp32_soc_add_unimp_device(sys_mem, "esp32.rtcio", DR_REG_RTCIO_BASE, 0x400); + esp32_soc_add_unimp_device(sys_mem, "esp32.rtcio", DR_REG_SENS_BASE, 0x400); + esp32_soc_add_unimp_device(sys_mem, "esp32.iomux", DR_REG_IO_MUX_BASE, 0x2000); + esp32_soc_add_unimp_device(sys_mem, "esp32.hinf", DR_REG_HINF_BASE, 0x1000); + esp32_soc_add_unimp_device(sys_mem, "esp32.slc", DR_REG_SLC_BASE, 0x1000); + esp32_soc_add_unimp_device(sys_mem, "esp32.slchost", DR_REG_SLCHOST_BASE, 0x1000); + esp32_soc_add_unimp_device(sys_mem, "esp32.apbctrl", DR_REG_APB_CTRL_BASE, 0x1000); + esp32_soc_add_unimp_device(sys_mem, "esp32.i2s0", DR_REG_I2S_BASE, 0x1000); + esp32_soc_add_unimp_device(sys_mem, "esp32.i2s1", DR_REG_I2S1_BASE, 0x1000); + esp32_soc_add_unimp_device(sys_mem, "esp32.i2c0", DR_REG_I2C_EXT_BASE, 0x1000); + esp32_soc_add_unimp_device(sys_mem, "esp32.i2c1", DR_REG_I2C1_EXT_BASE, 0x1000); + + qemu_register_reset((QEMUResetHandler*) esp32_soc_reset, dev); +} + +static void esp32_soc_init(Object *obj) +{ + Esp32SocState *s = ESP32_SOC(obj); + MachineState *ms = MACHINE(qdev_get_machine()); + char name[16]; + + MemoryRegion *system_memory = get_system_memory(); + + for (int i = 0; i < ms->smp.cpus; ++i) { + snprintf(name, sizeof(name), "cpu%d", i); + object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]), TYPE_ESP32_CPU, &error_abort, NULL); + + const uint32_t cpuid[ESP32_CPU_COUNT] = { 0xcdcd, 0xabab }; + s->cpu[i].env.sregs[PRID] = cpuid[i]; + + snprintf(name, sizeof(name), "cpu%d-mem", i); + memory_region_init(&s->cpu_specific_mem[i], NULL, name, UINT32_MAX); + + CPUState* cs = CPU(&s->cpu[i]); + cs->num_ases = 1; + cpu_address_space_init(cs, 0, "cpu-memory", &s->cpu_specific_mem[i]); + + MemoryRegion *cpu_view_sysmem = g_new(MemoryRegion, 1); + snprintf(name, sizeof(name), "cpu%d-sysmem", i); + memory_region_init_alias(cpu_view_sysmem, NULL, name, system_memory, 0, UINT32_MAX); + memory_region_add_subregion_overlap(&s->cpu_specific_mem[i], 0, cpu_view_sysmem, 0); + cs->memory = &s->cpu_specific_mem[i]; + } + + for (int i = 0; i < ESP32_UART_COUNT; ++i) { + snprintf(name, sizeof(name), "uart%d", i); + object_initialize_child(obj, name, &s->uart[i], sizeof(s->uart[i]), + TYPE_ESP32_UART, &error_abort, NULL); + } + + object_property_add_alias(obj, "serial0", OBJECT(&s->uart[0]), "chardev", + &error_abort); + + object_initialize_child(obj, "gpio", &s->gpio, sizeof(s->gpio), + TYPE_ESP32_GPIO, &error_abort, NULL); + + object_initialize_child(obj, "dport", &s->dport, sizeof(s->dport), + TYPE_ESP32_DPORT, &error_abort, NULL); + + object_initialize_child(obj, "rtc_cntl", &s->rtc_cntl, sizeof(s->rtc_cntl), + TYPE_ESP32_RTC_CNTL, &error_abort, NULL); + + for (int i = 0; i < ESP32_FRC_COUNT; ++i) { + snprintf(name, sizeof(name), "frc%d", i); + object_initialize_child(obj, name, &s->frc_timer[i], sizeof(s->frc_timer[i]), + TYPE_ESP32_FRC_TIMER, &error_abort, NULL); + } + + for (int i = 0; i < ESP32_TIMG_COUNT; ++i) { + snprintf(name, sizeof(name), "timg%d", i); + object_initialize_child(obj, name, &s->timg[i], sizeof(s->timg[i]), + TYPE_ESP32_TIMG, &error_abort, NULL); + } + + for (int i = 0; i < ESP32_SPI_COUNT; ++i) { + snprintf(name, sizeof(name), "spi%d", i); + object_initialize_child(obj, name, &s->spi[i], sizeof(s->spi[i]), + TYPE_ESP32_SPI, &error_abort, NULL); + } + + object_initialize_child(obj, "rng", &s->rng, sizeof(s->rng), + TYPE_ESP32_RNG, &error_abort, NULL); + + object_initialize_child(obj, "sha", &s->sha, sizeof(s->sha), + TYPE_ESP32_SHA, &error_abort, NULL); + + object_initialize_child(obj, "efuse", &s->efuse, sizeof(s->efuse), + TYPE_ESP32_EFUSE, &error_abort, NULL); + + + qdev_init_gpio_in_named(DEVICE(s), esp32_dig_reset, ESP32_RTC_DIG_RESET_GPIO, 1); + qdev_init_gpio_in_named(DEVICE(s), esp32_cpu_reset, ESP32_RTC_CPU_RESET_GPIO, ESP32_CPU_COUNT); + qdev_init_gpio_in_named(DEVICE(s), esp32_cpu_stall, ESP32_RTC_CPU_STALL_GPIO, ESP32_CPU_COUNT); + qdev_init_gpio_in_named(DEVICE(s), esp32_clk_update, ESP32_RTC_CLK_UPDATE_GPIO, 1); + qdev_init_gpio_in_named(DEVICE(s), esp32_timg_cpu_reset, ESP32_TIMG_WDT_CPU_RESET_GPIO, 2); + qdev_init_gpio_in_named(DEVICE(s), esp32_timg_sys_reset, ESP32_TIMG_WDT_SYS_RESET_GPIO, 2); +} + +static Property esp32_soc_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void esp32_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = esp32_soc_reset; + dc->realize = esp32_soc_realize; + dc->props = esp32_soc_properties; +} + +static const TypeInfo esp32_soc_info = { + .name = TYPE_ESP32_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Esp32SocState), + .instance_init = esp32_soc_init, + .class_init = esp32_soc_class_init +}; + +static void esp32_soc_register_types(void) +{ + type_register_static(&esp32_soc_info); +} + +type_init(esp32_soc_register_types) + + +static uint64_t translate_phys_addr(void *opaque, uint64_t addr) +{ + XtensaCPU *cpu = opaque; + + return cpu_get_phys_page_debug(CPU(cpu), addr); +} + +static void esp32_machine_init_spi_flash(MachineState *machine, Esp32SocState *s, BlockBackend* blk) +{ + /* "main" flash chip is attached to SPI1 */ + DeviceState *spi_master = DEVICE(&s->spi[1]); + SSIBus* spi_bus = (SSIBus *)qdev_get_child_bus(spi_master, "spi"); + DeviceState *flash_dev = ssi_create_slave_no_init(spi_bus, "gd25q32"); + qdev_prop_set_drive(flash_dev, "drive", blk, &error_fatal); + qdev_init_nofail(flash_dev); + qdev_connect_gpio_out_named(spi_master, SSI_GPIO_CS, 0, + qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0)); +} + +static void esp32_machine_init_openeth(Esp32SocState *ss) +{ + SysBusDevice *sbd; + NICInfo *nd = &nd_table[0]; + MemoryRegion* sys_mem = get_system_memory(); + hwaddr reg_base = DR_REG_EMAC_BASE; + hwaddr desc_base = reg_base + 0x400; + qemu_irq irq = qdev_get_gpio_in(DEVICE(&ss->dport.intmatrix), ETS_ETH_MAC_INTR_SOURCE); + + const char* type_openeth = "open_eth"; + if (nd->used && nd->model && strcmp(nd->model, type_openeth) == 0) { + DeviceState* open_eth_dev = qdev_create(NULL, type_openeth); + ss->eth = open_eth_dev; + qdev_set_nic_properties(open_eth_dev, nd); + qdev_init_nofail(open_eth_dev); + + sbd = SYS_BUS_DEVICE(open_eth_dev); + sysbus_connect_irq(sbd, 0, irq); + memory_region_add_subregion(sys_mem, reg_base, sysbus_mmio_get_region(sbd, 0)); + memory_region_add_subregion(sys_mem, desc_base, sysbus_mmio_get_region(sbd, 1)); + } +} + + +static void esp32_machine_inst_init(MachineState *machine) +{ + Esp32SocState *s = g_new0(Esp32SocState, 1); + + BlockBackend* blk = NULL; + DriveInfo *dinfo = drive_get_next(IF_MTD); + if (dinfo) { + qemu_log("Adding SPI flash device\n"); + blk = blk_by_legacy_dinfo(dinfo); + } else { + qemu_log("Not initializing SPI Flash\n"); + } + + object_initialize_child(OBJECT(machine), "soc", s, sizeof(*s), + TYPE_ESP32_SOC, &error_abort, NULL); + + if (blk) { + s->dport.flash_blk = blk; + } + qdev_prop_set_chr(DEVICE(s), "serial0", serial_hd(0)); + + object_property_set_bool(OBJECT(s), true, "realized", &error_abort); + + if (blk) { + esp32_machine_init_spi_flash(machine, s, blk); + } + + esp32_machine_init_openeth(s); + + /* Need MMU initialized prior to ELF loading, + * so that ELF gets loaded into virtual addresses + */ + cpu_reset(CPU(&s->cpu[0])); + + const char *load_elf_filename = NULL; + if (machine->firmware) { + load_elf_filename = machine->firmware; + } + if (machine->kernel_filename) { + qemu_log("Warning: both -bios and -kernel arguments specified. Only loading the the -kernel file.\n"); + load_elf_filename = machine->kernel_filename; + } + + if (load_elf_filename) { + uint64_t elf_entry; + uint64_t elf_lowaddr; + int success = load_elf(load_elf_filename, NULL, + translate_phys_addr, &s->cpu[0], + &elf_entry, &elf_lowaddr, + NULL, 0, EM_XTENSA, 0, 0); + if (success > 0) { + s->cpu[0].env.pc = elf_entry; + } + } else { + char *rom_binary = qemu_find_file(QEMU_FILE_TYPE_BIOS, "esp32-r0-rom.bin"); + if (rom_binary == NULL) { + error_report("Error: -bios argument not set, and ROM code binary not found"); + exit(1); + } + + int size = load_image_targphys(rom_binary, esp32_memmap[ESP32_MEMREGION_IROM].base, esp32_memmap[ESP32_MEMREGION_IROM].size); + if (size < 0) { + error_report("Error: could not load ROM binary '%s'", rom_binary); + exit(1); + } + g_free(rom_binary); + } +} + +/* Initialize machine type */ +static void esp32_machine_init(MachineClass *mc) +{ + mc->desc = "Espressif ESP32 machine"; + mc->init = esp32_machine_inst_init; + mc->max_cpus = 2; + mc->default_cpus = 2; +} + +DEFINE_MACHINE("esp32", esp32_machine_init) + diff --git a/pc-bios/esp32-r0-rom.bin b/pc-bios/esp32-r0-rom.bin new file mode 100644 index 0000000000000000000000000000000000000000..8f0bb3fa676368b2cc2fb38b8d7fd7012220dab4 GIT binary patch literal 458752 zcmce;3tSXOwlH4Z^I#sWnE^#~H0hZU98i;H#s~OVX9h%2lN~@1NwNzVz`X9Fi_v7w zO*0x847odui2`xI?ZFU{NHSm^B*vQt4M7+0qDfp$Viq;Hn#Am=h=4$Ur@BE+cJKGQ zkKg~#kDl&2b?VfqQ>RXyI#u21lN8+-DRfT?b0Y=KLCE5WOHIxVJwc!oVJKM^WbO1t z867vrZex;E=%4(3qSk$(rhC-P4K&$0h8eO#>nYzloPg&9t<+f!Vwl$@NDqM{U*P4RkDI4&jd|KjDiT6b1WUr`63 z{$aI!h1&J7I_F7s(eKpkOKR_HYVJ*S;Go1yvV3I8&l#Xk=5plEf&Yy({n`Jr{OAA6 z@?ZQf%byC{;zp@RDG2|KR^LI@&A;>fKYDVYq>=ww)nav_CxmE6d}?gDKwpwERxVDK zlFP~dN1XhR3fcdc{42u{dh<<$;!tpjAP6svGGV{ZXfnZb_hC7*_kWJ;9bX{(DmAiO zG?0cXSvj&~9fj;G;eI#cB!|$qVf6R1*zbh-K0W+e&FJQDRmRH#ZPW2GWc-`Jd@o~| z;tErzOidbl1p04bQ`4EXVRSAso)=Qj3%M5rO7=YID$xC-$+53>AsQ_XE)KeE{Cfu` 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1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/esp32_timg.c b/hw/timer/esp32_timg.c index 0590cc488758d..ef368ae8b4eef 100644 --- a/hw/timer/esp32_timg.c +++ b/hw/timer/esp32_timg.c @@ -159,7 +159,7 @@ static void esp32_timg_write(void *opaque, hwaddr addr, ts = &s->t0; } else if (addr <= A_TIMG_T1LOAD) { ts = &s->t1; - } else if (addr >= A_TIMG_LACTCONFIG && addr < A_TIMG_LACTLOAD) { + } else if (addr >= A_TIMG_LACTCONFIG && addr <= A_TIMG_LACTLOAD) { ts = &s->lact; }